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* [PATCH v4 00/14] Add device tree support for sc7180
@ 2019-11-06  6:50 Rajendra Nayak
  2019-11-06  6:50 ` [PATCH v4 01/14] dt-bindings: qcom: Add SC7180 bindings Rajendra Nayak
                   ` (13 more replies)
  0 siblings, 14 replies; 40+ messages in thread
From: Rajendra Nayak @ 2019-11-06  6:50 UTC (permalink / raw)
  To: agross, robh+dt, bjorn.andersson
  Cc: linux-arm-msm, devicetree, linux-kernel, mka, swboyd, Rajendra Nayak

Changes in v4:
* Rebased on top of Rob;s for-next
* reorderd patches to take care of pdc dependency
* Updated pdc binding to use a soc specific and soc independent compatible
* Other updates based on v3 feedback, changes listed in each patch 

Changes in v3:
* PATCH 2/11: Updated the qup and uart lables to be consistent
with the naming convention followed in sdm845 as suggested
by Matthias
* Dropped 2 patches from v2 which added the new compatible and
binding updates for sc7180 pdc and reused sdm845 compatible instead
as suggested by Marc Z

This series adds DT support for basic peripherals on qualcomm's sc7180 SoC,
drivers for which are already upstream.

The series has a dependency on gcc clock driver patches [1]
to merge first

[1] https://www.spinics.net/lists/linux-clk/msg41851.html

Kiran Gunda (3):
  arm64: dts: qcom: sc7180: Add SPMI PMIC arbiter device
  arm64: dts: qcom: pm6150: Add PM6150/PM6150L PMIC peripherals
  arm64: dts: qcom: sc7180-idp: Add RPMh regulators

Maulik Shah (3):
  arm64: dts: qcom: sc7180: Add cmd_db reserved area
  arm64: dts: qcom: sc7180: Add rpmh-rsc node
  arm64: dts: qcom: sc7180: Add pdc interrupt controller

Rajendra Nayak (5):
  dt-bindings: qcom: Add SC7180 bindings
  arm64: dts: sc7180: Add minimal dts/dtsi files for SC7180 soc
  dt-bindings: arm-smmu: update binding for qcom sc7180 SoC
  drivers: irqchip: qcom-pdc: Move to an SoC independent compatible
  dt-bindings: qcom,pdc: Add compatible for sc7180

Roja Rani Yarubandi (1):
  arm64: dts: sc7180: Add qupv3_0 and qupv3_1

Taniya Das (1):
  arm64: dts: qcom: SC7180: Add node for rpmhcc clock driver

Vivek Gautam (1):
  arm64: dts: sc7180: Add device node for apps_smmu

 .../devicetree/bindings/arm/qcom.yaml         |    6 +
 .../interrupt-controller/qcom,pdc.txt         |    3 +-
 .../devicetree/bindings/iommu/arm,smmu.yaml   |    1 +
 arch/arm64/boot/dts/qcom/Makefile             |    1 +
 arch/arm64/boot/dts/qcom/pm6150.dtsi          |   72 ++
 arch/arm64/boot/dts/qcom/pm6150l.dtsi         |   31 +
 arch/arm64/boot/dts/qcom/sc7180-idp.dts       |  402 ++++++
 arch/arm64/boot/dts/qcom/sc7180.dtsi          | 1133 +++++++++++++++++
 drivers/irqchip/qcom-pdc.c                    |    2 +-
 9 files changed, 1649 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm64/boot/dts/qcom/pm6150.dtsi
 create mode 100644 arch/arm64/boot/dts/qcom/pm6150l.dtsi
 create mode 100644 arch/arm64/boot/dts/qcom/sc7180-idp.dts
 create mode 100644 arch/arm64/boot/dts/qcom/sc7180.dtsi

-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation


^ permalink raw reply	[flat|nested] 40+ messages in thread

* [PATCH v4 01/14] dt-bindings: qcom: Add SC7180 bindings
  2019-11-06  6:50 [PATCH v4 00/14] Add device tree support for sc7180 Rajendra Nayak
@ 2019-11-06  6:50 ` Rajendra Nayak
  2019-11-07  0:48   ` Rob Herring
  2019-11-07 17:43   ` Stephen Boyd
  2019-11-06  6:50 ` [PATCH v4 02/14] arm64: dts: sc7180: Add minimal dts/dtsi files for SC7180 soc Rajendra Nayak
                   ` (12 subsequent siblings)
  13 siblings, 2 replies; 40+ messages in thread
From: Rajendra Nayak @ 2019-11-06  6:50 UTC (permalink / raw)
  To: agross, robh+dt, bjorn.andersson
  Cc: linux-arm-msm, devicetree, linux-kernel, mka, swboyd,
	Rajendra Nayak, Vinod Koul

Add a SoC string 'sc7180' for the qualcomm SC7180 SoC.
Also add a new board type 'idp'

Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
---
v4: Added schema for sc7180 IDP board

 Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
index e39d8f02e33c..11c3c02d8a80 100644
--- a/Documentation/devicetree/bindings/arm/qcom.yaml
+++ b/Documentation/devicetree/bindings/arm/qcom.yaml
@@ -36,6 +36,7 @@ description: |
   	mdm9615
   	ipq8074
   	sdm845
+  	sc7180
 
   The 'board' element must be one of the following strings:
 
@@ -46,6 +47,7 @@ description: |
   	sbc
   	hk01
   	qrd
+  	idp
 
   The 'soc_version' and 'board_version' elements take the form of v<Major>.<Minor>
   where the minor number may be omitted when it's zero, i.e.  v1.0 is the same
@@ -144,4 +146,8 @@ properties:
               - qcom,ipq8074-hk01
           - const: qcom,ipq8074
 
+      - items:
+          - enum:
+              - qcom,sc7180-idp
+          - const: qcom,sc7180
 ...
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation


^ permalink raw reply	[flat|nested] 40+ messages in thread

* [PATCH v4 02/14] arm64: dts: sc7180: Add minimal dts/dtsi files for SC7180 soc
  2019-11-06  6:50 [PATCH v4 00/14] Add device tree support for sc7180 Rajendra Nayak
  2019-11-06  6:50 ` [PATCH v4 01/14] dt-bindings: qcom: Add SC7180 bindings Rajendra Nayak
@ 2019-11-06  6:50 ` Rajendra Nayak
  2019-11-07 17:46   ` Stephen Boyd
  2019-11-06  6:50 ` [PATCH v4 03/14] dt-bindings: arm-smmu: update binding for qcom sc7180 SoC Rajendra Nayak
                   ` (11 subsequent siblings)
  13 siblings, 1 reply; 40+ messages in thread
From: Rajendra Nayak @ 2019-11-06  6:50 UTC (permalink / raw)
  To: agross, robh+dt, bjorn.andersson
  Cc: linux-arm-msm, devicetree, linux-kernel, mka, swboyd,
	Rajendra Nayak, Taniya Das

Add skeletal sc7180 SoC dtsi and idp board dts files.

Co-developed-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
---
v4:
* renamed uart10 to uart8
* dropped clock-output-names for xo_board

 arch/arm64/boot/dts/qcom/Makefile       |   1 +
 arch/arm64/boot/dts/qcom/sc7180-idp.dts |  47 ++++
 arch/arm64/boot/dts/qcom/sc7180.dtsi    | 299 ++++++++++++++++++++++++
 3 files changed, 347 insertions(+)
 create mode 100644 arch/arm64/boot/dts/qcom/sc7180-idp.dts
 create mode 100644 arch/arm64/boot/dts/qcom/sc7180.dtsi

diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index 6498a1ec893f..7a5c2f7fe37f 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -13,6 +13,7 @@ dtb-$(CONFIG_ARCH_QCOM)	+= msm8998-asus-novago-tp370ql.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= msm8998-hp-envy-x2.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= msm8998-lenovo-miix-630.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= msm8998-mtp.dtb
+dtb-$(CONFIG_ARCH_QCOM)	+= sc7180-idp.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= sdm845-cheza-r1.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= sdm845-cheza-r2.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= sdm845-cheza-r3.dtb
diff --git a/arch/arm64/boot/dts/qcom/sc7180-idp.dts b/arch/arm64/boot/dts/qcom/sc7180-idp.dts
new file mode 100644
index 000000000000..c637a4a647f8
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sc7180-idp.dts
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * SC7180 IDP board device tree source
+ *
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "sc7180.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. SC7180 IDP";
+	compatible = "qcom,sc7180-idp";
+
+	aliases {
+		serial0 = &uart8;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&qupv3_id_1 {
+	status = "okay";
+};
+
+&uart8 {
+	status = "okay";
+};
+
+/* PINCTRL - additions to nodes defined in sc7180.dtsi */
+
+&qup_uart8_default {
+	pinconf-tx {
+		pins = "gpio44";
+		drive-strength = <2>;
+		bias-disable;
+	};
+
+	pinconf-rx {
+		pins = "gpio45";
+		drive-strength = <2>;
+		bias-pull-up;
+	};
+};
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
new file mode 100644
index 000000000000..17870dd67390
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -0,0 +1,299 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * SC7180 SoC device tree source
+ *
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ */
+
+#include <dt-bindings/clock/qcom,gcc-sc7180.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	interrupt-parent = <&intc>;
+
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	chosen { };
+
+	clocks {
+		xo_board: xo-board {
+			compatible = "fixed-clock";
+			clock-frequency = <38400000>;
+			#clock-cells = <0>;
+		};
+
+		sleep_clk: sleep-clk {
+			compatible = "fixed-clock";
+			clock-frequency = <32764>;
+			clock-output-names = "sleep_clk";
+			#clock-cells = <0>;
+		};
+	};
+
+	cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		CPU0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x0>;
+			enable-method = "psci";
+			next-level-cache = <&L2_0>;
+			L2_0: l2-cache {
+				compatible = "cache";
+				next-level-cache = <&L3_0>;
+				L3_0: l3-cache {
+					compatible = "cache";
+				};
+			};
+		};
+
+		CPU1: cpu@100 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x100>;
+			enable-method = "psci";
+			next-level-cache = <&L2_100>;
+			L2_100: l2-cache {
+				compatible = "cache";
+				next-level-cache = <&L3_0>;
+			};
+		};
+
+		CPU2: cpu@200 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x200>;
+			enable-method = "psci";
+			next-level-cache = <&L2_200>;
+			L2_200: l2-cache {
+				compatible = "cache";
+				next-level-cache = <&L3_0>;
+			};
+		};
+
+		CPU3: cpu@300 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x300>;
+			enable-method = "psci";
+			next-level-cache = <&L2_300>;
+			L2_300: l2-cache {
+				compatible = "cache";
+				next-level-cache = <&L3_0>;
+			};
+		};
+
+		CPU4: cpu@400 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x400>;
+			enable-method = "psci";
+			next-level-cache = <&L2_400>;
+			L2_400: l2-cache {
+				compatible = "cache";
+				next-level-cache = <&L3_0>;
+			};
+		};
+
+		CPU5: cpu@500 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x500>;
+			enable-method = "psci";
+			next-level-cache = <&L2_500>;
+			L2_500: l2-cache {
+				compatible = "cache";
+				next-level-cache = <&L3_0>;
+			};
+		};
+
+		CPU6: cpu@600 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x600>;
+			enable-method = "psci";
+			next-level-cache = <&L2_600>;
+			L2_600: l2-cache {
+				compatible = "cache";
+				next-level-cache = <&L3_0>;
+			};
+		};
+
+		CPU7: cpu@700 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x700>;
+			enable-method = "psci";
+			next-level-cache = <&L2_700>;
+			L2_700: l2-cache {
+				compatible = "cache";
+				next-level-cache = <&L3_0>;
+			};
+		};
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		/* We expect the bootloader to fill in the size */
+		reg = <0 0x80000000 0 0>;
+	};
+
+	pmu {
+		compatible = "arm,armv8-pmuv3";
+		interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	psci {
+		compatible = "arm,psci-1.0";
+		method = "smc";
+	};
+
+	soc: soc {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges = <0 0 0 0 0x10 0>;
+		dma-ranges = <0 0 0 0 0x10 0>;
+		compatible = "simple-bus";
+
+		gcc: clock-controller@100000 {
+			compatible = "qcom,gcc-sc7180";
+			reg = <0 0x00100000 0 0x1f0000>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			#power-domain-cells = <1>;
+		};
+
+		qupv3_id_1: geniqup@ac0000 {
+			compatible = "qcom,geni-se-qup";
+			reg = <0 0x00ac0000 0 0x6000>;
+			clock-names = "m-ahb", "s-ahb";
+			clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+				 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+			status = "disabled";
+
+			uart8: serial@a88000 {
+				compatible = "qcom,geni-debug-uart";
+				reg = <0 0x00a88000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_uart8_default>;
+				interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+		};
+
+		tlmm: pinctrl@3500000 {
+			compatible = "qcom,sc7180-pinctrl";
+			reg = <0 0x03500000 0 0x300000>,
+			      <0 0x03900000 0 0x300000>,
+			      <0 0x03d00000 0 0x300000>;
+			reg-names = "west", "north", "south";
+			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			gpio-ranges = <&tlmm 0 0 120>;
+
+			qup_uart8_default: qup-uart8-default {
+				pinmux {
+					pins = "gpio44", "gpio45";
+					function = "qup12";
+				};
+			};
+		};
+
+		intc: interrupt-controller@17a00000 {
+			compatible = "arm,gic-v3";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+			#interrupt-cells = <3>;
+			interrupt-controller;
+			reg = <0 0x17a00000 0 0x10000>,     /* GICD */
+			      <0 0x17a60000 0 0x100000>;    /* GICR * 8 */
+			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+
+			gic-its@17a40000 {
+				compatible = "arm,gic-v3-its";
+				msi-controller;
+				#msi-cells = <1>;
+				reg = <0 0x17a40000 0 0x20000>;
+				status = "disabled";
+			};
+		};
+
+		timer@17c20000{
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+			compatible = "arm,armv7-timer-mem";
+			reg = <0 0x17c20000 0 0x1000>;
+
+			frame@17c21000 {
+				frame-number = <0>;
+				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+				reg = <0 0x17c21000 0 0x1000>,
+				      <0 0x17c22000 0 0x1000>;
+			};
+
+			frame@17c23000 {
+				frame-number = <1>;
+				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+				reg = <0 0x17c23000 0 0x1000>;
+				status = "disabled";
+			};
+
+			frame@17c25000 {
+				frame-number = <2>;
+				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+				reg = <0 0x17c25000 0 0x1000>;
+				status = "disabled";
+			};
+
+			frame@17c27000 {
+				frame-number = <3>;
+				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+				reg = <0 0x17c27000 0 0x1000>;
+				status = "disabled";
+			};
+
+			frame@17c29000 {
+				frame-number = <4>;
+				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+				reg = <0 0x17c29000 0 0x1000>;
+				status = "disabled";
+			};
+
+			frame@17c2b000 {
+				frame-number = <5>;
+				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+				reg = <0 0x17c2b000 0 0x1000>;
+				status = "disabled";
+			};
+
+			frame@17c2d000 {
+				frame-number = <6>;
+				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+				reg = <0 0x17c2d000 0 0x1000>;
+				status = "disabled";
+			};
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
+	};
+};
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation


^ permalink raw reply	[flat|nested] 40+ messages in thread

* [PATCH v4 03/14] dt-bindings: arm-smmu: update binding for qcom sc7180 SoC
  2019-11-06  6:50 [PATCH v4 00/14] Add device tree support for sc7180 Rajendra Nayak
  2019-11-06  6:50 ` [PATCH v4 01/14] dt-bindings: qcom: Add SC7180 bindings Rajendra Nayak
  2019-11-06  6:50 ` [PATCH v4 02/14] arm64: dts: sc7180: Add minimal dts/dtsi files for SC7180 soc Rajendra Nayak
@ 2019-11-06  6:50 ` Rajendra Nayak
  2019-11-07  0:49   ` Rob Herring
  2019-11-07 17:47   ` Stephen Boyd
  2019-11-06  6:50 ` [PATCH v4 04/14] arm64: dts: sc7180: Add device node for apps_smmu Rajendra Nayak
                   ` (10 subsequent siblings)
  13 siblings, 2 replies; 40+ messages in thread
From: Rajendra Nayak @ 2019-11-06  6:50 UTC (permalink / raw)
  To: agross, robh+dt, bjorn.andersson
  Cc: linux-arm-msm, devicetree, linux-kernel, mka, swboyd,
	Rajendra Nayak, Joerg Roedel, Mark Rutland

Add the soc specific compatible for sc7180 smmu-500

Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Cc: Joerg Roedel <joro@8bytes.org>
Cc: Mark Rutland <mark.rutland@arm.com>
---
v4: Updated yaml, sorted.

 Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
index 3b31b4802a54..6515dbe47508 100644
--- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
+++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
@@ -34,6 +34,7 @@ properties:
       - description: Qcom SoCs implementing "arm,mmu-500"
         items:
           - enum:
+              - qcom,sc7180-smmu-500
               - qcom,sdm845-smmu-500
           - const: arm,mmu-500
       - items:
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation


^ permalink raw reply	[flat|nested] 40+ messages in thread

* [PATCH v4 04/14] arm64: dts: sc7180: Add device node for apps_smmu
  2019-11-06  6:50 [PATCH v4 00/14] Add device tree support for sc7180 Rajendra Nayak
                   ` (2 preceding siblings ...)
  2019-11-06  6:50 ` [PATCH v4 03/14] dt-bindings: arm-smmu: update binding for qcom sc7180 SoC Rajendra Nayak
@ 2019-11-06  6:50 ` Rajendra Nayak
  2019-11-07 17:47   ` Stephen Boyd
  2019-11-06  6:50 ` [PATCH v4 05/14] arm64: dts: qcom: sc7180: Add cmd_db reserved area Rajendra Nayak
                   ` (9 subsequent siblings)
  13 siblings, 1 reply; 40+ messages in thread
From: Rajendra Nayak @ 2019-11-06  6:50 UTC (permalink / raw)
  To: agross, robh+dt, bjorn.andersson
  Cc: linux-arm-msm, devicetree, linux-kernel, mka, swboyd,
	Vivek Gautam, Rajendra Nayak

From: Vivek Gautam <vivek.gautam@codeaurora.org>

Adding device node for APPS SMMU that is connected to
devices such as display, video, usb, mmc, etc. on SC7180
chipset.

Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
---
 arch/arm64/boot/dts/qcom/sc7180.dtsi | 88 ++++++++++++++++++++++++++++
 1 file changed, 88 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index 17870dd67390..ef52cd7efc88 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -210,6 +210,94 @@
 			};
 		};
 
+		apps_smmu: iommu@15000000 {
+			compatible = "qcom,sc7180-smmu-500", "arm,mmu-500";
+			reg = <0 0x15000000 0 0x100000>;
+			#iommu-cells = <2>;
+			#global-interrupts = <1>;
+			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
 		intc: interrupt-controller@17a00000 {
 			compatible = "arm,gic-v3";
 			#address-cells = <2>;
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation


^ permalink raw reply	[flat|nested] 40+ messages in thread

* [PATCH v4 05/14] arm64: dts: qcom: sc7180: Add cmd_db reserved area
  2019-11-06  6:50 [PATCH v4 00/14] Add device tree support for sc7180 Rajendra Nayak
                   ` (3 preceding siblings ...)
  2019-11-06  6:50 ` [PATCH v4 04/14] arm64: dts: sc7180: Add device node for apps_smmu Rajendra Nayak
@ 2019-11-06  6:50 ` Rajendra Nayak
  2019-11-07 17:47   ` Stephen Boyd
  2019-11-06  6:50 ` [PATCH v4 06/14] arm64: dts: qcom: sc7180: Add rpmh-rsc node Rajendra Nayak
                   ` (8 subsequent siblings)
  13 siblings, 1 reply; 40+ messages in thread
From: Rajendra Nayak @ 2019-11-06  6:50 UTC (permalink / raw)
  To: agross, robh+dt, bjorn.andersson
  Cc: linux-arm-msm, devicetree, linux-kernel, mka, swboyd,
	Maulik Shah, Rajendra Nayak

From: Maulik Shah <mkshah@codeaurora.org>

Command_db provides mapping for resource key and address managed
by remote processor. Add cmd_db reserved memory area.

Signed-off-by: Maulik Shah <mkshah@codeaurora.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
---
v4: updated label to aop_cmd_db_mem

 arch/arm64/boot/dts/qcom/sc7180.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index ef52cd7efc88..61250560c7ef 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -31,6 +31,18 @@
 		};
 	};
 
+	reserved_memory: reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		aop_cmd_db_mem: memory@80820000 {
+			reg = <0x0 0x80820000 0x0 0x20000>;
+			compatible = "qcom,cmd-db";
+			no-map;
+		};
+	};
+
 	cpus {
 		#address-cells = <2>;
 		#size-cells = <0>;
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation


^ permalink raw reply	[flat|nested] 40+ messages in thread

* [PATCH v4 06/14] arm64: dts: qcom: sc7180: Add rpmh-rsc node
  2019-11-06  6:50 [PATCH v4 00/14] Add device tree support for sc7180 Rajendra Nayak
                   ` (4 preceding siblings ...)
  2019-11-06  6:50 ` [PATCH v4 05/14] arm64: dts: qcom: sc7180: Add cmd_db reserved area Rajendra Nayak
@ 2019-11-06  6:50 ` Rajendra Nayak
  2019-11-07 17:53   ` Stephen Boyd
  2019-11-07 17:53   ` Stephen Boyd
  2019-11-06  6:50 ` [PATCH v4 07/14] drivers: irqchip: qcom-pdc: Move to an SoC independent compatible Rajendra Nayak
                   ` (7 subsequent siblings)
  13 siblings, 2 replies; 40+ messages in thread
From: Rajendra Nayak @ 2019-11-06  6:50 UTC (permalink / raw)
  To: agross, robh+dt, bjorn.andersson
  Cc: linux-arm-msm, devicetree, linux-kernel, mka, swboyd,
	Maulik Shah, Rajendra Nayak

From: Maulik Shah <mkshah@codeaurora.org>

Add device bindings for the application processor's rsc. The rsc
contains the TCS that are used for communicating with the hardened
resource accelerators on Qualcomm Technologies, Inc. (QTI) SoCs.

Signed-off-by: Maulik Shah <mkshah@codeaurora.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
---
 arch/arm64/boot/dts/qcom/sc7180.dtsi | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index 61250560c7ef..98c8ab7d613c 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -7,6 +7,7 @@
 
 #include <dt-bindings/clock/qcom,gcc-sc7180.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/soc/qcom,rpmh-rsc.h>
 
 / {
 	interrupt-parent = <&intc>;
@@ -387,6 +388,24 @@
 				status = "disabled";
 			};
 		};
+
+		apps_rsc: rsc@18200000 {
+			label = "apps_rsc";
+			compatible = "qcom,rpmh-rsc";
+			reg = <0 0x18200000 0 0x10000>,
+			      <0 0x18210000 0 0x10000>,
+			      <0 0x18220000 0 0x10000>;
+			reg-names = "drv-0", "drv-1", "drv-2";
+			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+			qcom,tcs-offset = <0xd00>;
+			qcom,drv-id = <2>;
+			qcom,tcs-config = <ACTIVE_TCS  2>,
+					  <SLEEP_TCS   3>,
+					  <WAKE_TCS    3>,
+					  <CONTROL_TCS 1>;
+		};
 	};
 
 	timer {
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation


^ permalink raw reply	[flat|nested] 40+ messages in thread

* [PATCH v4 07/14] drivers: irqchip: qcom-pdc: Move to an SoC independent compatible
  2019-11-06  6:50 [PATCH v4 00/14] Add device tree support for sc7180 Rajendra Nayak
                   ` (5 preceding siblings ...)
  2019-11-06  6:50 ` [PATCH v4 06/14] arm64: dts: qcom: sc7180: Add rpmh-rsc node Rajendra Nayak
@ 2019-11-06  6:50 ` Rajendra Nayak
  2019-11-06 18:20   ` Lina Iyer
  2019-11-06 19:10   ` Stephen Boyd
  2019-11-06  6:50 ` [PATCH v4 08/14] dt-bindings: qcom,pdc: Add compatible for sc7180 Rajendra Nayak
                   ` (6 subsequent siblings)
  13 siblings, 2 replies; 40+ messages in thread
From: Rajendra Nayak @ 2019-11-06  6:50 UTC (permalink / raw)
  To: agross, robh+dt, bjorn.andersson
  Cc: linux-arm-msm, devicetree, linux-kernel, mka, swboyd,
	Rajendra Nayak, Lina Iyer, Marc Zyngier

Remove the sdm845 SoC specific compatible to make the driver
easily reusable across other SoC's with the same IP block.
This will reduce further churn adding any SoC specific
compatibles unless really needed.

Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Cc: Lina Iyer <ilina@codeaurora.org>
Cc: Marc Zyngier <maz@kernel.org>
---
 drivers/irqchip/qcom-pdc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/irqchip/qcom-pdc.c b/drivers/irqchip/qcom-pdc.c
index faa7d61b9d6c..c175333bb646 100644
--- a/drivers/irqchip/qcom-pdc.c
+++ b/drivers/irqchip/qcom-pdc.c
@@ -309,4 +309,4 @@ static int qcom_pdc_init(struct device_node *node, struct device_node *parent)
 	return ret;
 }
 
-IRQCHIP_DECLARE(pdc_sdm845, "qcom,sdm845-pdc", qcom_pdc_init);
+IRQCHIP_DECLARE(qcom_pdc, "qcom,pdc", qcom_pdc_init);
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation


^ permalink raw reply	[flat|nested] 40+ messages in thread

* [PATCH v4 08/14] dt-bindings: qcom,pdc: Add compatible for sc7180
  2019-11-06  6:50 [PATCH v4 00/14] Add device tree support for sc7180 Rajendra Nayak
                   ` (6 preceding siblings ...)
  2019-11-06  6:50 ` [PATCH v4 07/14] drivers: irqchip: qcom-pdc: Move to an SoC independent compatible Rajendra Nayak
@ 2019-11-06  6:50 ` Rajendra Nayak
  2019-11-06 16:56   ` Rob Herring
  2019-11-06 19:11   ` Stephen Boyd
  2019-11-06  6:50 ` [PATCH v4 09/14] arm64: dts: qcom: sc7180: Add pdc interrupt controller Rajendra Nayak
                   ` (5 subsequent siblings)
  13 siblings, 2 replies; 40+ messages in thread
From: Rajendra Nayak @ 2019-11-06  6:50 UTC (permalink / raw)
  To: agross, robh+dt, bjorn.andersson
  Cc: linux-arm-msm, devicetree, linux-kernel, mka, swboyd,
	Rajendra Nayak, Lina Iyer, Marc Zyngier

Add the compatible string for sc7180 SoC from Qualcomm.

Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Cc: Lina Iyer <ilina@codeaurora.org>
Cc: Marc Zyngier <maz@kernel.org>
---
 .../devicetree/bindings/interrupt-controller/qcom,pdc.txt      | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt
index 8e0797cb1487..1df293953327 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt
@@ -17,7 +17,8 @@ Properties:
 - compatible:
 	Usage: required
 	Value type: <string>
-	Definition: Should contain "qcom,<soc>-pdc"
+	Definition: Should contain "qcom,<soc>-pdc" and "qcom,pdc"
+		    - "qcom,sc7180-pdc": For SC7180
 		    - "qcom,sdm845-pdc": For SDM845
 
 - reg:
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation


^ permalink raw reply	[flat|nested] 40+ messages in thread

* [PATCH v4 09/14] arm64: dts: qcom: sc7180: Add pdc interrupt controller
  2019-11-06  6:50 [PATCH v4 00/14] Add device tree support for sc7180 Rajendra Nayak
                   ` (7 preceding siblings ...)
  2019-11-06  6:50 ` [PATCH v4 08/14] dt-bindings: qcom,pdc: Add compatible for sc7180 Rajendra Nayak
@ 2019-11-06  6:50 ` Rajendra Nayak
  2019-11-06 19:11   ` Stephen Boyd
  2019-11-06  6:50 ` [PATCH v4 10/14] arm64: dts: qcom: sc7180: Add SPMI PMIC arbiter device Rajendra Nayak
                   ` (4 subsequent siblings)
  13 siblings, 1 reply; 40+ messages in thread
From: Rajendra Nayak @ 2019-11-06  6:50 UTC (permalink / raw)
  To: agross, robh+dt, bjorn.andersson
  Cc: linux-arm-msm, devicetree, linux-kernel, mka, swboyd,
	Maulik Shah, Rajendra Nayak

From: Maulik Shah <mkshah@codeaurora.org>

Add pdc interrupt controller for sc7180

Signed-off-by: Maulik Shah <mkshah@codeaurora.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
---
v4: Updated compatible string

 arch/arm64/boot/dts/qcom/sc7180.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index 98c8ab7d613c..14b8986c8a5f 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -202,6 +202,16 @@
 			};
 		};
 
+		pdc: interrupt-controller@b220000 {
+			compatible = "qcom,sc7180-pdc", "qcom,pdc";
+			reg = <0 0xb220000 0 0x30000>;
+			qcom,pdc-ranges = <0 480 15>, <17 497 98>,
+					  <119 634 4>, <124 639 1>;
+			#interrupt-cells = <2>;
+			interrupt-parent = <&intc>;
+			interrupt-controller;
+		};
+
 		tlmm: pinctrl@3500000 {
 			compatible = "qcom,sc7180-pinctrl";
 			reg = <0 0x03500000 0 0x300000>,
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation


^ permalink raw reply	[flat|nested] 40+ messages in thread

* [PATCH v4 10/14] arm64: dts: qcom: sc7180: Add SPMI PMIC arbiter device
  2019-11-06  6:50 [PATCH v4 00/14] Add device tree support for sc7180 Rajendra Nayak
                   ` (8 preceding siblings ...)
  2019-11-06  6:50 ` [PATCH v4 09/14] arm64: dts: qcom: sc7180: Add pdc interrupt controller Rajendra Nayak
@ 2019-11-06  6:50 ` Rajendra Nayak
  2019-11-07 17:54   ` Stephen Boyd
  2019-11-06  6:50 ` [PATCH v4 11/14] arm64: dts: qcom: pm6150: Add PM6150/PM6150L PMIC peripherals Rajendra Nayak
                   ` (3 subsequent siblings)
  13 siblings, 1 reply; 40+ messages in thread
From: Rajendra Nayak @ 2019-11-06  6:50 UTC (permalink / raw)
  To: agross, robh+dt, bjorn.andersson
  Cc: linux-arm-msm, devicetree, linux-kernel, mka, swboyd,
	Kiran Gunda, Rajendra Nayak

From: Kiran Gunda <kgunda@codeaurora.org>

Add SPMI PMIC arbiter device to communicate with PMICs
attached to SPMI bus.

Signed-off-by: Kiran Gunda <kgunda@codeaurora.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
---
 arch/arm64/boot/dts/qcom/sc7180.dtsi | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index 14b8986c8a5f..ff0197df9a7f 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -233,6 +233,25 @@
 			};
 		};
 
+		spmi_bus: spmi@c440000 {
+			compatible = "qcom,spmi-pmic-arb";
+			reg = <0 0x0c440000 0 0x1100>,
+			      <0 0x0c600000 0 0x2000000>,
+			      <0 0x0e600000 0 0x100000>,
+			      <0 0x0e700000 0 0xa0000>,
+			      <0 0x0c40a000 0 0x26000>;
+			reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
+			interrupt-names = "periph_irq";
+			interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
+			qcom,ee = <0>;
+			qcom,channel = <0>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			interrupt-controller;
+			#interrupt-cells = <4>;
+			cell-index = <0>;
+		};
+
 		apps_smmu: iommu@15000000 {
 			compatible = "qcom,sc7180-smmu-500", "arm,mmu-500";
 			reg = <0 0x15000000 0 0x100000>;
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation


^ permalink raw reply	[flat|nested] 40+ messages in thread

* [PATCH v4 11/14] arm64: dts: qcom: pm6150: Add PM6150/PM6150L PMIC peripherals
  2019-11-06  6:50 [PATCH v4 00/14] Add device tree support for sc7180 Rajendra Nayak
                   ` (9 preceding siblings ...)
  2019-11-06  6:50 ` [PATCH v4 10/14] arm64: dts: qcom: sc7180: Add SPMI PMIC arbiter device Rajendra Nayak
@ 2019-11-06  6:50 ` Rajendra Nayak
  2019-11-07 17:59   ` Stephen Boyd
  2019-11-06  6:50 ` [PATCH v4 12/14] arm64: dts: qcom: sc7180-idp: Add RPMh regulators Rajendra Nayak
                   ` (2 subsequent siblings)
  13 siblings, 1 reply; 40+ messages in thread
From: Rajendra Nayak @ 2019-11-06  6:50 UTC (permalink / raw)
  To: agross, robh+dt, bjorn.andersson
  Cc: linux-arm-msm, devicetree, linux-kernel, mka, swboyd,
	Kiran Gunda, Rajendra Nayak

From: Kiran Gunda <kgunda@codeaurora.org>

Add PM6150/PM6150L peripherals such as PON, GPIOs, ADC and other
PMIC infra modules.

Signed-off-by: Kiran Gunda <kgunda@codeaurora.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
---
v4: Updated pm6150_gpio and pm6150l_gpio to use gpio-ranges

 arch/arm64/boot/dts/qcom/pm6150.dtsi    | 72 +++++++++++++++++++++++++
 arch/arm64/boot/dts/qcom/pm6150l.dtsi   | 31 +++++++++++
 arch/arm64/boot/dts/qcom/sc7180-idp.dts |  2 +
 3 files changed, 105 insertions(+)
 create mode 100644 arch/arm64/boot/dts/qcom/pm6150.dtsi
 create mode 100644 arch/arm64/boot/dts/qcom/pm6150l.dtsi

diff --git a/arch/arm64/boot/dts/qcom/pm6150.dtsi b/arch/arm64/boot/dts/qcom/pm6150.dtsi
new file mode 100644
index 000000000000..1fcbc7a1e062
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/pm6150.dtsi
@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: BSD-3-Clause
+// Copyright (c) 2019, The Linux Foundation. All rights reserved.
+
+#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/spmi/spmi.h>
+#include <dt-bindings/thermal/thermal.h>
+
+&spmi_bus {
+	pm6150_lsid0: pmic@0 {
+		compatible = "qcom,pm6150", "qcom,spmi-pmic";
+		reg = <0x0 SPMI_USID>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pm6150_pon: pon@800 {
+			compatible = "qcom,pm8998-pon";
+			reg = <0x800>;
+			mode-bootloader = <0x2>;
+			mode-recovery = <0x1>;
+
+			pwrkey {
+				compatible = "qcom,pm8941-pwrkey";
+				interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
+				debounce = <15625>;
+				bias-pull-up;
+				linux,code = <KEY_POWER>;
+			};
+		};
+
+		pm6150_temp: temp-alarm@2400 {
+			compatible = "qcom,spmi-temp-alarm";
+			reg = <0x2400>;
+			interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_RISING>;
+			io-channels = <&pm6150_adc ADC5_DIE_TEMP>;
+			io-channel-names = "thermal";
+			#thermal-sensor-cells = <0>;
+		};
+
+		pm6150_adc: adc@3100 {
+			compatible = "qcom,spmi-adc5";
+			reg = <0x3100>;
+			interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			#io-channel-cells = <1>;
+
+			adc-chan@ADC5_DIE_TEMP {
+				reg = <ADC5_DIE_TEMP>;
+				label = "die_temp";
+			};
+		};
+
+		pm6150_gpio: gpios@c000 {
+			compatible = "qcom,pm6150-gpio", "qcom,spmi-gpio";
+			reg = <0xc000>;
+			gpio-controller;
+			gpio-ranges = <&pm6150_gpio 0 0 10>;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+
+	pm6150_lsid1: pmic@1 {
+		compatible = "qcom,pm6150", "qcom,spmi-pmic";
+		reg = <0x1 SPMI_USID>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+};
diff --git a/arch/arm64/boot/dts/qcom/pm6150l.dtsi b/arch/arm64/boot/dts/qcom/pm6150l.dtsi
new file mode 100644
index 000000000000..f84027b505d1
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/pm6150l.dtsi
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: BSD-3-Clause
+// Copyright (c) 2019, The Linux Foundation. All rights reserved.
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/spmi/spmi.h>
+
+&spmi_bus {
+	pm6150l_lsid4: pmic@4 {
+		compatible = "qcom,pm6150l", "qcom,spmi-pmic";
+		reg = <0x4 SPMI_USID>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pm6150l_gpio: gpios@c000 {
+			compatible = "qcom,pm6150l-gpio", "qcom,spmi-gpio";
+			reg = <0xc000>;
+			gpio-controller;
+			gpio-ranges = <&pm6150l_gpio 0 0 12>;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+
+	pm6150l_lsid5: pmic@5 {
+		compatible = "qcom,pm6150l", "qcom,spmi-pmic";
+		reg = <0x5 SPMI_USID>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+};
diff --git a/arch/arm64/boot/dts/qcom/sc7180-idp.dts b/arch/arm64/boot/dts/qcom/sc7180-idp.dts
index c637a4a647f8..eb4e7f320a41 100644
--- a/arch/arm64/boot/dts/qcom/sc7180-idp.dts
+++ b/arch/arm64/boot/dts/qcom/sc7180-idp.dts
@@ -8,6 +8,8 @@
 /dts-v1/;
 
 #include "sc7180.dtsi"
+#include "pm6150.dtsi"
+#include "pm6150l.dtsi"
 
 / {
 	model = "Qualcomm Technologies, Inc. SC7180 IDP";
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation


^ permalink raw reply	[flat|nested] 40+ messages in thread

* [PATCH v4 12/14] arm64: dts: qcom: sc7180-idp: Add RPMh regulators
  2019-11-06  6:50 [PATCH v4 00/14] Add device tree support for sc7180 Rajendra Nayak
                   ` (10 preceding siblings ...)
  2019-11-06  6:50 ` [PATCH v4 11/14] arm64: dts: qcom: pm6150: Add PM6150/PM6150L PMIC peripherals Rajendra Nayak
@ 2019-11-06  6:50 ` Rajendra Nayak
  2019-11-06  6:50 ` [PATCH v4 13/14] arm64: dts: qcom: SC7180: Add node for rpmhcc clock driver Rajendra Nayak
  2019-11-06  6:50 ` [PATCH v4 14/14] arm64: dts: sc7180: Add qupv3_0 and qupv3_1 Rajendra Nayak
  13 siblings, 0 replies; 40+ messages in thread
From: Rajendra Nayak @ 2019-11-06  6:50 UTC (permalink / raw)
  To: agross, robh+dt, bjorn.andersson
  Cc: linux-arm-msm, devicetree, linux-kernel, mka, swboyd,
	Kiran Gunda, Rajendra Nayak

From: Kiran Gunda <kgunda@codeaurora.org>

Add the rpmh regulators for the sc7180 idp platform. This platform
consists of PMIC PM6150 and PM6150l

Signed-off-by: Kiran Gunda <kgunda@codeaurora.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
---
 arch/arm64/boot/dts/qcom/sc7180-idp.dts | 207 ++++++++++++++++++++++++
 1 file changed, 207 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sc7180-idp.dts b/arch/arm64/boot/dts/qcom/sc7180-idp.dts
index eb4e7f320a41..d8206d1b5896 100644
--- a/arch/arm64/boot/dts/qcom/sc7180-idp.dts
+++ b/arch/arm64/boot/dts/qcom/sc7180-idp.dts
@@ -7,6 +7,7 @@
 
 /dts-v1/;
 
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
 #include "sc7180.dtsi"
 #include "pm6150.dtsi"
 #include "pm6150l.dtsi"
@@ -24,6 +25,212 @@
 	};
 };
 
+&apps_rsc {
+	pm6150-rpmh-regulators {
+		compatible = "qcom,pm6150-rpmh-regulators";
+		qcom,pmic-id = "a";
+
+		vreg_s1a_1p1: smps1 {
+			regulator-min-microvolt = <1128000>;
+			regulator-max-microvolt = <1128000>;
+		};
+
+		vreg_s4a_1p0: smps4 {
+			regulator-min-microvolt = <824000>;
+			regulator-max-microvolt = <1120000>;
+		};
+
+		vreg_s5a_2p0: smps5 {
+			regulator-min-microvolt = <1744000>;
+			regulator-max-microvolt = <2040000>;
+		};
+
+		vreg_l1a_1p2: ldo1 {
+			regulator-min-microvolt = <1178000>;
+			regulator-max-microvolt = <1256000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+		};
+
+		vreg_l2a_1p0: ldo2 {
+			regulator-min-microvolt = <944000>;
+			regulator-max-microvolt = <1056000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+		};
+
+		vreg_l3a_1p0: ldo3 {
+			regulator-min-microvolt = <968000>;
+			regulator-max-microvolt = <1064000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+		};
+
+		vreg_l4a_0p8: ldo4 {
+			regulator-min-microvolt = <824000>;
+			regulator-max-microvolt = <928000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+		};
+
+		vreg_l5a_2p7: ldo5 {
+			regulator-min-microvolt = <2496000>;
+			regulator-max-microvolt = <3000000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+		};
+
+		vreg_l6a_0p6: ldo6 {
+			regulator-min-microvolt = <568000>;
+			regulator-max-microvolt = <648000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+		};
+
+		vreg_l9a_0p6: ldo9 {
+			regulator-min-microvolt = <488000>;
+			regulator-max-microvolt = <800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+		};
+
+		vreg_l10a_1p8: ldo10 {
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1832000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+		};
+
+		vreg_l11a_1p8: ldo11 {
+			regulator-min-microvolt = <1696000>;
+			regulator-max-microvolt = <1904000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+		};
+
+		vreg_l12a_1p8: ldo12 {
+			regulator-min-microvolt = <1696000>;
+			regulator-max-microvolt = <1952000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+		};
+
+		vreg_l13a_1p8: ldo13 {
+			regulator-min-microvolt = <1696000>;
+			regulator-max-microvolt = <1904000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+		};
+
+		vreg_l14a_1p8: ldo14 {
+			regulator-min-microvolt = <1728000>;
+			regulator-max-microvolt = <1832000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+		};
+
+		vreg_l15a_1p8: ldo15 {
+			regulator-min-microvolt = <1696000>;
+			regulator-max-microvolt = <1904000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+		};
+
+		vreg_l16a_2p7: ldo16 {
+			regulator-min-microvolt = <2496000>;
+			regulator-max-microvolt = <3304000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+		};
+
+		vreg_l17a_3p0: ldo17 {
+			regulator-min-microvolt = <2920000>;
+			regulator-max-microvolt = <3232000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+		};
+
+		vreg_l18a_2p8: ldo18 {
+			regulator-min-microvolt = <2496000>;
+			regulator-max-microvolt = <3304000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+		};
+
+		vreg_l19a_2p9: ldo19 {
+			regulator-min-microvolt = <2696000>;
+			regulator-max-microvolt = <3304000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+		};
+	};
+
+	pm6150l-rpmh-regulators {
+		compatible = "qcom,pm6150l-rpmh-regulators";
+		qcom,pmic-id = "c";
+
+		vreg_s8c_1p3: smps8 {
+			regulator-min-microvolt = <1120000>;
+			regulator-max-microvolt = <1408000>;
+		};
+
+		vreg_l1c_1p8: ldo1 {
+			regulator-min-microvolt = <1616000>;
+			regulator-max-microvolt = <1984000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+		};
+
+		vreg_l2c_1p3: ldo2 {
+			regulator-min-microvolt = <1168000>;
+			regulator-max-microvolt = <1304000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+		};
+
+		vreg_l3c_1p2: ldo3 {
+			regulator-min-microvolt = <1144000>;
+			regulator-max-microvolt = <1304000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+		};
+
+		vreg_l4c_1p8: ldo4 {
+			regulator-min-microvolt = <1648000>;
+			regulator-max-microvolt = <3304000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+		};
+
+		vreg_l5c_1p8: ldo5 {
+			regulator-min-microvolt = <1648000>;
+			regulator-max-microvolt = <3304000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+		};
+
+		vreg_l6c_2p9: ldo6 {
+			regulator-min-microvolt = <2696000>;
+			regulator-max-microvolt = <3304000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+		};
+
+		vreg_l7c_3p0: ldo7 {
+			regulator-min-microvolt = <3000000>;
+			regulator-max-microvolt = <3312000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+		};
+
+		vreg_l8c_1p8: ldo8 {
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1904000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+		};
+
+		vreg_l9c_2p9: ldo9 {
+			regulator-min-microvolt = <2952000>;
+			regulator-max-microvolt = <3304000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+		};
+
+		vreg_l10c_3p3: ldo10 {
+			regulator-min-microvolt = <3000000>;
+			regulator-max-microvolt = <3400000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+		};
+
+		vreg_l11c_3p3: ldo11 {
+			regulator-min-microvolt = <3000000>;
+			regulator-max-microvolt = <3400000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+		};
+
+		vreg_bob: bob {
+			regulator-min-microvolt = <3008000>;
+			regulator-max-microvolt = <3960000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+		};
+	};
+};
+
 &qupv3_id_1 {
 	status = "okay";
 };
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation


^ permalink raw reply	[flat|nested] 40+ messages in thread

* [PATCH v4 13/14] arm64: dts: qcom: SC7180: Add node for rpmhcc clock driver
  2019-11-06  6:50 [PATCH v4 00/14] Add device tree support for sc7180 Rajendra Nayak
                   ` (11 preceding siblings ...)
  2019-11-06  6:50 ` [PATCH v4 12/14] arm64: dts: qcom: sc7180-idp: Add RPMh regulators Rajendra Nayak
@ 2019-11-06  6:50 ` Rajendra Nayak
  2019-11-07 18:50   ` Stephen Boyd
  2019-11-06  6:50 ` [PATCH v4 14/14] arm64: dts: sc7180: Add qupv3_0 and qupv3_1 Rajendra Nayak
  13 siblings, 1 reply; 40+ messages in thread
From: Rajendra Nayak @ 2019-11-06  6:50 UTC (permalink / raw)
  To: agross, robh+dt, bjorn.andersson
  Cc: linux-arm-msm, devicetree, linux-kernel, mka, swboyd, Taniya Das,
	Rajendra Nayak

From: Taniya Das <tdas@codeaurora.org>

Add node for rpmhcc clock driver.

Signed-off-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
---
 arch/arm64/boot/dts/qcom/sc7180.dtsi | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index ff0197df9a7f..c9c8c3a52f3d 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -6,6 +6,7 @@
  */
 
 #include <dt-bindings/clock/qcom,gcc-sc7180.h>
+#include <dt-bindings/clock/qcom,rpmh.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
 
@@ -174,6 +175,9 @@
 		gcc: clock-controller@100000 {
 			compatible = "qcom,gcc-sc7180";
 			reg = <0 0x00100000 0 0x1f0000>;
+			clocks = <&rpmhcc RPMH_CXO_CLK>,
+				 <&rpmhcc RPMH_CXO_CLK_A>;
+			clock-names = "bi_tcxo", "bi_tcxo_ao";
 			#clock-cells = <1>;
 			#reset-cells = <1>;
 			#power-domain-cells = <1>;
@@ -434,6 +438,13 @@
 					  <SLEEP_TCS   3>,
 					  <WAKE_TCS    3>,
 					  <CONTROL_TCS 1>;
+
+			rpmhcc: clock-controller {
+				compatible = "qcom,sc7180-rpmh-clk";
+				clocks = <&xo_board>;
+				clock-names = "xo";
+				#clock-cells = <1>;
+			};
 		};
 	};
 
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation


^ permalink raw reply	[flat|nested] 40+ messages in thread

* [PATCH v4 14/14] arm64: dts: sc7180: Add qupv3_0 and qupv3_1
  2019-11-06  6:50 [PATCH v4 00/14] Add device tree support for sc7180 Rajendra Nayak
                   ` (12 preceding siblings ...)
  2019-11-06  6:50 ` [PATCH v4 13/14] arm64: dts: qcom: SC7180: Add node for rpmhcc clock driver Rajendra Nayak
@ 2019-11-06  6:50 ` Rajendra Nayak
  2019-11-07 18:52   ` Stephen Boyd
  13 siblings, 1 reply; 40+ messages in thread
From: Rajendra Nayak @ 2019-11-06  6:50 UTC (permalink / raw)
  To: agross, robh+dt, bjorn.andersson
  Cc: linux-arm-msm, devicetree, linux-kernel, mka, swboyd,
	Roja Rani Yarubandi, Rajendra Nayak

From: Roja Rani Yarubandi <rojay@codeaurora.org>

Add QUP SE instances configuration for sc7180.

Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
---
v4:
* dropped the uart8/10 hunks
* Fixed qup06/07/08/09/10 functions as qup10/11/12/13/14

 arch/arm64/boot/dts/qcom/sc7180-idp.dts | 146 +++++
 arch/arm64/boot/dts/qcom/sc7180.dtsi    | 675 ++++++++++++++++++++++++
 2 files changed, 821 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sc7180-idp.dts b/arch/arm64/boot/dts/qcom/sc7180-idp.dts
index d8206d1b5896..189254f5ae95 100644
--- a/arch/arm64/boot/dts/qcom/sc7180-idp.dts
+++ b/arch/arm64/boot/dts/qcom/sc7180-idp.dts
@@ -17,6 +17,7 @@
 	compatible = "qcom,sc7180-idp";
 
 	aliases {
+		hsuart0 = &uart3;
 		serial0 = &uart8;
 	};
 
@@ -231,16 +232,100 @@
 	};
 };
 
+&qupv3_id_0 {
+	status = "okay";
+};
+
 &qupv3_id_1 {
 	status = "okay";
 };
 
+&uart3 {
+	status = "okay";
+};
+
 &uart8 {
 	status = "okay";
 };
 
 /* PINCTRL - additions to nodes defined in sc7180.dtsi */
 
+&qup_i2c2_default {
+	pinconf {
+		pins = "gpio15", "gpio16";
+		drive-strength = <2>;
+
+		/* Has external pullup */
+		bias-disable;
+	};
+};
+
+&qup_i2c4_default {
+	pinconf {
+		pins = "gpio115", "gpio116";
+		drive-strength = <2>;
+
+		/* Has external pullup */
+		bias-disable;
+	};
+};
+
+&qup_i2c7_default {
+	pinconf {
+		pins = "gpio6", "gpio7";
+		drive-strength = <2>;
+		bias-disable;
+	};
+};
+
+&qup_i2c9_default {
+	pinconf {
+		pins = "gpio46", "gpio47";
+		drive-strength = <2>;
+
+		/* Has external pullup */
+		bias-disable;
+	};
+};
+
+&qup_uart3_default {
+	pinconf-cts {
+		/*
+		 * Configure a pull-down on 38 (CTS) to match the pull of
+		 * the Bluetooth module.
+		 */
+		pins = "gpio38";
+		bias-pull-down;
+		output-high;
+	};
+
+	pinconf-rts {
+		/* We'll drive 39 (RTS), so no pull */
+		pins = "gpio39";
+		drive-strength = <2>;
+		bias-disable;
+	};
+
+	pinconf-tx {
+		/* We'll drive 40 (TX), so no pull */
+		pins = "gpio40";
+		drive-strength = <2>;
+		bias-disable;
+		output-high;
+	};
+
+	pinconf-rx {
+		/*
+		 * Configure a pull-up on 41 (RX). This is needed to avoid
+		 * garbage data when the TX pin of the Bluetooth module is
+		 * in tri-state (module powered off or not driving the
+		 * signal yet).
+		 */
+		pins = "gpio41";
+		bias-pull-up;
+	};
+};
+
 &qup_uart8_default {
 	pinconf-tx {
 		pins = "gpio44";
@@ -254,3 +339,64 @@
 		bias-pull-up;
 	};
 };
+
+&qup_spi0_default {
+	pinconf {
+		pins = "gpio34", "gpio35", "gpio36", "gpio37";
+		drive-strength = <2>;
+		bias-disable;
+	};
+};
+
+&qup_spi6_default {
+	pinconf {
+		pins = "gpio59", "gpio60", "gpio61", "gpio62";
+		drive-strength = <2>;
+		bias-disable;
+	};
+};
+
+&qup_spi10_default {
+	pinconf {
+		pins = "gpio86", "gpio87", "gpio88", "gpio89";
+		drive-strength = <2>;
+		bias-disable;
+	};
+};
+
+&qspi {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&qspi_clk &qspi_cs0 &qspi_data01>;
+
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <25000000>;
+		spi-tx-bus-width = <2>;
+		spi-rx-bus-width = <2>;
+	};
+};
+
+&qspi_cs0 {
+		pinconf {
+			pins = "gpio68";
+			bias-disable;
+		};
+};
+
+&qspi_clk {
+		pinconf {
+			pins = "gpio63";
+			bias-disable;
+		};
+};
+
+&qspi_data01 {
+		pinconf {
+			pins = "gpio64", "gpio65";
+
+			/* High-Z when no transfers; nice to park the lines */
+			bias-pull-up;
+		};
+};
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index c9c8c3a52f3d..5849baaa8990 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -183,6 +183,214 @@
 			#power-domain-cells = <1>;
 		};
 
+		qupv3_id_0: geniqup@8c0000 {
+			compatible = "qcom,geni-se-qup";
+			reg = <0 0x008c0000 0 0x6000>;
+			clock-names = "m-ahb", "s-ahb";
+			clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+				 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+			status = "disabled";
+
+			i2c0: i2c@880000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0 0x00880000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_i2c0_default>;
+				interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			spi0: spi@880000 {
+				compatible = "qcom,geni-spi";
+				reg = <0 0x00880000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_spi0_default>;
+				interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			uart0: serial@880000 {
+				compatible = "qcom,geni-uart";
+				reg = <0 0x00880000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_uart0_default>;
+				interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			i2c1: i2c@884000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0 0x00884000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_i2c1_default>;
+				interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			spi1: spi@884000 {
+				compatible = "qcom,geni-spi";
+				reg = <0 0x00884000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_spi1_default>;
+				interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			uart1: serial@884000 {
+				compatible = "qcom,geni-uart";
+				reg = <0 0x00884000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_uart1_default>;
+				interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			i2c2: i2c@888000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0 0x00888000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_i2c2_default>;
+				interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			uart2: serial@888000 {
+				compatible = "qcom,geni-uart";
+				reg = <0 0x00888000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_uart2_default>;
+				interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			i2c3: i2c@88c000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0 0x0088c000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_i2c3_default>;
+				interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			spi3: spi@88c000 {
+				compatible = "qcom,geni-spi";
+				reg = <0 0x0088c000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_spi3_default>;
+				interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			uart3: serial@88c000 {
+				compatible = "qcom,geni-uart";
+				reg = <0 0x0088c000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_uart3_default>;
+				interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			i2c4: i2c@890000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0 0x00890000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_i2c4_default>;
+				interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			uart4: serial@890000 {
+				compatible = "qcom,geni-uart";
+				reg = <0 0x00890000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_uart4_default>;
+				interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			i2c5: i2c@894000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0 0x00894000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_i2c5_default>;
+				interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			spi5: spi@894000 {
+				compatible = "qcom,geni-spi";
+				reg = <0 0x00894000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_spi5_default>;
+				interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			uart5: serial@894000 {
+				compatible = "qcom,geni-uart";
+				reg = <0 0x00894000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_uart5_default>;
+				interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+		};
+
 		qupv3_id_1: geniqup@ac0000 {
 			compatible = "qcom,geni-se-qup";
 			reg = <0 0x00ac0000 0 0x6000>;
@@ -194,6 +402,93 @@
 			ranges;
 			status = "disabled";
 
+			i2c6: i2c@a80000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0 0x00a80000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_i2c6_default>;
+				interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			spi6: spi@a80000 {
+				compatible = "qcom,geni-spi";
+				reg = <0 0x00a80000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_spi6_default>;
+				interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			uart6: serial@a80000 {
+				compatible = "qcom,geni-uart";
+				reg = <0 0x00a80000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_uart6_default>;
+				interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			i2c7: i2c@a84000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0 0x00a84000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_i2c7_default>;
+				interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			uart7: serial@a84000 {
+				compatible = "qcom,geni-uart";
+				reg = <0 0x00a84000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_uart7_default>;
+				interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			i2c8: i2c@a88000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0 0x00a88000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_i2c8_default>;
+				interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			spi8: spi@a88000 {
+				compatible = "qcom,geni-spi";
+				reg = <0 0x00a88000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_spi8_default>;
+				interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
 			uart8: serial@a88000 {
 				compatible = "qcom,geni-debug-uart";
 				reg = <0 0x00a88000 0 0x4000>;
@@ -204,6 +499,104 @@
 				interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
 				status = "disabled";
 			};
+
+			i2c9: i2c@a8c000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0 0x00a8c000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_i2c9_default>;
+				interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			uart9: serial@a8c000 {
+				compatible = "qcom,geni-uart";
+				reg = <0 0x00a8c000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_uart9_default>;
+				interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			i2c10: i2c@a90000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0 0x00a90000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_i2c10_default>;
+				interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			spi10: spi@a90000 {
+				compatible = "qcom,geni-spi";
+				reg = <0 0x00a90000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_spi10_default>;
+				interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			uart10: serial@a90000 {
+				compatible = "qcom,geni-uart";
+				reg = <0 0x00a90000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_uart10_default>;
+				interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			i2c11: i2c@a94000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0 0x00a94000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_i2c11_default>;
+				interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			spi11: spi@a94000 {
+				compatible = "qcom,geni-spi";
+				reg = <0 0x00a94000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_spi11_default>;
+				interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			uart11: serial@a94000 {
+				compatible = "qcom,geni-uart";
+				reg = <0 0x00a94000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_uart11_default>;
+				interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
 		};
 
 		pdc: interrupt-controller@b220000 {
@@ -229,12 +622,294 @@
 			#interrupt-cells = <2>;
 			gpio-ranges = <&tlmm 0 0 120>;
 
+			qspi_clk: qspi-clk {
+				pinmux {
+					pins = "gpio63";
+					function = "qspi_clk";
+				};
+			};
+
+			qspi_cs0: qspi-cs0 {
+				pinmux {
+					pins = "gpio68";
+					function = "qspi_cs";
+				};
+			};
+
+			qspi_cs1: qspi-cs1 {
+				pinmux {
+					pins = "gpio72";
+					function = "qspi_cs";
+				};
+			};
+
+			qspi_data01: qspi-data01 {
+				pinmux-data {
+					pins = "gpio64", "gpio65";
+					function = "qspi_data";
+				};
+			};
+
+			qspi_data12: qspi-data12 {
+				pinmux-data {
+					pins = "gpio66", "gpio67";
+					function = "qspi_data";
+				};
+			};
+
+			qup_i2c0_default: qup-i2c0-default {
+				pinmux {
+					pins = "gpio34", "gpio35";
+					function = "qup00";
+				};
+			};
+
+			qup_i2c1_default: qup-i2c1-default {
+				pinmux {
+					pins = "gpio0", "gpio1";
+					function = "qup01";
+				};
+			};
+
+			qup_i2c2_default: qup-i2c2-default {
+				pinmux {
+					pins = "gpio15", "gpio16";
+					function = "qup02";
+				};
+			};
+
+			qup_i2c3_default: qup-i2c3-default {
+				pinmux {
+					pins = "gpio38", "gpio39";
+					function = "qup03";
+				};
+			};
+
+			qup_i2c4_default: qup-i2c4-default {
+				pinmux {
+					pins = "gpio115", "gpio116";
+					function = "qup04";
+				};
+			};
+
+			qup_i2c5_default: qup-i2c5-default {
+				pinmux {
+					pins = "gpio25", "gpio26";
+					function = "qup05";
+				};
+			};
+
+			qup_i2c6_default: qup-i2c6-default {
+				pinmux {
+					pins = "gpio59", "gpio60";
+					function = "qup10";
+				};
+			};
+
+			qup_i2c7_default: qup-i2c7-default {
+				pinmux {
+					pins = "gpio6", "gpio7";
+					function = "qup11";
+				};
+			};
+
+			qup_i2c8_default: qup-i2c8-default {
+				pinmux {
+					pins = "gpio42", "gpio43";
+					function = "qup12";
+				};
+			};
+
+			qup_i2c9_default: qup-i2c9-default {
+				pinmux {
+					pins = "gpio46", "gpio47";
+					function = "qup13";
+				};
+			};
+
+			qup_i2c10_default: qup-i2c10-default {
+				pinmux {
+					pins = "gpio86", "gpio87";
+					function = "qup14";
+				};
+			};
+
+			qup_i2c11_default: qup-i2c11-default {
+				pinmux {
+					pins = "gpio53", "gpio54";
+					function = "qup15";
+				};
+			};
+
+			qup_spi0_default: qup-spi0-default {
+				pinmux {
+					pins = "gpio34", "gpio35",
+					       "gpio36", "gpio37";
+					function = "qup00";
+				};
+			};
+
+			qup_spi1_default: qup-spi1-default {
+				pinmux {
+					pins = "gpio0", "gpio1",
+					       "gpio2", "gpio3",
+					       "gpio12", "gpio94";
+					function = "qup01";
+				};
+			};
+
+			qup_spi3_default: qup-spi3-default {
+				pinmux {
+					pins = "gpio38", "gpio39",
+					       "gpio40", "gpio41";
+					function = "qup03";
+				};
+			};
+
+			qup_spi5_default: qup-spi5-default {
+				pinmux {
+					pins = "gpio25", "gpio26",
+					       "gpio27", "gpio28";
+					function = "qup05";
+				};
+			};
+
+			qup_spi6_default: qup-spi6-default {
+				pinmux {
+					pins = "gpio59", "gpio60",
+					       "gpio61", "gpio62",
+					       "gpio68", "gpio72";
+					function = "qup10";
+				};
+			};
+
+			qup_spi8_default: qup-spi8-default {
+				pinmux {
+					pins = "gpio42", "gpio43",
+					       "gpio44", "gpio45";
+					function = "qup12";
+				};
+			};
+
+			qup_spi10_default: qup-spi10-default {
+				pinmux {
+					pins = "gpio86", "gpio87",
+					       "gpio88", "gpio89",
+					       "gpio90", "gpio91";
+					function = "qup14";
+				};
+			};
+
+			qup_spi11_default: qup-spi11-default {
+				pinmux {
+					pins = "gpio53", "gpio54",
+					       "gpio55", "gpio56";
+					function = "qup15";
+				};
+			};
+
+			qup_uart0_default: qup-uart0-default {
+				pinmux {
+					pins = "gpio34", "gpio35",
+					       "gpio36", "gpio37";
+					function = "qup00";
+				};
+			};
+
+			qup_uart1_default: qup-uart1-default {
+				pinmux {
+					pins = "gpio0", "gpio1",
+					       "gpio2", "gpio3";
+					function = "qup01";
+				};
+			};
+
+			qup_uart2_default: qup-uart2-default {
+				pinmux {
+					pins = "gpio15", "gpio16";
+					function = "qup02";
+				};
+			};
+
+			qup_uart3_default: qup-uart3-default {
+				pinmux {
+					pins = "gpio38", "gpio39",
+					       "gpio40", "gpio41";
+					function = "qup03";
+				};
+			};
+
+			qup_uart4_default: qup-uart4-default {
+				pinmux {
+					pins = "gpio115", "gpio116";
+					function = "qup04";
+				};
+			};
+
+			qup_uart5_default: qup-uart5-default {
+				pinmux {
+					pins = "gpio25", "gpio26",
+					       "gpio27", "gpio28";
+					function = "qup05";
+				};
+			};
+
+			qup_uart6_default: qup-uart6-default {
+				pinmux {
+					pins = "gpio59", "gpio60",
+					       "gpio61", "gpio62";
+					function = "qup10";
+				};
+			};
+
+			qup_uart7_default: qup-uart7-default {
+				pinmux {
+					pins = "gpio6", "gpio7";
+					function = "qup11";
+				};
+			};
+
 			qup_uart8_default: qup-uart8-default {
 				pinmux {
 					pins = "gpio44", "gpio45";
 					function = "qup12";
 				};
 			};
+
+			qup_uart9_default: qup-uart9-default {
+				pinmux {
+					pins = "gpio46", "gpio47";
+					function = "qup13";
+				};
+			};
+
+			qup_uart10_default: qup-uart10-default {
+				pinmux {
+					pins = "gpio86", "gpio87",
+					       "gpio88", "gpio89";
+					function = "qup14";
+				};
+			};
+
+			qup_uart11_default: qup-uart11-default {
+				pinmux {
+					pins = "gpio53", "gpio54",
+					       "gpio55", "gpio56";
+					function = "qup15";
+				};
+			};
+		};
+
+		qspi: spi@88dc000 {
+			compatible = "qcom,qspi-v1";
+			reg = <0 0x088dc000 0 0x600>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
+				 <&gcc GCC_QSPI_CORE_CLK>;
+			clock-names = "iface", "core";
+			status = "disabled";
 		};
 
 		spmi_bus: spmi@c440000 {
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation


^ permalink raw reply	[flat|nested] 40+ messages in thread

* Re: [PATCH v4 08/14] dt-bindings: qcom,pdc: Add compatible for sc7180
  2019-11-06  6:50 ` [PATCH v4 08/14] dt-bindings: qcom,pdc: Add compatible for sc7180 Rajendra Nayak
@ 2019-11-06 16:56   ` Rob Herring
  2019-11-07  5:46     ` Rajendra Nayak
  2019-11-06 19:11   ` Stephen Boyd
  1 sibling, 1 reply; 40+ messages in thread
From: Rob Herring @ 2019-11-06 16:56 UTC (permalink / raw)
  To: Rajendra Nayak
  Cc: agross, robh+dt, bjorn.andersson, linux-arm-msm, devicetree,
	linux-kernel, mka, swboyd, Rajendra Nayak, Lina Iyer,
	Marc Zyngier

On Wed,  6 Nov 2019 12:20:11 +0530, Rajendra Nayak wrote:
> Add the compatible string for sc7180 SoC from Qualcomm.
> 
> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
> Cc: Lina Iyer <ilina@codeaurora.org>
> Cc: Marc Zyngier <maz@kernel.org>
> ---
>  .../devicetree/bindings/interrupt-controller/qcom,pdc.txt      | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 

Please add Acked-by/Reviewed-by tags when posting new versions. However,
there's no need to repost patches *only* to add the tags. The upstream
maintainer will do that for acks received on the version they apply.

If a tag was not added on purpose, please state why and what changed.

^ permalink raw reply	[flat|nested] 40+ messages in thread

* Re: [PATCH v4 07/14] drivers: irqchip: qcom-pdc: Move to an SoC independent compatible
  2019-11-06  6:50 ` [PATCH v4 07/14] drivers: irqchip: qcom-pdc: Move to an SoC independent compatible Rajendra Nayak
@ 2019-11-06 18:20   ` Lina Iyer
  2019-11-06 19:10   ` Stephen Boyd
  1 sibling, 0 replies; 40+ messages in thread
From: Lina Iyer @ 2019-11-06 18:20 UTC (permalink / raw)
  To: Rajendra Nayak
  Cc: agross, robh+dt, bjorn.andersson, linux-arm-msm, devicetree,
	linux-kernel, mka, swboyd, Marc Zyngier

On Wed, Nov 06 2019 at 23:52 -0700, Rajendra Nayak wrote:
>Remove the sdm845 SoC specific compatible to make the driver
>easily reusable across other SoC's with the same IP block.
>This will reduce further churn adding any SoC specific
>compatibles unless really needed.
>
>Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
>Cc: Lina Iyer <ilina@codeaurora.org>
>Cc: Marc Zyngier <maz@kernel.org>
Reviewed-by: Lina Iyer <ilina@codeaurora.org>

>---
> drivers/irqchip/qcom-pdc.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
>diff --git a/drivers/irqchip/qcom-pdc.c b/drivers/irqchip/qcom-pdc.c
>index faa7d61b9d6c..c175333bb646 100644
>--- a/drivers/irqchip/qcom-pdc.c
>+++ b/drivers/irqchip/qcom-pdviewed-by: Lina Iyer <ilina@codeaurora.org>
>@@ -309,4 +309,4 @@ static int qcom_pdc_init(struct device_node *node, struct device_node *parent)
> 	return ret;
> }
>
>-IRQCHIP_DECLARE(pdc_sdm845, "qcom,sdm845-pdc", qcom_pdc_init);
>+IRQCHIP_DECLARE(qcom_pdc, "qcom,pdc", qcom_pdc_init);
>--
>QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
>of Code Aurora Forum, hosted by The Linux Foundation
>

^ permalink raw reply	[flat|nested] 40+ messages in thread

* Re: [PATCH v4 07/14] drivers: irqchip: qcom-pdc: Move to an SoC independent compatible
  2019-11-06  6:50 ` [PATCH v4 07/14] drivers: irqchip: qcom-pdc: Move to an SoC independent compatible Rajendra Nayak
  2019-11-06 18:20   ` Lina Iyer
@ 2019-11-06 19:10   ` Stephen Boyd
  1 sibling, 0 replies; 40+ messages in thread
From: Stephen Boyd @ 2019-11-06 19:10 UTC (permalink / raw)
  To: Rajendra Nayak, agross, bjorn.andersson, robh+dt
  Cc: linux-arm-msm, devicetree, linux-kernel, mka, Rajendra Nayak,
	Lina Iyer, Marc Zyngier

Quoting Rajendra Nayak (2019-11-05 22:50:10)
> Remove the sdm845 SoC specific compatible to make the driver
> easily reusable across other SoC's with the same IP block.
> This will reduce further churn adding any SoC specific
> compatibles unless really needed.
> 
> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
> Cc: Lina Iyer <ilina@codeaurora.org>
> Cc: Marc Zyngier <maz@kernel.org>
> ---

Reviewed-by: Stephen Boyd <swboyd@chromium.org>


^ permalink raw reply	[flat|nested] 40+ messages in thread

* Re: [PATCH v4 08/14] dt-bindings: qcom,pdc: Add compatible for sc7180
  2019-11-06  6:50 ` [PATCH v4 08/14] dt-bindings: qcom,pdc: Add compatible for sc7180 Rajendra Nayak
  2019-11-06 16:56   ` Rob Herring
@ 2019-11-06 19:11   ` Stephen Boyd
  1 sibling, 0 replies; 40+ messages in thread
From: Stephen Boyd @ 2019-11-06 19:11 UTC (permalink / raw)
  To: Rajendra Nayak, agross, bjorn.andersson, robh+dt
  Cc: linux-arm-msm, devicetree, linux-kernel, mka, Rajendra Nayak,
	Lina Iyer, Marc Zyngier

Quoting Rajendra Nayak (2019-11-05 22:50:11)
> Add the compatible string for sc7180 SoC from Qualcomm.
> 
> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
> Cc: Lina Iyer <ilina@codeaurora.org>
> Cc: Marc Zyngier <maz@kernel.org>
> ---

Reviewed-by: Stephen Boyd <swboyd@chromium.org>


^ permalink raw reply	[flat|nested] 40+ messages in thread

* Re: [PATCH v4 09/14] arm64: dts: qcom: sc7180: Add pdc interrupt controller
  2019-11-06  6:50 ` [PATCH v4 09/14] arm64: dts: qcom: sc7180: Add pdc interrupt controller Rajendra Nayak
@ 2019-11-06 19:11   ` Stephen Boyd
  0 siblings, 0 replies; 40+ messages in thread
From: Stephen Boyd @ 2019-11-06 19:11 UTC (permalink / raw)
  To: Rajendra Nayak, agross, bjorn.andersson, robh+dt
  Cc: linux-arm-msm, devicetree, linux-kernel, mka, Maulik Shah,
	Rajendra Nayak

Quoting Rajendra Nayak (2019-11-05 22:50:12)
> From: Maulik Shah <mkshah@codeaurora.org>
> 
> Add pdc interrupt controller for sc7180
> 
> Signed-off-by: Maulik Shah <mkshah@codeaurora.org>
> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
> ---

Reviewed-by: Stephen Boyd <swboyd@chromium.org>


^ permalink raw reply	[flat|nested] 40+ messages in thread

* Re: [PATCH v4 01/14] dt-bindings: qcom: Add SC7180 bindings
  2019-11-06  6:50 ` [PATCH v4 01/14] dt-bindings: qcom: Add SC7180 bindings Rajendra Nayak
@ 2019-11-07  0:48   ` Rob Herring
  2019-11-07 17:43   ` Stephen Boyd
  1 sibling, 0 replies; 40+ messages in thread
From: Rob Herring @ 2019-11-07  0:48 UTC (permalink / raw)
  To: Rajendra Nayak
  Cc: agross, robh+dt, bjorn.andersson, linux-arm-msm, devicetree,
	linux-kernel, mka, swboyd, Rajendra Nayak, Vinod Koul

On Wed,  6 Nov 2019 12:20:04 +0530, Rajendra Nayak wrote:
> Add a SoC string 'sc7180' for the qualcomm SC7180 SoC.
> Also add a new board type 'idp'
> 
> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
> Reviewed-by: Vinod Koul <vkoul@kernel.org>
> ---
> v4: Added schema for sc7180 IDP board
> 
>  Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++++++
>  1 file changed, 6 insertions(+)
> 

Reviewed-by: Rob Herring <robh@kernel.org>

^ permalink raw reply	[flat|nested] 40+ messages in thread

* Re: [PATCH v4 03/14] dt-bindings: arm-smmu: update binding for qcom sc7180 SoC
  2019-11-06  6:50 ` [PATCH v4 03/14] dt-bindings: arm-smmu: update binding for qcom sc7180 SoC Rajendra Nayak
@ 2019-11-07  0:49   ` Rob Herring
  2019-11-07 17:47   ` Stephen Boyd
  1 sibling, 0 replies; 40+ messages in thread
From: Rob Herring @ 2019-11-07  0:49 UTC (permalink / raw)
  To: Rajendra Nayak
  Cc: agross, robh+dt, bjorn.andersson, linux-arm-msm, devicetree,
	linux-kernel, mka, swboyd, Rajendra Nayak, Joerg Roedel,
	Mark Rutland

On Wed,  6 Nov 2019 12:20:06 +0530, Rajendra Nayak wrote:
> Add the soc specific compatible for sc7180 smmu-500
> 
> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
> Cc: Joerg Roedel <joro@8bytes.org>
> Cc: Mark Rutland <mark.rutland@arm.com>
> ---
> v4: Updated yaml, sorted.
> 
>  Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 1 +
>  1 file changed, 1 insertion(+)
> 

As this one is dependent on my tree, I've applied it.

Rob

^ permalink raw reply	[flat|nested] 40+ messages in thread

* Re: [PATCH v4 08/14] dt-bindings: qcom,pdc: Add compatible for sc7180
  2019-11-06 16:56   ` Rob Herring
@ 2019-11-07  5:46     ` Rajendra Nayak
  2019-11-08 23:46       ` Rob Herring
  0 siblings, 1 reply; 40+ messages in thread
From: Rajendra Nayak @ 2019-11-07  5:46 UTC (permalink / raw)
  To: Rob Herring
  Cc: agross, robh+dt, bjorn.andersson, linux-arm-msm, devicetree,
	linux-kernel, mka, swboyd, Lina Iyer, Marc Zyngier



On 11/6/2019 10:26 PM, Rob Herring wrote:
> On Wed,  6 Nov 2019 12:20:11 +0530, Rajendra Nayak wrote:
>> Add the compatible string for sc7180 SoC from Qualcomm.
>>
>> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
>> Cc: Lina Iyer <ilina@codeaurora.org>
>> Cc: Marc Zyngier <maz@kernel.org>
>> ---
>>   .../devicetree/bindings/interrupt-controller/qcom,pdc.txt      | 3 ++-
>>   1 file changed, 2 insertions(+), 1 deletion(-)
>>
> 
> Please add Acked-by/Reviewed-by tags when posting new versions. However,
> there's no need to repost patches *only* to add the tags. The upstream
> maintainer will do that for acks received on the version they apply.
> 
> If a tag was not added on purpose, please state why and what changed.

Sorry I missed mentioning the delta and the reason for not including your Acked-by.
The previous patch was proposing using just a SoC specific compatible, and this
one adds a SoC independent one along with the SoC specific one as discussed here [1]

[1] https://lkml.org/lkml/2019/11/4/73

-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

^ permalink raw reply	[flat|nested] 40+ messages in thread

* Re: [PATCH v4 01/14] dt-bindings: qcom: Add SC7180 bindings
  2019-11-06  6:50 ` [PATCH v4 01/14] dt-bindings: qcom: Add SC7180 bindings Rajendra Nayak
  2019-11-07  0:48   ` Rob Herring
@ 2019-11-07 17:43   ` Stephen Boyd
  2019-11-08  3:02     ` Rajendra Nayak
  1 sibling, 1 reply; 40+ messages in thread
From: Stephen Boyd @ 2019-11-07 17:43 UTC (permalink / raw)
  To: Rajendra Nayak, agross, bjorn.andersson, robh+dt
  Cc: linux-arm-msm, devicetree, linux-kernel, mka, Rajendra Nayak, Vinod Koul

Quoting Rajendra Nayak (2019-11-05 22:50:04)
> Add a SoC string 'sc7180' for the qualcomm SC7180 SoC.
> Also add a new board type 'idp'
> 
> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
> Reviewed-by: Vinod Koul <vkoul@kernel.org>
> ---

Reviewed-by: Stephen Boyd <swboyd@chromium.org>

I see that it isn't sorted but o well!


^ permalink raw reply	[flat|nested] 40+ messages in thread

* Re: [PATCH v4 02/14] arm64: dts: sc7180: Add minimal dts/dtsi files for SC7180 soc
  2019-11-06  6:50 ` [PATCH v4 02/14] arm64: dts: sc7180: Add minimal dts/dtsi files for SC7180 soc Rajendra Nayak
@ 2019-11-07 17:46   ` Stephen Boyd
  2019-11-08  3:48     ` Rajendra Nayak
  0 siblings, 1 reply; 40+ messages in thread
From: Stephen Boyd @ 2019-11-07 17:46 UTC (permalink / raw)
  To: Rajendra Nayak, agross, bjorn.andersson, robh+dt
  Cc: linux-arm-msm, devicetree, linux-kernel, mka, Rajendra Nayak, Taniya Das

Quoting Rajendra Nayak (2019-11-05 22:50:05)
> diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> new file mode 100644
> index 000000000000..17870dd67390
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> @@ -0,0 +1,299 @@
> +// SPDX-License-Identifier: BSD-3-Clause
> +/*
> + * SC7180 SoC device tree source
> + *
> + * Copyright (c) 2019, The Linux Foundation. All rights reserved.
> + */
> +
> +#include <dt-bindings/clock/qcom,gcc-sc7180.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +/ {
> +       interrupt-parent = <&intc>;
> +
> +       #address-cells = <2>;
> +       #size-cells = <2>;
> +
> +       chosen { };
> +
> +       clocks {
> +               xo_board: xo-board {
> +                       compatible = "fixed-clock";
> +                       clock-frequency = <38400000>;
> +                       #clock-cells = <0>;
> +               };
> +
> +               sleep_clk: sleep-clk {
> +                       compatible = "fixed-clock";
> +                       clock-frequency = <32764>;
> +                       clock-output-names = "sleep_clk";

Remove this one too?

> +                       #clock-cells = <0>;
> +               };
> +       };
> +
[...]
> +       memory@80000000 {
> +               device_type = "memory";
> +               /* We expect the bootloader to fill in the size */
> +               reg = <0 0x80000000 0 0>;
> +       };
> +
> +       pmu {
> +               compatible = "arm,armv8-pmuv3";
> +               interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
> +       };
> +
> +       psci {
> +               compatible = "arm,psci-1.0";
> +               method = "smc";
> +       };
> +
> +       soc: soc {
> +               #address-cells = <2>;
> +               #size-cells = <2>;
> +               ranges = <0 0 0 0 0x10 0>;
> +               dma-ranges = <0 0 0 0 0x10 0>;
> +               compatible = "simple-bus";
> +
> +               gcc: clock-controller@100000 {
> +                       compatible = "qcom,gcc-sc7180";
> +                       reg = <0 0x00100000 0 0x1f0000>;
> +                       #clock-cells = <1>;
> +                       #reset-cells = <1>;
> +                       #power-domain-cells = <1>;
> +               };
> +
> +               qupv3_id_1: geniqup@ac0000 {
> +                       compatible = "qcom,geni-se-qup";
> +                       reg = <0 0x00ac0000 0 0x6000>;
> +                       clock-names = "m-ahb", "s-ahb";
> +                       clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
> +                                <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
> +                       #address-cells = <2>;
> +                       #size-cells = <2>;
> +                       ranges;
> +                       status = "disabled";
> +
> +                       uart8: serial@a88000 {
> +                               compatible = "qcom,geni-debug-uart";
> +                               reg = <0 0x00a88000 0 0x4000>;
> +                               clock-names = "se";
> +                               clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
> +                               pinctrl-names = "default";
> +                               pinctrl-0 = <&qup_uart8_default>;
> +                               interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
> +                               status = "disabled";
> +                       };
> +               };
> +
> +               tlmm: pinctrl@3500000 {
> +                       compatible = "qcom,sc7180-pinctrl";
> +                       reg = <0 0x03500000 0 0x300000>,
> +                             <0 0x03900000 0 0x300000>,
> +                             <0 0x03d00000 0 0x300000>;
> +                       reg-names = "west", "north", "south";
> +                       interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
> +                       gpio-controller;
> +                       #gpio-cells = <2>;
> +                       interrupt-controller;
> +                       #interrupt-cells = <2>;
> +                       gpio-ranges = <&tlmm 0 0 120>;
> +
> +                       qup_uart8_default: qup-uart8-default {
> +                               pinmux {
> +                                       pins = "gpio44", "gpio45";
> +                                       function = "qup12";

That looks weird to have qup12 function on uart8. It's right?

> +                               };
> +                       };
> +               };
> +

^ permalink raw reply	[flat|nested] 40+ messages in thread

* Re: [PATCH v4 03/14] dt-bindings: arm-smmu: update binding for qcom sc7180 SoC
  2019-11-06  6:50 ` [PATCH v4 03/14] dt-bindings: arm-smmu: update binding for qcom sc7180 SoC Rajendra Nayak
  2019-11-07  0:49   ` Rob Herring
@ 2019-11-07 17:47   ` Stephen Boyd
  1 sibling, 0 replies; 40+ messages in thread
From: Stephen Boyd @ 2019-11-07 17:47 UTC (permalink / raw)
  To: Rajendra Nayak, agross, bjorn.andersson, robh+dt
  Cc: linux-arm-msm, devicetree, linux-kernel, mka, Rajendra Nayak,
	Joerg Roedel, Mark Rutland

Quoting Rajendra Nayak (2019-11-05 22:50:06)
> Add the soc specific compatible for sc7180 smmu-500
> 
> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
> Cc: Joerg Roedel <joro@8bytes.org>
> Cc: Mark Rutland <mark.rutland@arm.com>
> ---

Reviewed-by: Stephen Boyd <swboyd@chromium.org>


^ permalink raw reply	[flat|nested] 40+ messages in thread

* Re: [PATCH v4 04/14] arm64: dts: sc7180: Add device node for apps_smmu
  2019-11-06  6:50 ` [PATCH v4 04/14] arm64: dts: sc7180: Add device node for apps_smmu Rajendra Nayak
@ 2019-11-07 17:47   ` Stephen Boyd
  0 siblings, 0 replies; 40+ messages in thread
From: Stephen Boyd @ 2019-11-07 17:47 UTC (permalink / raw)
  To: Rajendra Nayak, agross, bjorn.andersson, robh+dt
  Cc: linux-arm-msm, devicetree, linux-kernel, mka, Vivek Gautam,
	Rajendra Nayak

Quoting Rajendra Nayak (2019-11-05 22:50:07)
> From: Vivek Gautam <vivek.gautam@codeaurora.org>
> 
> Adding device node for APPS SMMU that is connected to
> devices such as display, video, usb, mmc, etc. on SC7180
> chipset.
> 
> Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org>
> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
> ---

Reviewed-by: Stephen Boyd <swboyd@chromium.org>


^ permalink raw reply	[flat|nested] 40+ messages in thread

* Re: [PATCH v4 05/14] arm64: dts: qcom: sc7180: Add cmd_db reserved area
  2019-11-06  6:50 ` [PATCH v4 05/14] arm64: dts: qcom: sc7180: Add cmd_db reserved area Rajendra Nayak
@ 2019-11-07 17:47   ` Stephen Boyd
  0 siblings, 0 replies; 40+ messages in thread
From: Stephen Boyd @ 2019-11-07 17:47 UTC (permalink / raw)
  To: Rajendra Nayak, agross, bjorn.andersson, robh+dt
  Cc: linux-arm-msm, devicetree, linux-kernel, mka, Maulik Shah,
	Rajendra Nayak

Quoting Rajendra Nayak (2019-11-05 22:50:08)
> From: Maulik Shah <mkshah@codeaurora.org>
> 
> Command_db provides mapping for resource key and address managed
> by remote processor. Add cmd_db reserved memory area.
> 
> Signed-off-by: Maulik Shah <mkshah@codeaurora.org>
> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
> ---

Reviewed-by: Stephen Boyd <swboyd@chromium.org>


^ permalink raw reply	[flat|nested] 40+ messages in thread

* Re: [PATCH v4 06/14] arm64: dts: qcom: sc7180: Add rpmh-rsc node
  2019-11-06  6:50 ` [PATCH v4 06/14] arm64: dts: qcom: sc7180: Add rpmh-rsc node Rajendra Nayak
@ 2019-11-07 17:53   ` Stephen Boyd
  2019-11-08  3:50     ` Rajendra Nayak
  2019-11-07 17:53   ` Stephen Boyd
  1 sibling, 1 reply; 40+ messages in thread
From: Stephen Boyd @ 2019-11-07 17:53 UTC (permalink / raw)
  To: Rajendra Nayak, agross, bjorn.andersson, robh+dt
  Cc: linux-arm-msm, devicetree, linux-kernel, mka, Maulik Shah,
	Rajendra Nayak

Quoting Rajendra Nayak (2019-11-05 22:50:09)
> diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> index 61250560c7ef..98c8ab7d613c 100644
> --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> @@ -387,6 +388,24 @@
>                                 status = "disabled";
>                         };
>                 };
> +
> +               apps_rsc: rsc@18200000 {

The node name is non-standard. This has been a problem since sdm845
though so it would be nice if we can invent some new name for this that
is standard at some point in the future.

> +                       label = "apps_rsc";

Can we remove this property? The value seems minimal given that we can
use the dev_name() and get the address in there instead of using a label.


^ permalink raw reply	[flat|nested] 40+ messages in thread

* Re: [PATCH v4 06/14] arm64: dts: qcom: sc7180: Add rpmh-rsc node
  2019-11-06  6:50 ` [PATCH v4 06/14] arm64: dts: qcom: sc7180: Add rpmh-rsc node Rajendra Nayak
  2019-11-07 17:53   ` Stephen Boyd
@ 2019-11-07 17:53   ` Stephen Boyd
  1 sibling, 0 replies; 40+ messages in thread
From: Stephen Boyd @ 2019-11-07 17:53 UTC (permalink / raw)
  To: Rajendra Nayak, agross, bjorn.andersson, robh+dt
  Cc: linux-arm-msm, devicetree, linux-kernel, mka, Maulik Shah,
	Rajendra Nayak

Quoting Rajendra Nayak (2019-11-05 22:50:09)
> From: Maulik Shah <mkshah@codeaurora.org>
> 
> Add device bindings for the application processor's rsc. The rsc
> contains the TCS that are used for communicating with the hardened
> resource accelerators on Qualcomm Technologies, Inc. (QTI) SoCs.
> 
> Signed-off-by: Maulik Shah <mkshah@codeaurora.org>
> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
> ---

Reviewed-by: Stephen Boyd <swboyd@chromium.org>


^ permalink raw reply	[flat|nested] 40+ messages in thread

* Re: [PATCH v4 10/14] arm64: dts: qcom: sc7180: Add SPMI PMIC arbiter device
  2019-11-06  6:50 ` [PATCH v4 10/14] arm64: dts: qcom: sc7180: Add SPMI PMIC arbiter device Rajendra Nayak
@ 2019-11-07 17:54   ` Stephen Boyd
  0 siblings, 0 replies; 40+ messages in thread
From: Stephen Boyd @ 2019-11-07 17:54 UTC (permalink / raw)
  To: Rajendra Nayak, agross, bjorn.andersson, robh+dt
  Cc: linux-arm-msm, devicetree, linux-kernel, mka, Kiran Gunda,
	Rajendra Nayak

Quoting Rajendra Nayak (2019-11-05 22:50:13)
> From: Kiran Gunda <kgunda@codeaurora.org>
> 
> Add SPMI PMIC arbiter device to communicate with PMICs
> attached to SPMI bus.
> 
> Signed-off-by: Kiran Gunda <kgunda@codeaurora.org>
> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
> ---

Reviewed-by: Stephen Boyd <swboyd@chromium.org>


^ permalink raw reply	[flat|nested] 40+ messages in thread

* Re: [PATCH v4 11/14] arm64: dts: qcom: pm6150: Add PM6150/PM6150L PMIC peripherals
  2019-11-06  6:50 ` [PATCH v4 11/14] arm64: dts: qcom: pm6150: Add PM6150/PM6150L PMIC peripherals Rajendra Nayak
@ 2019-11-07 17:59   ` Stephen Boyd
  0 siblings, 0 replies; 40+ messages in thread
From: Stephen Boyd @ 2019-11-07 17:59 UTC (permalink / raw)
  To: Rajendra Nayak, agross, bjorn.andersson, robh+dt
  Cc: linux-arm-msm, devicetree, linux-kernel, mka, Kiran Gunda,
	Rajendra Nayak

Quoting Rajendra Nayak (2019-11-05 22:50:14)
> From: Kiran Gunda <kgunda@codeaurora.org>
> 
> Add PM6150/PM6150L peripherals such as PON, GPIOs, ADC and other
> PMIC infra modules.
> 
> Signed-off-by: Kiran Gunda <kgunda@codeaurora.org>
> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
> ---

Reviewed-by: Stephen Boyd <swboyd@chromium.org>


^ permalink raw reply	[flat|nested] 40+ messages in thread

* Re: [PATCH v4 13/14] arm64: dts: qcom: SC7180: Add node for rpmhcc clock driver
  2019-11-06  6:50 ` [PATCH v4 13/14] arm64: dts: qcom: SC7180: Add node for rpmhcc clock driver Rajendra Nayak
@ 2019-11-07 18:50   ` Stephen Boyd
  0 siblings, 0 replies; 40+ messages in thread
From: Stephen Boyd @ 2019-11-07 18:50 UTC (permalink / raw)
  To: Rajendra Nayak, agross, bjorn.andersson, robh+dt
  Cc: linux-arm-msm, devicetree, linux-kernel, mka, Taniya Das, Rajendra Nayak

Quoting Rajendra Nayak (2019-11-05 22:50:16)
> From: Taniya Das <tdas@codeaurora.org>
> 
> Add node for rpmhcc clock driver.
> 
> Signed-off-by: Taniya Das <tdas@codeaurora.org>
> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
> ---

Reviewed-by: Stephen Boyd <swboyd@chromium.org>


^ permalink raw reply	[flat|nested] 40+ messages in thread

* Re: [PATCH v4 14/14] arm64: dts: sc7180: Add qupv3_0 and qupv3_1
  2019-11-06  6:50 ` [PATCH v4 14/14] arm64: dts: sc7180: Add qupv3_0 and qupv3_1 Rajendra Nayak
@ 2019-11-07 18:52   ` Stephen Boyd
  2019-11-08  3:52     ` Rajendra Nayak
  0 siblings, 1 reply; 40+ messages in thread
From: Stephen Boyd @ 2019-11-07 18:52 UTC (permalink / raw)
  To: Rajendra Nayak, agross, bjorn.andersson, robh+dt
  Cc: linux-arm-msm, devicetree, linux-kernel, mka,
	Roja Rani Yarubandi, Rajendra Nayak

Quoting Rajendra Nayak (2019-11-05 22:50:17)
> From: Roja Rani Yarubandi <rojay@codeaurora.org>
> 
> Add QUP SE instances configuration for sc7180.
> 
> Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org>
> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
> ---

Reviewed-by: Stephen Boyd <swboyd@chromium.org>

It has the weird qup numbering too, but I guess it's correct somehow.


^ permalink raw reply	[flat|nested] 40+ messages in thread

* Re: [PATCH v4 01/14] dt-bindings: qcom: Add SC7180 bindings
  2019-11-07 17:43   ` Stephen Boyd
@ 2019-11-08  3:02     ` Rajendra Nayak
  0 siblings, 0 replies; 40+ messages in thread
From: Rajendra Nayak @ 2019-11-08  3:02 UTC (permalink / raw)
  To: Stephen Boyd, agross, bjorn.andersson, robh+dt
  Cc: linux-arm-msm, devicetree, linux-kernel, mka, Vinod Koul



On 11/7/2019 11:13 PM, Stephen Boyd wrote:
> Quoting Rajendra Nayak (2019-11-05 22:50:04)
>> Add a SoC string 'sc7180' for the qualcomm SC7180 SoC.
>> Also add a new board type 'idp'
>>
>> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
>> Reviewed-by: Vinod Koul <vkoul@kernel.org>
>> ---
> 
> Reviewed-by: Stephen Boyd <swboyd@chromium.org>
> 
> I see that it isn't sorted but o well!

Well, it wasn't sorted to begin with, so I left it unsorted ¯\_(ツ)_/¯

-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

^ permalink raw reply	[flat|nested] 40+ messages in thread

* Re: [PATCH v4 02/14] arm64: dts: sc7180: Add minimal dts/dtsi files for SC7180 soc
  2019-11-07 17:46   ` Stephen Boyd
@ 2019-11-08  3:48     ` Rajendra Nayak
  2019-11-08 19:09       ` Stephen Boyd
  0 siblings, 1 reply; 40+ messages in thread
From: Rajendra Nayak @ 2019-11-08  3:48 UTC (permalink / raw)
  To: Stephen Boyd, agross, bjorn.andersson, robh+dt
  Cc: linux-arm-msm, devicetree, linux-kernel, mka, Taniya Das



On 11/7/2019 11:16 PM, Stephen Boyd wrote:
> Quoting Rajendra Nayak (2019-11-05 22:50:05)
>> diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
>> new file mode 100644
>> index 000000000000..17870dd67390
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
>> @@ -0,0 +1,299 @@
>> +// SPDX-License-Identifier: BSD-3-Clause
>> +/*
>> + * SC7180 SoC device tree source
>> + *
>> + * Copyright (c) 2019, The Linux Foundation. All rights reserved.
>> + */
>> +
>> +#include <dt-bindings/clock/qcom,gcc-sc7180.h>
>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>> +
>> +/ {
>> +       interrupt-parent = <&intc>;
>> +
>> +       #address-cells = <2>;
>> +       #size-cells = <2>;
>> +
>> +       chosen { };
>> +
>> +       clocks {
>> +               xo_board: xo-board {
>> +                       compatible = "fixed-clock";
>> +                       clock-frequency = <38400000>;
>> +                       #clock-cells = <0>;
>> +               };
>> +
>> +               sleep_clk: sleep-clk {
>> +                       compatible = "fixed-clock";
>> +                       clock-frequency = <32764>;
>> +                       clock-output-names = "sleep_clk";
> 
> Remove this one too?

ah, yes. Not sure how I missed that :/

> 
>> +                       #clock-cells = <0>;
>> +               };
>> +       };
>> +
> [...]
>> +       memory@80000000 {
>> +               device_type = "memory";
>> +               /* We expect the bootloader to fill in the size */
>> +               reg = <0 0x80000000 0 0>;
>> +       };
>> +
>> +       pmu {
>> +               compatible = "arm,armv8-pmuv3";
>> +               interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
>> +       };
>> +
>> +       psci {
>> +               compatible = "arm,psci-1.0";
>> +               method = "smc";
>> +       };
>> +
>> +       soc: soc {
>> +               #address-cells = <2>;
>> +               #size-cells = <2>;
>> +               ranges = <0 0 0 0 0x10 0>;
>> +               dma-ranges = <0 0 0 0 0x10 0>;
>> +               compatible = "simple-bus";
>> +
>> +               gcc: clock-controller@100000 {
>> +                       compatible = "qcom,gcc-sc7180";
>> +                       reg = <0 0x00100000 0 0x1f0000>;
>> +                       #clock-cells = <1>;
>> +                       #reset-cells = <1>;
>> +                       #power-domain-cells = <1>;
>> +               };
>> +
>> +               qupv3_id_1: geniqup@ac0000 {
>> +                       compatible = "qcom,geni-se-qup";
>> +                       reg = <0 0x00ac0000 0 0x6000>;
>> +                       clock-names = "m-ahb", "s-ahb";
>> +                       clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
>> +                                <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
>> +                       #address-cells = <2>;
>> +                       #size-cells = <2>;
>> +                       ranges;
>> +                       status = "disabled";
>> +
>> +                       uart8: serial@a88000 {
>> +                               compatible = "qcom,geni-debug-uart";
>> +                               reg = <0 0x00a88000 0 0x4000>;
>> +                               clock-names = "se";
>> +                               clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
>> +                               pinctrl-names = "default";
>> +                               pinctrl-0 = <&qup_uart8_default>;
>> +                               interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
>> +                               status = "disabled";
>> +                       };
>> +               };
>> +
>> +               tlmm: pinctrl@3500000 {
>> +                       compatible = "qcom,sc7180-pinctrl";
>> +                       reg = <0 0x03500000 0 0x300000>,
>> +                             <0 0x03900000 0 0x300000>,
>> +                             <0 0x03d00000 0 0x300000>;
>> +                       reg-names = "west", "north", "south";
>> +                       interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
>> +                       gpio-controller;
>> +                       #gpio-cells = <2>;
>> +                       interrupt-controller;
>> +                       #interrupt-cells = <2>;
>> +                       gpio-ranges = <&tlmm 0 0 120>;
>> +
>> +                       qup_uart8_default: qup-uart8-default {
>> +                               pinmux {
>> +                                       pins = "gpio44", "gpio45";
>> +                                       function = "qup12";
> 
> That looks weird to have qup12 function on uart8. It's right?

So we have 2 qup instances each with 6 SEs on sc7180.
So the i2c/uart/spi SE instances are numbered from 0 to 5 in the first qup
and 6 to 11 in the next.
The pinctrl functions however have it named qup0 to 5 for first and
qup10 to 15 for the next which is weird. Now all data in the pinctrl
driver is autogenerated using hw description so its coming from that.

Just for comparison, on sdm845 we had 2 qup instances with 8 SE's
and the function names were qup0 to 8 for first and 9 to 15 for the
second.

-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

^ permalink raw reply	[flat|nested] 40+ messages in thread

* Re: [PATCH v4 06/14] arm64: dts: qcom: sc7180: Add rpmh-rsc node
  2019-11-07 17:53   ` Stephen Boyd
@ 2019-11-08  3:50     ` Rajendra Nayak
  0 siblings, 0 replies; 40+ messages in thread
From: Rajendra Nayak @ 2019-11-08  3:50 UTC (permalink / raw)
  To: Stephen Boyd, agross, bjorn.andersson, robh+dt
  Cc: linux-arm-msm, devicetree, linux-kernel, mka, Maulik Shah



On 11/7/2019 11:23 PM, Stephen Boyd wrote:
> Quoting Rajendra Nayak (2019-11-05 22:50:09)
>> diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
>> index 61250560c7ef..98c8ab7d613c 100644
>> --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
>> @@ -387,6 +388,24 @@
>>                                  status = "disabled";
>>                          };
>>                  };
>> +
>> +               apps_rsc: rsc@18200000 {
> 
> The node name is non-standard. This has been a problem since sdm845
> though so it would be nice if we can invent some new name for this that
> is standard at some point in the future.
> 
>> +                       label = "apps_rsc";
> 
> Can we remove this property? The value seems minimal given that we can
> use the dev_name() and get the address in there instead of using a label.

Sure, i'll remove it.

-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

^ permalink raw reply	[flat|nested] 40+ messages in thread

* Re: [PATCH v4 14/14] arm64: dts: sc7180: Add qupv3_0 and qupv3_1
  2019-11-07 18:52   ` Stephen Boyd
@ 2019-11-08  3:52     ` Rajendra Nayak
  0 siblings, 0 replies; 40+ messages in thread
From: Rajendra Nayak @ 2019-11-08  3:52 UTC (permalink / raw)
  To: Stephen Boyd, agross, bjorn.andersson, robh+dt
  Cc: linux-arm-msm, devicetree, linux-kernel, mka, Roja Rani Yarubandi



On 11/8/2019 12:22 AM, Stephen Boyd wrote:
> Quoting Rajendra Nayak (2019-11-05 22:50:17)
>> From: Roja Rani Yarubandi <rojay@codeaurora.org>
>>
>> Add QUP SE instances configuration for sc7180.
>>
>> Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org>
>> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
>> ---
> 
> Reviewed-by: Stephen Boyd <swboyd@chromium.org>
> 
> It has the weird qup numbering too, but I guess it's correct somehow.

I responded to PATCH 2/14 as to why its weird.

-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

^ permalink raw reply	[flat|nested] 40+ messages in thread

* Re: [PATCH v4 02/14] arm64: dts: sc7180: Add minimal dts/dtsi files for SC7180 soc
  2019-11-08  3:48     ` Rajendra Nayak
@ 2019-11-08 19:09       ` Stephen Boyd
  0 siblings, 0 replies; 40+ messages in thread
From: Stephen Boyd @ 2019-11-08 19:09 UTC (permalink / raw)
  To: Rajendra Nayak, agross, bjorn.andersson, robh+dt
  Cc: linux-arm-msm, devicetree, linux-kernel, mka, Taniya Das

Quoting Rajendra Nayak (2019-11-07 19:48:57)
> 
> On 11/7/2019 11:16 PM, Stephen Boyd wrote:
> > Quoting Rajendra Nayak (2019-11-05 22:50:05)
> >> +                       qup_uart8_default: qup-uart8-default {
> >> +                               pinmux {
> >> +                                       pins = "gpio44", "gpio45";
> >> +                                       function = "qup12";
> > 
> > That looks weird to have qup12 function on uart8. It's right?
> 
> So we have 2 qup instances each with 6 SEs on sc7180.
> So the i2c/uart/spi SE instances are numbered from 0 to 5 in the first qup
> and 6 to 11 in the next.
> The pinctrl functions however have it named qup0 to 5 for first and
> qup10 to 15 for the next which is weird. Now all data in the pinctrl
> driver is autogenerated using hw description so its coming from that.
> 
> Just for comparison, on sdm845 we had 2 qup instances with 8 SE's
> and the function names were qup0 to 8 for first and 9 to 15 for the
> second.
> 

Alright. Good to know the hardware description is all messed up.


^ permalink raw reply	[flat|nested] 40+ messages in thread

* Re: [PATCH v4 08/14] dt-bindings: qcom,pdc: Add compatible for sc7180
  2019-11-07  5:46     ` Rajendra Nayak
@ 2019-11-08 23:46       ` Rob Herring
  0 siblings, 0 replies; 40+ messages in thread
From: Rob Herring @ 2019-11-08 23:46 UTC (permalink / raw)
  To: Rajendra Nayak
  Cc: Andy Gross, Bjorn Andersson, linux-arm-msm, devicetree,
	linux-kernel, Matthias Kaehlcke, Stephen Boyd, Lina Iyer,
	Marc Zyngier

On Wed, Nov 6, 2019 at 11:46 PM Rajendra Nayak <rnayak@codeaurora.org> wrote:
>
>
>
> On 11/6/2019 10:26 PM, Rob Herring wrote:
> > On Wed,  6 Nov 2019 12:20:11 +0530, Rajendra Nayak wrote:
> >> Add the compatible string for sc7180 SoC from Qualcomm.
> >>
> >> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
> >> Cc: Lina Iyer <ilina@codeaurora.org>
> >> Cc: Marc Zyngier <maz@kernel.org>
> >> ---
> >>   .../devicetree/bindings/interrupt-controller/qcom,pdc.txt      | 3 ++-
> >>   1 file changed, 2 insertions(+), 1 deletion(-)
> >>
> >
> > Please add Acked-by/Reviewed-by tags when posting new versions. However,
> > there's no need to repost patches *only* to add the tags. The upstream
> > maintainer will do that for acks received on the version they apply.
> >
> > If a tag was not added on purpose, please state why and what changed.
>
> Sorry I missed mentioning the delta and the reason for not including your Acked-by.
> The previous patch was proposing using just a SoC specific compatible, and this
> one adds a SoC independent one along with the SoC specific one as discussed here [1]

Okay.

Reviewed-by: Rob Herring <robh@kernel.org>

^ permalink raw reply	[flat|nested] 40+ messages in thread

end of thread, back to index

Thread overview: 40+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-11-06  6:50 [PATCH v4 00/14] Add device tree support for sc7180 Rajendra Nayak
2019-11-06  6:50 ` [PATCH v4 01/14] dt-bindings: qcom: Add SC7180 bindings Rajendra Nayak
2019-11-07  0:48   ` Rob Herring
2019-11-07 17:43   ` Stephen Boyd
2019-11-08  3:02     ` Rajendra Nayak
2019-11-06  6:50 ` [PATCH v4 02/14] arm64: dts: sc7180: Add minimal dts/dtsi files for SC7180 soc Rajendra Nayak
2019-11-07 17:46   ` Stephen Boyd
2019-11-08  3:48     ` Rajendra Nayak
2019-11-08 19:09       ` Stephen Boyd
2019-11-06  6:50 ` [PATCH v4 03/14] dt-bindings: arm-smmu: update binding for qcom sc7180 SoC Rajendra Nayak
2019-11-07  0:49   ` Rob Herring
2019-11-07 17:47   ` Stephen Boyd
2019-11-06  6:50 ` [PATCH v4 04/14] arm64: dts: sc7180: Add device node for apps_smmu Rajendra Nayak
2019-11-07 17:47   ` Stephen Boyd
2019-11-06  6:50 ` [PATCH v4 05/14] arm64: dts: qcom: sc7180: Add cmd_db reserved area Rajendra Nayak
2019-11-07 17:47   ` Stephen Boyd
2019-11-06  6:50 ` [PATCH v4 06/14] arm64: dts: qcom: sc7180: Add rpmh-rsc node Rajendra Nayak
2019-11-07 17:53   ` Stephen Boyd
2019-11-08  3:50     ` Rajendra Nayak
2019-11-07 17:53   ` Stephen Boyd
2019-11-06  6:50 ` [PATCH v4 07/14] drivers: irqchip: qcom-pdc: Move to an SoC independent compatible Rajendra Nayak
2019-11-06 18:20   ` Lina Iyer
2019-11-06 19:10   ` Stephen Boyd
2019-11-06  6:50 ` [PATCH v4 08/14] dt-bindings: qcom,pdc: Add compatible for sc7180 Rajendra Nayak
2019-11-06 16:56   ` Rob Herring
2019-11-07  5:46     ` Rajendra Nayak
2019-11-08 23:46       ` Rob Herring
2019-11-06 19:11   ` Stephen Boyd
2019-11-06  6:50 ` [PATCH v4 09/14] arm64: dts: qcom: sc7180: Add pdc interrupt controller Rajendra Nayak
2019-11-06 19:11   ` Stephen Boyd
2019-11-06  6:50 ` [PATCH v4 10/14] arm64: dts: qcom: sc7180: Add SPMI PMIC arbiter device Rajendra Nayak
2019-11-07 17:54   ` Stephen Boyd
2019-11-06  6:50 ` [PATCH v4 11/14] arm64: dts: qcom: pm6150: Add PM6150/PM6150L PMIC peripherals Rajendra Nayak
2019-11-07 17:59   ` Stephen Boyd
2019-11-06  6:50 ` [PATCH v4 12/14] arm64: dts: qcom: sc7180-idp: Add RPMh regulators Rajendra Nayak
2019-11-06  6:50 ` [PATCH v4 13/14] arm64: dts: qcom: SC7180: Add node for rpmhcc clock driver Rajendra Nayak
2019-11-07 18:50   ` Stephen Boyd
2019-11-06  6:50 ` [PATCH v4 14/14] arm64: dts: sc7180: Add qupv3_0 and qupv3_1 Rajendra Nayak
2019-11-07 18:52   ` Stephen Boyd
2019-11-08  3:52     ` Rajendra Nayak

LKML Archive on lore.kernel.org

Archives are clonable:
	git clone --mirror https://lore.kernel.org/lkml/0 lkml/git/0.git
	git clone --mirror https://lore.kernel.org/lkml/1 lkml/git/1.git
	git clone --mirror https://lore.kernel.org/lkml/2 lkml/git/2.git
	git clone --mirror https://lore.kernel.org/lkml/3 lkml/git/3.git
	git clone --mirror https://lore.kernel.org/lkml/4 lkml/git/4.git
	git clone --mirror https://lore.kernel.org/lkml/5 lkml/git/5.git
	git clone --mirror https://lore.kernel.org/lkml/6 lkml/git/6.git
	git clone --mirror https://lore.kernel.org/lkml/7 lkml/git/7.git

	# If you have public-inbox 1.1+ installed, you may
	# initialize and index your mirror using the following commands:
	public-inbox-init -V2 lkml lkml/ https://lore.kernel.org/lkml \
		linux-kernel@vger.kernel.org
	public-inbox-index lkml

Example config snippet for mirrors

Newsgroup available over NNTP:
	nntp://nntp.lore.kernel.org/org.kernel.vger.linux-kernel


AGPL code for this site: git clone https://public-inbox.org/public-inbox.git