From: Rob Herring <robh@kernel.org>
To: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
Cc: PCI <linux-pci@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
Bjorn Helgaas <bhelgaas@google.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Marc Zyngier <maz@kernel.org>
Subject: Re: [PATCH v9 2/2] PCI: xilinx-cpm: Add Versal CPM Root Port driver
Date: Fri, 10 Jul 2020 09:16:57 -0600 [thread overview]
Message-ID: <CAL_JsqJ0WARicxaATS_1h2W2MyXqZ8OGOxOTvWWB+hD70ea_MQ@mail.gmail.com> (raw)
In-Reply-To: <1592312214-9347-3-git-send-email-bharat.kumar.gogada@xilinx.com>
On Tue, Jun 16, 2020 at 6:57 AM Bharat Kumar Gogada
<bharat.kumar.gogada@xilinx.com> wrote:
>
> - Add support for Versal CPM as Root Port.
> - The Versal ACAP devices include CCIX-PCIe Module (CPM). The integrated
> block for CPM along with the integrated bridge can function
> as PCIe Root Port.
> - Bridge error and legacy interrupts in Versal CPM are handled using
> Versal CPM specific interrupt line.
>
> Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
> ---
> drivers/pci/controller/Kconfig | 8 +
> drivers/pci/controller/Makefile | 1 +
> drivers/pci/controller/pcie-xilinx-cpm.c | 617 +++++++++++++++++++++++++++++++
> 3 files changed, 626 insertions(+)
> create mode 100644 drivers/pci/controller/pcie-xilinx-cpm.c
[...]
> +static int xilinx_cpm_pcie_probe(struct platform_device *pdev)
> +{
> + struct xilinx_cpm_pcie_port *port;
> + struct device *dev = &pdev->dev;
> + struct pci_host_bridge *bridge;
> + struct resource *bus_range;
> + int err;
> +
> + bridge = devm_pci_alloc_host_bridge(dev, sizeof(*port));
> + if (!bridge)
> + return -ENODEV;
> +
> + port = pci_host_bridge_priv(bridge);
> +
> + port->dev = dev;
> +
> + err = pci_parse_request_of_pci_ranges(dev, &bridge->windows,
> + &bridge->dma_ranges, &bus_range);
> + if (err) {
> + dev_err(dev, "Getting bridge resources failed\n");
> + return err;
> + }
> +
> + err = xilinx_cpm_pcie_init_irq_domain(port);
> + if (err)
> + return err;
> +
> + err = xilinx_cpm_pcie_parse_dt(port, bus_range);
> + if (err) {
> + dev_err(dev, "Parsing DT failed\n");
> + goto err_parse_dt;
> + }
> +
> + xilinx_cpm_pcie_init_port(port);
> +
> + err = xilinx_cpm_setup_irq(port);
> + if (err) {
> + dev_err(dev, "Failed to set up interrupts\n");
> + goto err_setup_irq;
> + }
All the h/w init here can be moved to an .init() function in ecam ops
and then use pci_host_common_probe. Given this is v9, that can be a
follow-up I guess.
Otherwise,
Reviewed-by: Rob Herring <robh@kernel.org>
> +
> + bridge->dev.parent = dev;
> + bridge->sysdata = port->cfg;
> + bridge->busnr = port->cfg->busr.start;
> + bridge->ops = &pci_generic_ecam_ops.pci_ops;
> + bridge->map_irq = of_irq_parse_and_map_pci;
> + bridge->swizzle_irq = pci_common_swizzle;
> +
> + err = pci_host_probe(bridge);
> + if (err < 0)
> + goto err_host_bridge;
> +
> + return 0;
> +
> +err_host_bridge:
> + xilinx_cpm_free_interrupts(port);
> +err_setup_irq:
> + pci_ecam_free(port->cfg);
> +err_parse_dt:
> + xilinx_cpm_free_irq_domains(port);
> + return err;
> +}
next prev parent reply other threads:[~2020-07-10 15:20 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-16 12:56 [PATCH v9 0/2] Adding support for Versal CPM as Root Port driver Bharat Kumar Gogada
2020-06-16 12:56 ` [PATCH v9 1/2] PCI: xilinx-cpm: Add YAML schemas for Versal CPM Root Port Bharat Kumar Gogada
2020-07-10 15:04 ` Rob Herring
2020-06-16 12:56 ` [PATCH v9 2/2] PCI: xilinx-cpm: Add Versal CPM Root Port driver Bharat Kumar Gogada
2020-06-25 11:47 ` Bharat Kumar Gogada
2020-07-10 15:16 ` Rob Herring [this message]
2020-07-13 11:26 ` Lorenzo Pieralisi
2020-07-13 12:24 ` Bharat Kumar Gogada
2020-07-14 14:17 ` Rob Herring
2020-08-05 20:43 ` Bjorn Helgaas
2020-08-05 21:39 ` Lorenzo Pieralisi
2020-08-05 22:03 ` Bjorn Helgaas
2020-08-05 23:30 ` Bjorn Helgaas
2020-08-06 9:54 ` Lorenzo Pieralisi
2020-08-06 13:13 ` Bjorn Helgaas
2020-07-13 13:56 ` [PATCH v9 0/2] Adding support for Versal CPM as " Lorenzo Pieralisi
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