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From: Rob Herring <robh@kernel.org>
To: Anup Patel <anup@brainfault.org>
Cc: Anup Patel <anup.patel@wdc.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Palmer Dabbelt <palmerdabbelt@google.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Thomas Gleixner <tglx@linutronix.de>,
	Marc Zyngier <maz@kernel.org>,
	Daniel Lezcano <daniel.lezcano@linaro.org>,
	Atish Patra <atish.patra@wdc.com>,
	Alistair Francis <Alistair.Francis@wdc.com>,
	linux-riscv <linux-riscv@lists.infradead.org>,
	"linux-kernel@vger.kernel.org List"
	<linux-kernel@vger.kernel.org>, DTML <devicetree@vger.kernel.org>
Subject: Re: [RFC PATCH v3 06/11] dt-bindings: timer: Update SiFive CLINT bindings for IPI support
Date: Wed, 1 Sep 2021 19:18:32 -0500	[thread overview]
Message-ID: <CAL_JsqJ_Uc5UqCFojUYioXYJycbcBCF-nGryJiTMkhkN5MJhpw@mail.gmail.com> (raw)
In-Reply-To: <CAAhSdy2e8bPXkTodpbtNeEVX-iCxVeyNLYBkL0aCQBZ7wbSCzw@mail.gmail.com>

On Wed, Sep 1, 2021 at 7:00 AM Anup Patel <anup@brainfault.org> wrote:
>
> On Wed, Sep 1, 2021 at 6:59 AM Rob Herring <robh@kernel.org> wrote:
> >
> > On Mon, Aug 30, 2021 at 09:47:24AM +0530, Anup Patel wrote:
> > > The Linux RISC-V now treats IPIs as regular per-CPU IRQs. This means
> > > we have to create a IPI interrupt domain to use CLINT IPI functionality
> > > hence requiring a "interrupt-controller" and "#interrupt-cells" DT
> > > property in CLINT DT nodes.
> > >
> > > Impact of this CLINT DT bindings change only affects Linux RISC-V
> > > NoMMU kernel and has no effect of existing M-mode runtime firmwares
> > > (i.e. OpenSBI).
> >
> > It appears to me you should fix Linux to not need these 2 useless
> > properties. I say useless because #interrupt-cells being 0 is pretty
> > useless.
>
> Linux IRQCHIP framework only probes IRQCHIP DT nodes which
> have "interrupt-controller" DT property.

Right, I believe I wrote that... So what would it look like to fix
that? The simplest thing is just drop the check for
'interrupt-controller'. That's just a sanity check and we have other
ways to do that now (schemas). Do you need this early? You can always
implement your own initcall.


> The "interrupt-cells" DT property
> can be removed because as an interrupt controller SiFive CLINT
> will only provide IPIs to arch code.

The schema will disagree.

Rob

  reply	other threads:[~2021-09-02  0:18 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-08-30  4:17 [RFC PATCH v3 00/11] Linux RISC-V ACLINT Support Anup Patel
2021-08-30  4:17 ` [RFC PATCH v3 01/11] RISC-V: Clear SIP bit only when using SBI IPI operations Anup Patel
2021-08-30  4:17 ` [RFC PATCH v3 02/11] RISC-V: Treat IPIs as normal Linux IRQs Anup Patel
2021-08-30  4:17 ` [RFC PATCH v3 03/11] RISC-V: Allow marking IPIs as suitable for remote FENCEs Anup Patel
2021-08-30  4:17 ` [RFC PATCH v3 04/11] RISC-V: Use IPIs for remote TLB flush when possible Anup Patel
2021-08-30  4:17 ` [RFC PATCH v3 05/11] dt-bindings: interrupt-controller: Add ACLINT MSWI and SSWI bindings Anup Patel
2021-09-01  1:24   ` Rob Herring
2021-09-01 11:56     ` Anup Patel
2021-09-02  0:33       ` Rob Herring
2021-09-03 10:40         ` Anup Patel
2021-09-07 13:48           ` Rob Herring
2021-08-30  4:17 ` [RFC PATCH v3 06/11] dt-bindings: timer: Update SiFive CLINT bindings for IPI support Anup Patel
2021-09-01  1:29   ` Rob Herring
2021-09-01 12:00     ` Anup Patel
2021-09-02  0:18       ` Rob Herring [this message]
2021-09-02  5:37         ` Anup Patel
2021-08-30  4:17 ` [RFC PATCH v3 07/11] irqchip: Add ACLINT software interrupt driver Anup Patel
2021-08-30  4:17 ` [RFC PATCH v3 08/11] RISC-V: Select ACLINT SWI driver for virt machine Anup Patel
2021-08-30  4:17 ` [RFC PATCH v3 09/11] dt-bindings: timer: Add ACLINT MTIMER bindings Anup Patel
2021-09-01  1:31   ` Rob Herring
2021-08-30  4:17 ` [RFC PATCH v3 10/11] clocksource: clint: Add support for ACLINT MTIMER device Anup Patel
2021-08-30  4:17 ` [RFC PATCH v3 11/11] MAINTAINERS: Add entry for RISC-V ACLINT drivers Anup Patel

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