From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.1 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,MAILING_LIST_MULTI,SPF_PASS,T_DKIMWL_WL_HIGH autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 39210C46471 for ; Mon, 6 Aug 2018 15:20:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E630721A51 for ; Mon, 6 Aug 2018 15:20:13 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=kernel.org header.i=@kernel.org header.b="WSSL1c6A" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E630721A51 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732774AbeHFR3q (ORCPT ); Mon, 6 Aug 2018 13:29:46 -0400 Received: from mail.kernel.org ([198.145.29.99]:52274 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727665AbeHFR3q (ORCPT ); Mon, 6 Aug 2018 13:29:46 -0400 Received: from mail-qt0-f179.google.com (mail-qt0-f179.google.com [209.85.216.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 2A41521A52; Mon, 6 Aug 2018 15:20:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1533568811; bh=Ak2PP2n4i5ZzDY9Kr9kA5ITfUSCB1L3UoyTvkbtIuew=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=WSSL1c6AJzowRgXejPCTCDvlrnS83tQ8LlqYhC8LnMPEoW4YHO8u9Vq54gqirPWfk +5MnuB/L8buQQTou2GOXCgcIirNhJjLWLk46AxxxPUr0Pf9q1l1oyIprr3wLIfhHPb Y18pmJqbCrDQcPmpHOEXge8bdVTe1sAb7POkiJOA= Received: by mail-qt0-f179.google.com with SMTP id h4-v6so14195498qtj.7; Mon, 06 Aug 2018 08:20:11 -0700 (PDT) X-Gm-Message-State: AOUpUlHZSCctT67ra953vue4gDddP+gBNrK3h1dPe1LRrV0pxH9kIoDW xZ3nnuT/jqgmb6SMzeOqP3Imbjt2FVwzXsEhdw== X-Google-Smtp-Source: AAOMgpc2XILn0qSCBy+xGWyT97XXZOVaZrovGG2DGVwYFoWAE2v6ZGrCBQCI4BKikn4vBwV+81MfJSds1114L8Dg8LA= X-Received: by 2002:ac8:96b:: with SMTP id z40-v6mr14821088qth.362.1533568810413; Mon, 06 Aug 2018 08:20:10 -0700 (PDT) MIME-Version: 1.0 References: <20180803030237.3366-1-songjun.wu@linux.intel.com> <20180803030237.3366-3-songjun.wu@linux.intel.com> In-Reply-To: <20180803030237.3366-3-songjun.wu@linux.intel.com> From: Rob Herring Date: Mon, 6 Aug 2018 09:19:59 -0600 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v2 02/18] clk: intel: Add clock driver for Intel MIPS SoCs To: Songjun Wu Cc: hua.ma@linux.intel.com, yixin zhu , chuanhua.lei@linux.intel.com, qi-ming.wu@intel.com, Linux-MIPS , linux-clk , "open list:SERIAL DRIVERS" , devicetree@vger.kernel.org, Michael Turquette , Stephen Boyd , "linux-kernel@vger.kernel.org" , Mark Rutland Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Aug 2, 2018 at 9:03 PM Songjun Wu wrote: > > From: Yixin Zhu > > This driver provides PLL clock registration as well as various clock > branches, e.g. MUX clock, gate clock, divider clock and so on. > > PLLs that provide clock to DDR, CPU and peripherals are shown below: > > +---------+ > |--->| LCPLL3 0|--PCIe clk--> > XO | +---------+ > +-----------| > | +---------+ > | | 3|--PAE clk--> > |--->| PLL0B 2|--GSWIP clk--> > | | 1|--DDR clk-->DDR PHY clk--> > | | 0|--CPU1 clk--+ +-----+ > | +---------+ |--->0 | > | | MUX |--CPU clk--> > | +---------+ |--->1 | > | | 0|--CPU0 clk--+ +-----+ > |--->| PLLOA 1|--SSX4 clk--> > | 2|--NGI clk--> > | 3|--CBM clk--> > +---------+ > > Signed-off-by: Yixin Zhu > Signed-off-by: Songjun Wu > --- > > Changes in v2: > - Rewrite clock driver, add platform clock description details in > clock driver. > > drivers/clk/Kconfig | 1 + > drivers/clk/Makefile | 3 + > drivers/clk/intel/Kconfig | 20 ++ > drivers/clk/intel/Makefile | 7 + > drivers/clk/intel/clk-cgu-pll.c | 166 ++++++++++ > drivers/clk/intel/clk-cgu-pll.h | 34 ++ > drivers/clk/intel/clk-cgu.c | 470 +++++++++++++++++++++++++++ > drivers/clk/intel/clk-cgu.h | 259 +++++++++++++++ > drivers/clk/intel/clk-grx500.c | 168 ++++++++++ > include/dt-bindings/clock/intel,grx500-clk.h | 69 ++++ This belongs with the clk binding patch. Rob