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From: Rob Herring <robh+dt@kernel.org>
To: Aisheng Dong <aisheng.dong@nxp.com>
Cc: "Peng Fan (OSS)" <peng.fan@oss.nxp.com>,
	"sboyd@kernel.org" <sboyd@kernel.org>,
	"shawnguo@kernel.org" <shawnguo@kernel.org>,
	"s.hauer@pengutronix.de" <s.hauer@pengutronix.de>,
	"kernel@pengutronix.de" <kernel@pengutronix.de>,
	"festevam@gmail.com" <festevam@gmail.com>,
	dl-linux-imx <linux-imx@nxp.com>,
	"ulf.hansson@linaro.org" <ulf.hansson@linaro.org>,
	"adrian.hunter@intel.com" <adrian.hunter@intel.com>,
	"linux-clk@vger.kernel.org" <linux-clk@vger.kernel.org>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	"linux-arm-kernel@lists.infradead.org" 
	<linux-arm-kernel@lists.infradead.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"linux-mmc@vger.kernel.org" <linux-mmc@vger.kernel.org>,
	Peng Fan <peng.fan@nxp.com>
Subject: Re: [PATCH V3 4/5] dt-bindings: mmc: fsl-imx-esdhc: add clock bindings
Date: Fri, 5 Mar 2021 08:14:23 -0600	[thread overview]
Message-ID: <CAL_JsqKK8t6XUqTuOKPzOviJbysqWqga_mdxWE0P0N4ejTgG=A@mail.gmail.com> (raw)
In-Reply-To: <AM6PR04MB4966041BFFDDAF1EF00BE1AD80969@AM6PR04MB4966.eurprd04.prod.outlook.com>

On Fri, Mar 5, 2021 at 8:09 AM Aisheng Dong <aisheng.dong@nxp.com> wrote:
>
> Hi Rob,
>
> > From: Peng Fan (OSS) <peng.fan@oss.nxp.com>
> > Sent: Thursday, February 25, 2021 11:10 AM
> >
> > From: Peng Fan <peng.fan@nxp.com>
> >
> > Add clock bindings for fsl-imx-esdhc yaml
> >
> > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > ---
> >  .../devicetree/bindings/mmc/fsl-imx-esdhc.yaml        | 11 +++++++++++
> >  1 file changed, 11 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml
> > b/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml
> > index a7fbd8cc1e38..369471814496 100644
> > --- a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml
> > +++ b/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml
> > @@ -103,6 +103,17 @@ properties:
> >        Only eMMC HS400 mode need to take care of this property.
> >      default: 0
> >
> > +  clocks:
> > +    maxItems: 3
> > +    description:
> > +      Handle clocks for the sdhc controller.
> > +
> > +  clock-names:
> > +    items:
> > +      - const: ipg
> > +      - const: ahb
> > +      - const: per
>
> One question:
> The side effect of this patch is that it imposes a forced order of clk names
> In DT which actually was not needed.
>
> Do we really have to do that?

Yes.

> Or any other better approach to allow a random order to match the DT
> usage better?

Why do you need random order?

We can not enforce the order, but we only do that when there's
multiple optional entries.

Rob

  reply	other threads:[~2021-03-05 14:15 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-02-25  3:09 [PATCH V3 0/5] imx esdhc dt/driver update peng.fan
2021-02-25  3:10 ` [PATCH V3 1/5] dt-bindings: mmc: fsl-imx-esdhc: add pinctrl bindings peng.fan
2021-02-25  3:10 ` [PATCH V3 2/5] dt-bindings: clock: imx8qxp-lpcg: correct the example clock-names peng.fan
2021-03-06 20:39   ` Rob Herring
2021-02-25  3:10 ` [PATCH V3 3/5] arm64: dts: imx8qxp: correct usdhc clock-names sequence peng.fan
2021-02-25  3:10 ` [PATCH V3 4/5] dt-bindings: mmc: fsl-imx-esdhc: add clock bindings peng.fan
2021-03-04 22:48   ` Rob Herring
2021-03-05  0:38     ` Peng Fan
2021-03-05 14:09   ` Aisheng Dong
2021-03-05 14:14     ` Rob Herring [this message]
2021-03-06  4:53       ` Aisheng Dong
2021-02-25  3:10 ` [PATCH V3 5/5] mmc: sdhci-esdhc-imx: validate pinctrl before use it peng.fan
2021-03-02 10:39 ` [PATCH V3 0/5] imx esdhc dt/driver update Ulf Hansson
2021-03-03  3:00   ` Peng Fan (OSS)
2021-03-08  0:51     ` Shawn Guo

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