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Mon, 30 Nov 2020 12:31:32 -0800 (PST) MIME-Version: 1.0 References: <1606746513-30909-1-git-send-email-kevin3.tang@gmail.com> <1606746513-30909-6-git-send-email-kevin3.tang@gmail.com> In-Reply-To: <1606746513-30909-6-git-send-email-kevin3.tang@gmail.com> From: Rob Herring Date: Mon, 30 Nov 2020 13:31:21 -0700 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH 5/6] dt-bindings: display: add Unisoc's mipi dsi&dphy bindings To: Kevin Tang Cc: Maarten Lankhorst , Maxime Ripard , Sean Paul , David Airlie , Daniel Vetter , Mark Rutland , Orson Zhai , Lyra Zhang , "linux-kernel@vger.kernel.org" , dri-devel Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Nov 30, 2020 at 7:29 AM Kevin Tang wrote: > > From: Kevin Tang > > Adds MIPI DSI Master and MIPI DSI-PHY (D-PHY) > support for Unisoc's display subsystem. > > Cc: Orson Zhai > Cc: Chunyan Zhang > Signed-off-by: Kevin Tang > --- > .../display/sprd/sprd,sharkl3-dsi-host.yaml | 107 +++++++++++++++++++++ > .../display/sprd/sprd,sharkl3-dsi-phy.yaml | 84 ++++++++++++++++ > 2 files changed, 191 insertions(+) > create mode 100644 Documentation/devicetree/bindings/display/sprd/sprd,sharkl3-dsi-host.yaml > create mode 100644 Documentation/devicetree/bindings/display/sprd/sprd,sharkl3-dsi-phy.yaml > > diff --git a/Documentation/devicetree/bindings/display/sprd/sprd,sharkl3-dsi-host.yaml b/Documentation/devicetree/bindings/display/sprd/sprd,sharkl3-dsi-host.yaml > new file mode 100644 > index 0000000..fe0e89d > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/sprd/sprd,sharkl3-dsi-host.yaml > @@ -0,0 +1,107 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/display/sprd/sprd,sharkl3-dsi-host.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Unisoc MIPI DSI Controller > + > +maintainers: > + - Kevin Tang > + > +properties: > + compatible: > + const: sprd,sharkl3-dsi-host > + > + reg: > + maxItems: 1 > + description: > + Physical base address and length of the registers set for the device. > + > + interrupts: > + maxItems: 2 > + description: > + Should contain DSI interrupt. > + > + clocks: > + minItems: 1 > + > + clock-names: > + items: > + - const: clk_src_96m > + > + power-domains: > + maxItems: 1 > + description: A phandle to DSIM power domain node > + > + ports: > + type: object > + > + properties: > + "#address-cells": > + const: 1 > + > + "#size-cells": > + const: 0 > + > + port@0: > + type: object > + description: > + A port node with endpoint definitions as defined in > + Documentation/devicetree/bindings/media/video-interfaces.txt. > + That port should be the input endpoint, usually coming from > + the associated DPU. > + port@1: > + type: object > + description: > + A port node with endpoint definitions as defined in > + Documentation/devicetree/bindings/media/video-interfaces.txt. > + That port should be the output endpoint, usually output to > + the associated DPHY. > + > + required: > + - "#address-cells" > + - "#size-cells" > + - port@0 > + - port@1 > + > + additionalProperties: false > + > +required: > + - compatible > + - reg > + - interrupts > + - clocks > + - clock-names > + - ports > + > +additionalProperties: false > + > +examples: > + - | > + #include > + #include > + dsi: dsi@63100000 { > + compatible = "sprd,sharkl3-dsi-host"; > + reg = <0x63100000 0x1000>; > + interrupts = , > + ; > + clock-names = "clk_src_96m"; > + clocks = <&pll CLK_TWPLL_96M>; > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + port@0 { > + reg = <0>; > + dsi_in: endpoint { > + remote-endpoint = <&dpu_out>; > + }; > + }; > + port@1 { > + reg = <1>; > + dsi_out: endpoint { > + remote-endpoint = <&dphy_in>; > + }; > + }; > + }; > + }; > diff --git a/Documentation/devicetree/bindings/display/sprd/sprd,sharkl3-dsi-phy.yaml b/Documentation/devicetree/bindings/display/sprd/sprd,sharkl3-dsi-phy.yaml > new file mode 100644 > index 0000000..b4715d5 > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/sprd/sprd,sharkl3-dsi-phy.yaml > @@ -0,0 +1,84 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/display/sprd/sprd,sharkl3-dsi-phy.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Unisoc MIPI DSI-PHY (D-PHY) > + > +maintainers: > + - Kevin Tang > + > +properties: > + compatible: > + const: sprd,sharkl3-dsi-phy > + > + reg: > + maxItems: 1 > + description: > + Must be the dsi controller base address. > + > + ports: > + type: object > + > + properties: > + "#address-cells": > + const: 1 > + > + "#size-cells": > + const: 0 > + > + port@0: > + type: object > + description: > + A port node with endpoint definitions as defined in > + Documentation/devicetree/bindings/media/video-interfaces.txt. > + That port should be the output endpoint, usually output to > + the associated panel. > + port@1: For PHYs, we use the PHY binding, not the graph binding. Please follow what practically every other DSI PHY does. Rob