From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751334AbbCKHAl (ORCPT ); Wed, 11 Mar 2015 03:00:41 -0400 Received: from mail-lb0-f180.google.com ([209.85.217.180]:40524 "EHLO mail-lb0-f180.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750851AbbCKHAi (ORCPT ); Wed, 11 Mar 2015 03:00:38 -0400 MIME-Version: 1.0 In-Reply-To: <20150310075543.GB24885@pengutronix.de> References: <1425466152-7867-1-git-send-email-pi-cheng.chen@linaro.org> <20150304112109.GB11010@pengutronix.de> <20150305074207.GC11010@pengutronix.de> <20150310075543.GB24885@pengutronix.de> Date: Wed, 11 Mar 2015 15:00:36 +0800 Message-ID: Subject: Re: [PATCH] clk: mediatek: Export CPU mux clocks for CPU frequency control From: Pi-Cheng Chen To: Sascha Hauer Cc: Mike Turquette , Stephen Boyd , Matthias Brugger , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Henry Chen , James Liao , Chen Fan , Eddie Huang , "Joe.C" , Linux Kernel Mailing List , "linux-arm-kernel@lists.infradead.org" , "devicetree@vger.kernel.org" , Linaro Kernel Mailman List , linux-mediatek@lists.infradead.org, Viresh Kumar Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Mar 10, 2015 at 3:55 PM, Sascha Hauer wrote: > On Tue, Mar 10, 2015 at 09:53:19AM +0800, Pi-Cheng Chen wrote: >> On 5 March 2015 at 15:42, Sascha Hauer wrote: >> > >> > My suggestion is to take another approach. Implement clk_set_rate for >> > these muxes and in the set_rate hook: >> > >> > - switch mux to intermediate PLL parent >> > - call clk_set_rate() for the real parent PLL >> > - switch mux back to real parent PLL >> >> Hi Sascha, >> >> Thanks for your suggestion. I've tried to take this approach, but there's some >> issues here. >> >> Calling clk_set_rate() inside the set_rate callback of cpumux will cause >> an infinite recursive calling in the clock framework: >> mux.set_rate() -> pll.set_rate() -> mux.set_rate -> ... > > I don't understand why setting the PLL rate should call into the mux > set_rate. Are you sure you call clk_set_rate for the mux parent clk? > I think the general approach should work, drivers/clk/sirf/clk-common.c > does something similar in cpu_clk_set_rate(). If you like you can send > me your work in progress state privatly, I'll have a look then. Thanks for pointing me out the reference. I think I misunderstood the way you suggested to do it. I'll post the new version once the design including cpufreq part is finalized. Best Regards, Pi-Cheng > >> >> I've also tries to update pll register settings in the set_rate() >> callback of cpumux, >> but the PLL clock information will not be correctly updated in this case. > > No, that won't work. > > Sascha > > > -- > Pengutronix e.K. | | > Industrial Linux Solutions | http://www.pengutronix.de/ | > Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | > Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |