Re: [PATCH 2/9] perf tools: Support the auxiliary event

[Namhyung Kim <namhyung@kernel.org>]

On Wed, Feb 3, 2021 at 5:14 AM <kan.liang@linux.intel.com> wrote:
>
> From: Kan Liang <kan.liang@linux.intel.com>
>
> On the Intel Sapphire Rapids server, an auxiliary event has to be
> enabled simultaneously with the load latency event to retrieve complete
> Memory Info.
>
> Add X86 specific perf_mem_events__name() to handle the auxiliary event.
> - Users are only interested in the samples of the mem-loads event.
>   Sample read the auxiliary event.
> - The auxiliary event must be in front of the load latency event in a
>   group. Assume the second event to sample if the auxiliary event is the
>   leader.
> - Add a weak is_mem_loads_aux_event() to check the auxiliary event for
>   X86. For other ARCHs, it always return false.
>
> Parse the unique event name, mem-loads-aux, for the auxiliary event.
>
> Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
> ---
>  tools/perf/arch/x86/util/Build        |  1 +
>  tools/perf/arch/x86/util/mem-events.c | 44 +++++++++++++++++++++++++++++++++++
>  tools/perf/util/evsel.c               |  3 +++
>  tools/perf/util/mem-events.c          |  5 ++++
>  tools/perf/util/mem-events.h          |  2 ++
>  tools/perf/util/parse-events.l        |  1 +
>  tools/perf/util/record.c              |  5 +++-
>  7 files changed, 60 insertions(+), 1 deletion(-)
>  create mode 100644 tools/perf/arch/x86/util/mem-events.c
>
> diff --git a/tools/perf/arch/x86/util/Build b/tools/perf/arch/x86/util/Build
> index 347c39b..d73f548 100644
> --- a/tools/perf/arch/x86/util/Build
> +++ b/tools/perf/arch/x86/util/Build
> @@ -6,6 +6,7 @@ perf-y += perf_regs.o
>  perf-y += topdown.o
>  perf-y += machine.o
>  perf-y += event.o
> +perf-y += mem-events.o
>
>  perf-$(CONFIG_DWARF) += dwarf-regs.o
>  perf-$(CONFIG_BPF_PROLOGUE) += dwarf-regs.o
> diff --git a/tools/perf/arch/x86/util/mem-events.c b/tools/perf/arch/x86/util/mem-events.c
> new file mode 100644
> index 0000000..11b8469
> --- /dev/null
> +++ b/tools/perf/arch/x86/util/mem-events.c
> @@ -0,0 +1,44 @@
> +// SPDX-License-Identifier: GPL-2.0
> +#include "util/pmu.h"
> +#include "map_symbol.h"
> +#include "mem-events.h"
> +
> +static char mem_loads_name[100];
> +static bool mem_loads_name__init;
> +
> +#define MEM_LOADS_AUX          0x8203
> +#define MEM_LOADS_AUX_NAME     "{cpu/mem-loads-aux/,cpu/mem-loads,ldlat=%u/pp}:S"
> +
> +bool is_mem_loads_aux_event(struct evsel *leader)
> +{
> +       if (!pmu_have_event("cpu", "mem-loads-aux"))
> +               return false;
> +
> +       return leader->core.attr.config == MEM_LOADS_AUX;
> +}
> +
> +char *perf_mem_events__name(int i)
> +{
> +       struct perf_mem_event *e = perf_mem_events__ptr(i);
> +
> +       if (!e)
> +               return NULL;
> +
> +       if (i == PERF_MEM_EVENTS__LOAD) {
> +               if (mem_loads_name__init)
> +                       return mem_loads_name;
> +
> +               mem_loads_name__init = true;
> +
> +               if (pmu_have_event("cpu", "mem-loads-aux")) {
> +                       scnprintf(mem_loads_name, sizeof(MEM_LOADS_AUX_NAME),
> +                                 MEM_LOADS_AUX_NAME, perf_mem_events__loads_ldlat);

It changes "%u" to an actual latency value, right?
What if the value takes 3 or more digits?
I'm not sure scnprintf() will handle it properly.

Thanks,
Namhyung


> +               } else {
> +                       scnprintf(mem_loads_name, sizeof(mem_loads_name),
> +                                 e->name, perf_mem_events__loads_ldlat);
> +               }
> +               return mem_loads_name;
> +       }
> +
> +       return (char *)e->name;
> +}