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d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=9cyiA6wKj6aYc3HuGyRHU8Zz2WjjnKWj3tYvNZGV3VE=; b=TebE2FEbRqrapVY+HWxB2FnCUMpWVSA6DuTtuIs7uL1OEjstrp4Jn84DL5KVBCtu/h Q3X4bTzXGehX06jc21dsdTCzZDeci2mKlvtRmBx+c9QU1bsu8mSBZaMF8NSHDQ5qRqk9 czDTk7/Z/XcOzcjwxGnRzgwLdHgyat3xDeTuyHlQ5wz3pAN0XOShreE+YM1r+FswakQ3 GvzZAogEAwVT2NNdS2WZqc3nhDlu/T9PHwUKzAVkDFbSdXWUa/N/G/6gApc7vyH77KfA /8iQXuvuXd6Q+b/mpcB8nMqgGF5EyqwmemRyLrq7uuARnEYLI4heVFAnPkWY0zjQMbzN 6jAg== X-Gm-Message-State: AOAM533GZs1CCza/GxBgS5wfJ+tYlBXKTe1CSA6W+ZJiGrX6y8/Z0Rfd 02OEgGPOXZjUhRELh9yftIGbEy+UTDuUu+D98kfhxWmQTozDxw== X-Google-Smtp-Source: ABdhPJwp9HmT51Y/FoZx4UCv7YAz4y8OSSWO0aA59p1yqoD6CosC0wGNI5oxSR44LWQv6OrMas5DMQlXX5Qwh6+3nTs= X-Received: by 2002:a4a:d247:: with SMTP id e7mr9500271oos.77.1622636197909; Wed, 02 Jun 2021 05:16:37 -0700 (PDT) MIME-Version: 1.0 References: <20210515124055.22225-1-sergio.paracuellos@gmail.com> <20210515124055.22225-3-sergio.paracuellos@gmail.com> <20210531131431.bzsvmefqdyawmeo2@pali> <20210531135041.42ovpmbwuc3yfkaw@pali> In-Reply-To: From: Sergio Paracuellos Date: Wed, 2 Jun 2021 14:16:26 +0200 Message-ID: Subject: Re: [PATCH 2/4] MIPS: pci: Add driver for MT7621 PCIe controller To: =?UTF-8?Q?Pali_Roh=C3=A1r?= Cc: "open list:MIPS" , Thomas Bogendoerfer , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , Matthias Brugger , John Crispin , Bjorn Helgaas , Rob Herring , linux-staging@lists.linux.dev, Greg KH , NeilBrown , Ilya Lipnitskiy , linux-kernel , linux-pci@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Pali, On Mon, May 31, 2021 at 4:19 PM Sergio Paracuellos wrote: > > On Mon, May 31, 2021 at 3:50 PM Pali Roh=C3=A1r wrote: > > > > On Monday 31 May 2021 15:39:55 Sergio Paracuellos wrote: > > > Hi Pali, > > > > > > Thanks for your comments. > > > > > > On Mon, May 31, 2021 at 3:14 PM Pali Roh=C3=A1r wro= te: > > > > > > > > On Saturday 15 May 2021 14:40:53 Sergio Paracuellos wrote: > > > > > This patch adds a driver for the PCIe controller of MT7621 SoC. > > > > > > > > > > Signed-off-by: Sergio Paracuellos > > > > > --- > > > > > arch/mips/pci/Makefile | 1 + > > > > > arch/mips/pci/pci-mt7621.c | 624 +++++++++++++++++++++++++++++++= ++++++ > > > > > arch/mips/ralink/Kconfig | 9 +- > > > > > 3 files changed, 633 insertions(+), 1 deletion(-) > > > > > create mode 100644 arch/mips/pci/pci-mt7621.c > > > > > > > > > > diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile > > > > > index f3eecc065e5c..178c550739c4 100644 > > > > > --- a/arch/mips/pci/Makefile > > > > > +++ b/arch/mips/pci/Makefile > > > > > @@ -24,6 +24,7 @@ obj-$(CONFIG_PCI_AR2315) +=3D pci-ar2315.o > > > > > obj-$(CONFIG_SOC_AR71XX) +=3D pci-ar71xx.o > > > > > obj-$(CONFIG_PCI_AR724X) +=3D pci-ar724x.o > > > > > obj-$(CONFIG_PCI_XTALK_BRIDGE) +=3D pci-xtalk-bridge.o > > > > > +obj-$(CONFIG_PCI_MT7621) +=3D pci-mt7621.o > > > > > # > > > > > # These are still pretty much in the old state, watch, go blind. > > > > > # > > > > > diff --git a/arch/mips/pci/pci-mt7621.c b/arch/mips/pci/pci-mt762= 1.c > > > > > new file mode 100644 > > > > > index 000000000000..fe1945819d25 > > > > > --- /dev/null > > > > > +++ b/arch/mips/pci/pci-mt7621.c > > > > ... > > > > > +static int mt7621_pcie_enable_ports(struct mt7621_pcie *pcie) > > > > > +{ > > > > > + struct device *dev =3D pcie->dev; > > > > > + struct mt7621_pcie_port *port; > > > > > + u8 num_slots_enabled =3D 0; > > > > > + u32 slot; > > > > > + u32 val; > > > > > + int err; > > > > > + > > > > > + /* Setup MEMWIN and IOWIN */ > > > > > + pcie_write(pcie, 0xffffffff, RALINK_PCI_MEMBASE); > > > > > + pcie_write(pcie, pcie->io.start, RALINK_PCI_IOBASE); > > > > > + > > > > > + list_for_each_entry(port, &pcie->ports, list) { > > > > > + if (port->enabled) { > > > > > + err =3D clk_prepare_enable(port->clk); > > > > > + if (err) { > > > > > + dev_err(dev, "enabling clk pcie%d\n= ", slot); > > > > > + return err; > > > > > + } > > > > > + > > > > > + mt7621_pcie_enable_port(port); > > > > > + dev_info(dev, "PCIE%d enabled\n", port->slo= t); > > > > > + num_slots_enabled++; > > > > > + } > > > > > + } > > > > > + > > > > > + for (slot =3D 0; slot < num_slots_enabled; slot++) { > > > > > + val =3D read_config(pcie, slot, PCI_COMMAND); > > > > > + val |=3D PCI_COMMAND_MASTER; > > > > > + write_config(pcie, slot, PCI_COMMAND, val); > > > > > > > > Hello! Is this part of code correct? Because it looks strange if PC= Ie > > > > controller driver automatically enables PCI bus mastering, prior de= vice > > > > driver initialize itself. > > > > > > > > Moreover kernel has already function pci_set_master() for this purp= ose > > > > which is used by device drivers. > > > > > > > > So I think this code can confuse some device drivers... > > > > > > I agree that we have pci_set_master() to be used in pci device driver > > > code. Original controller driver set this bit for enabled slots. Sinc= e > > > there is no documentation at all for the PCI in this SoC > > > > I see... this is really a big problem to do any driver development... > > For sure it is :(. > > > > > > I have > > > maintained the setting in the driver in a cleaner way. See original > > > driver code and the setting here [0]. There is no other reason than > > > that. I am ok with removing this from here and testing with my two > > > devices that everything is still ok if having this setting in the pci > > > controller driver is a real problem. > > > > You can run lspci -nnvv with and without PCI_COMMAND_MASTER code and > > then compare outputs. > > > > Device drivers for sure enable PCI_COMMAND_MASTER at the time when it i= s > > needed, so it is possible that there would be no difference in lspci > > output. > > Thanks. I will take this into account when v2 is submitted after more > review comments come :). I have tested to remove this and check lspci -nnvv output with and without PCI_COMMAND_MASTER code and, as you pointed out, there is no difference between them. Also, both boards are working without regressions at all. So I will remove this code for next version. Thanks, Sergio Paracuellos > > > > > > [0]: https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging.g= it/tree/drivers/staging/mt7621-pci/pci-mt7621.c?h=3Dv4.18#n676 > > > > > > Best regards, > > > Sergio Paracuellos > > > > > > > > > + /* configure RC FTS number to 250 when it leaves L0= s */ > > > > > + val =3D read_config(pcie, slot, PCIE_FTS_NUM); > > > > > + val &=3D ~PCIE_FTS_NUM_MASK; > > > > > + val |=3D PCIE_FTS_NUM_L0(0x50); > > > > > + write_config(pcie, slot, PCIE_FTS_NUM, val); > > > > > + } > > > > > + > > > > > + return 0; > > > > > +}