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* [PATCH v2 0/3] PCI: mt7621: Add MediaTek MT7621 PCIe host controller driver
@ 2021-06-09 14:01 Sergio Paracuellos
  2021-06-09 14:01 ` [PATCH v2 1/3] dt-bindings: mt7621-pci: PCIe binding documentation for MT7621 SoCs Sergio Paracuellos
                   ` (3 more replies)
  0 siblings, 4 replies; 10+ messages in thread
From: Sergio Paracuellos @ 2021-06-09 14:01 UTC (permalink / raw)
  To: linux-pci
  Cc: linux-mips, tsbogend, devicetree, matthias.bgg, john, bhelgaas,
	robh+dt, linux-staging, gregkh, neil, ilya.lipnitskiy,
	linux-kernel, pali

MediaTek MT7621 PCIe subsys supports single Root complex (RC)
with 3 Root Ports. Each Root Ports supports a Gen1 1-lane Link.
Topology is as follows:

                          MT7621 PCIe HOST Topology

                                   .-------.
                                   |       |
                                   |  CPU  |
                                   |       |
                                   '-------'
                                       |
                                       |
                                       |
                                       v
                              .------------------.
                  .-----------|  HOST/PCI Bridge |------------.
                  |           '------------------'            |     Type1 
         BUS0     |                     |                     |    Access 
                  v                     v                     v    On Bus0
          .-------------.        .-------------.       .-------------.
          | VIRTUAL P2P |        | VIRTUAL P2P |       | VIRTUAL P2P |
          |    BUS0     |        |    BUS0     |       |    BUS0     |
          |    DEV0     |        |    DEV1     |       |    DEV2     |
          '-------------'        '-------------'       '-------------'
    Type0        |          Type0       |         Type0       |
   Access   BUS1 |         Access   BUS2|        Access   BUS3|
   On Bus1       v         On Bus2      v        On Bus3      v
           .----------.           .----------.          .----------.
           | Device 0 |           | Device 0 |          | Device 0 |
           |  Func 0  |           |  Func 0  |          |  Func 0  |
           '----------'           '----------'          '----------'

This driver has been very long time in staging and I have been cleaning
it from its first versions where there was code kaos and PCI_LEGACY support.
Original code came probably from openWRT based on mediatek's SDK code. There
is no documentation at all about the mt7621 PCI subsystem.
I have been cleaning it targeting mt7621 SoC which is the one I use in
my GNUBee PC1 board and HiLink HLK-MT7621A evaluation board.

Now I think is clean enough to be moved into 'drivers/pci/controller'.
This driver is mips/ralink architecture and need 'mips_cps_numiocu()'
to properly configure iocu regions for mips.

This driver also uses already mainlined pci phy driver located in
'drivers/phy/ralink/phy-mt7621-pci.c'. There are two instances of
the phy being the first one dual ported for pci0 and pci1, and the
second one not dual ported dedicated to pci2. Because of writing twice
some phy registers of the dual-ported one sometimes become in not
confident boot cycles we have to take care of this when device link
is checked here in controller driver. We power on the dual ported-phy
if there is something connected in pcie0 or pcie1. In the same manner
we have to properly disable it only if nothing is connected in of both
pcie0 and pcie1 slots.

Another thing that must be mentioned is that this driver uses IO
in physical address 0x001e160000. IO_SPACE_LIMIT for MIPS is 0xffff
so some generic PCI functions (like of_pci_range_to_resource) won't
work and the resource ranges part for IO is set manually.

Changes in v2:
    - Make one commit moving driver directly from staging into
     'drivers/pci/controllers' instead of two commits making
     one add and a later remove.
    - Update binding documentation moving 'clocks', 'resets' and
     'phys' properties to child root bridge nodes. 
    - Update code to properly be able to use new bindings.
    - Kconfig: add || (MIPS && COMPILE_TEST).
    - Use {read/write}_relaxed versions.
    - Use 'PCI_BASE_ADDRESS_0' instead of a custom definition.
    - Avoid to set 'PCI_COMMAND_MASTER' and re-do functions
     'mt7621_pcie_enable_ports' and 'mt7621_pcie_enable_port'.

NOTE: Greg, I have maintained your Acked-by from previous series in
delete driver commit and added in the one which is moving code here
and delete the remaining stuff. If you are not ok with this, just
let me now and I'll drop it and resend.

Thanks in advance for your time.

Best regards,
    Sergio Paracuellos

Sergio Paracuellos (3):
  dt-bindings: mt7621-pci: PCIe binding documentation for MT7621 SoCs
  PCI: mt7621: Add MediaTek MT7621 PCIe host controller driver
  MAINTAINERS: add myself as maintainer of the MT7621 PCI controller
    driver

 .../bindings/pci/mediatek,mt7621-pci.yaml     | 142 ++++++++++++++++++
 MAINTAINERS                                   |   6 +
 arch/mips/ralink/Kconfig                      |   2 +-
 drivers/pci/controller/Kconfig                |   8 +
 drivers/pci/controller/Makefile               |   1 +
 .../controller}/pci-mt7621.c                  |   0
 drivers/staging/Kconfig                       |   2 -
 drivers/staging/Makefile                      |   1 -
 drivers/staging/mt7621-pci/Kconfig            |   8 -
 drivers/staging/mt7621-pci/Makefile           |   2 -
 drivers/staging/mt7621-pci/TODO               |   4 -
 .../mt7621-pci/mediatek,mt7621-pci.txt        | 104 -------------
 12 files changed, 158 insertions(+), 122 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/pci/mediatek,mt7621-pci.yaml
 rename drivers/{staging/mt7621-pci => pci/controller}/pci-mt7621.c (100%)
 delete mode 100644 drivers/staging/mt7621-pci/Kconfig
 delete mode 100644 drivers/staging/mt7621-pci/Makefile
 delete mode 100644 drivers/staging/mt7621-pci/TODO
 delete mode 100644 drivers/staging/mt7621-pci/mediatek,mt7621-pci.txt

-- 
2.25.1


^ permalink raw reply	[flat|nested] 10+ messages in thread

* [PATCH v2 1/3] dt-bindings: mt7621-pci: PCIe binding documentation for MT7621 SoCs
  2021-06-09 14:01 [PATCH v2 0/3] PCI: mt7621: Add MediaTek MT7621 PCIe host controller driver Sergio Paracuellos
@ 2021-06-09 14:01 ` Sergio Paracuellos
  2021-06-18 21:08   ` Rob Herring
  2021-06-09 14:01 ` [PATCH v2 2/3] PCI: mt7621: Add MediaTek MT7621 PCIe host controller driver Sergio Paracuellos
                   ` (2 subsequent siblings)
  3 siblings, 1 reply; 10+ messages in thread
From: Sergio Paracuellos @ 2021-06-09 14:01 UTC (permalink / raw)
  To: linux-pci
  Cc: linux-mips, tsbogend, devicetree, matthias.bgg, john, bhelgaas,
	robh+dt, linux-staging, gregkh, neil, ilya.lipnitskiy,
	linux-kernel, pali

Add device tree binding documentation for PCIe in MT7621 SoCs.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 .../bindings/pci/mediatek,mt7621-pci.yaml     | 142 ++++++++++++++++++
 1 file changed, 142 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pci/mediatek,mt7621-pci.yaml

diff --git a/Documentation/devicetree/bindings/pci/mediatek,mt7621-pci.yaml b/Documentation/devicetree/bindings/pci/mediatek,mt7621-pci.yaml
new file mode 100644
index 000000000000..716b77d6c830
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/mediatek,mt7621-pci.yaml
@@ -0,0 +1,142 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/mediatek,mt7621-pci.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek MT7621 PCIe controller
+
+maintainers:
+  - Sergio Paracuellos <sergio.paracuellos@gmail.com>
+
+description: |+
+  MediaTek MT7621 PCIe subsys supports single Root complex (RC)
+  with 3 Root Ports. Each Root Ports supports a Gen1 1-lane Link
+
+allOf:
+  - $ref: /schemas/pci/pci-bus.yaml#
+
+properties:
+  compatible:
+    const: mediatek,mt7621-pci
+
+  reg:
+    items:
+      - description: host-pci bridge registers
+      - description: pcie port 0 RC control registers
+      - description: pcie port 1 RC control registers
+      - description: pcie port 2 RC control registers
+
+  ranges:
+    maxItems: 2
+
+patternProperties:
+  'pcie@[0-2],0':
+    type: object
+    $ref: /schemas/pci/pci-bus.yaml#
+
+    properties:
+      resets:
+        maxItems: 1
+
+      clocks:
+        maxItems: 1
+
+      phys:
+        maxItems: 1
+
+    required:
+      - "#interrupt-cells"
+      - interrupt-map-mask
+      - interrupt-map
+      - resets
+      - clocks
+      - phys
+      - phy-names
+      - ranges
+
+    unevaluatedProperties: false
+
+required:
+  - compatible
+  - reg
+  - ranges
+  - "#interrupt-cells"
+  - interrupt-map-mask
+  - interrupt-map
+  - reset-gpios
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/gpio/gpio.h>
+    #include <dt-bindings/interrupt-controller/mips-gic.h>
+
+    pcie: pcie@1e140000 {
+        compatible = "mediatek,mt7621-pci";
+        reg = <0x1e140000 0x100>,
+              <0x1e142000 0x100>,
+              <0x1e143000 0x100>,
+              <0x1e144000 0x100>;
+
+        #address-cells = <3>;
+        #size-cells = <2>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pcie_pins>;
+        device_type = "pci";
+        ranges = <0x02000000 0 0x00000000 0x60000000 0 0x10000000>,  /* pci memory */
+                 <0x01000000 0 0x00000000 0x1e160000 0 0x00010000>;  /* io space */
+        #interrupt-cells = <1>;
+        interrupt-map-mask = <0xF800 0 0 0>;
+        interrupt-map = <0x0000 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>,
+                        <0x0800 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>,
+                        <0x1000 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
+        reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
+
+        pcie@0,0 {
+            reg = <0x0000 0 0 0 0>;
+            #address-cells = <3>;
+            #size-cells = <2>;
+            device_type = "pci";
+            #interrupt-cells = <1>;
+            interrupt-map-mask = <0 0 0 0>;
+            interrupt-map = <0 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>;
+            resets = <&rstctrl 24>;
+            clocks = <&clkctrl 24>;
+            phys = <&pcie0_phy 1>;
+            phy-names = "pcie-phy0";
+            ranges;
+        };
+
+        pcie@1,0 {
+            reg = <0x0800 0 0 0 0>;
+            #address-cells = <3>;
+            #size-cells = <2>;
+            device_type = "pci";
+            #interrupt-cells = <1>;
+            interrupt-map-mask = <0 0 0 0>;
+            interrupt-map = <0 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>;
+            resets = <&rstctrl 25>;
+            clocks = <&clkctrl 25>;
+            phys = <&pcie0_phy 1>;
+            phy-names = "pcie-phy1";
+            ranges;
+        };
+
+        pcie@2,0 {
+            reg = <0x1000 0 0 0 0>;
+            #address-cells = <3>;
+            #size-cells = <2>;
+            device_type = "pci";
+            #interrupt-cells = <1>;
+            interrupt-map-mask = <0 0 0 0>;
+            interrupt-map = <0 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
+            resets = <&rstctrl 26>;
+            clocks = <&clkctrl 26>;
+            phys = <&pcie2_phy 0>;
+            phy-names = "pcie-phy2";
+            ranges;
+        };
+    };
+...
-- 
2.25.1


^ permalink raw reply	[flat|nested] 10+ messages in thread

* [PATCH v2 2/3] PCI: mt7621: Add MediaTek MT7621 PCIe host controller driver
  2021-06-09 14:01 [PATCH v2 0/3] PCI: mt7621: Add MediaTek MT7621 PCIe host controller driver Sergio Paracuellos
  2021-06-09 14:01 ` [PATCH v2 1/3] dt-bindings: mt7621-pci: PCIe binding documentation for MT7621 SoCs Sergio Paracuellos
@ 2021-06-09 14:01 ` Sergio Paracuellos
  2021-08-05 10:32   ` Lorenzo Pieralisi
  2021-06-09 14:01 ` [PATCH v2 3/3] MAINTAINERS: add myself as maintainer of the MT7621 PCI " Sergio Paracuellos
  2021-06-17  6:00 ` [PATCH v2 0/3] PCI: mt7621: Add MediaTek MT7621 PCIe host " Sergio Paracuellos
  3 siblings, 1 reply; 10+ messages in thread
From: Sergio Paracuellos @ 2021-06-09 14:01 UTC (permalink / raw)
  To: linux-pci
  Cc: linux-mips, tsbogend, devicetree, matthias.bgg, john, bhelgaas,
	robh+dt, linux-staging, gregkh, neil, ilya.lipnitskiy,
	linux-kernel, pali

Add driver for the PCIe controller of the MT7621 SoC.

Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 arch/mips/ralink/Kconfig                      |   2 +-
 drivers/pci/controller/Kconfig                |   8 ++
 drivers/pci/controller/Makefile               |   1 +
 .../controller}/pci-mt7621.c                  |   0
 drivers/staging/Kconfig                       |   2 -
 drivers/staging/Makefile                      |   1 -
 drivers/staging/mt7621-pci/Kconfig            |   8 --
 drivers/staging/mt7621-pci/Makefile           |   2 -
 drivers/staging/mt7621-pci/TODO               |   4 -
 .../mt7621-pci/mediatek,mt7621-pci.txt        | 104 ------------------
 10 files changed, 10 insertions(+), 122 deletions(-)
 rename drivers/{staging/mt7621-pci => pci/controller}/pci-mt7621.c (100%)
 delete mode 100644 drivers/staging/mt7621-pci/Kconfig
 delete mode 100644 drivers/staging/mt7621-pci/Makefile
 delete mode 100644 drivers/staging/mt7621-pci/TODO
 delete mode 100644 drivers/staging/mt7621-pci/mediatek,mt7621-pci.txt

diff --git a/arch/mips/ralink/Kconfig b/arch/mips/ralink/Kconfig
index ec4daa63c5e3..461e33d20c9c 100644
--- a/arch/mips/ralink/Kconfig
+++ b/arch/mips/ralink/Kconfig
@@ -56,7 +56,7 @@ choice
 		select MIPS_GIC
 		select COMMON_CLK
 		select CLKSRC_MIPS_GIC
-		select HAVE_PCI if PCI_MT7621
+		select HAVE_PCI
 		select SOC_BUS
 endchoice
 
diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
index 2f2c8a1729f9..6b006df87884 100644
--- a/drivers/pci/controller/Kconfig
+++ b/drivers/pci/controller/Kconfig
@@ -303,6 +303,14 @@ config PCIE_HISI_ERR
 	  Say Y here if you want error handling support
 	  for the PCIe controller's errors on HiSilicon HIP SoCs
 
+config PCI_MT7621
+	bool "MediaTek MT7621 PCI Controller"
+	depends on (RALINK && SOC_MT7621) || (MIPS && COMPILE_TEST)
+	select PCI_DRIVERS_GENERIC
+	default SOC_MT7621
+	help
+	  This selects a driver for the MediaTek MT7621 PCI Controller.
+
 source "drivers/pci/controller/dwc/Kconfig"
 source "drivers/pci/controller/mobiveil/Kconfig"
 source "drivers/pci/controller/cadence/Kconfig"
diff --git a/drivers/pci/controller/Makefile b/drivers/pci/controller/Makefile
index 63e3880a3e87..ac902dc4e1a9 100644
--- a/drivers/pci/controller/Makefile
+++ b/drivers/pci/controller/Makefile
@@ -36,6 +36,7 @@ obj-$(CONFIG_VMD) += vmd.o
 obj-$(CONFIG_PCIE_BRCMSTB) += pcie-brcmstb.o
 obj-$(CONFIG_PCI_LOONGSON) += pci-loongson.o
 obj-$(CONFIG_PCIE_HISI_ERR) += pcie-hisi-error.o
+obj-$(CONFIG_PCI_MT7621) += pci-mt7621.o
 # pcie-hisi.o quirks are needed even without CONFIG_PCIE_DW
 obj-y				+= dwc/
 obj-y				+= mobiveil/
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/pci/controller/pci-mt7621.c
similarity index 100%
rename from drivers/staging/mt7621-pci/pci-mt7621.c
rename to drivers/pci/controller/pci-mt7621.c
diff --git a/drivers/staging/Kconfig b/drivers/staging/Kconfig
index b7ae5bdc4eb5..9a21d730ab2b 100644
--- a/drivers/staging/Kconfig
+++ b/drivers/staging/Kconfig
@@ -86,8 +86,6 @@ source "drivers/staging/vc04_services/Kconfig"
 
 source "drivers/staging/pi433/Kconfig"
 
-source "drivers/staging/mt7621-pci/Kconfig"
-
 source "drivers/staging/mt7621-dma/Kconfig"
 
 source "drivers/staging/ralink-gdma/Kconfig"
diff --git a/drivers/staging/Makefile b/drivers/staging/Makefile
index 075c979bfe7c..b7b4916761d4 100644
--- a/drivers/staging/Makefile
+++ b/drivers/staging/Makefile
@@ -33,7 +33,6 @@ obj-$(CONFIG_KS7010)		+= ks7010/
 obj-$(CONFIG_GREYBUS)		+= greybus/
 obj-$(CONFIG_BCM2835_VCHIQ)	+= vc04_services/
 obj-$(CONFIG_PI433)		+= pi433/
-obj-$(CONFIG_PCI_MT7621)	+= mt7621-pci/
 obj-$(CONFIG_SOC_MT7621)	+= mt7621-dma/
 obj-$(CONFIG_DMA_RALINK)	+= ralink-gdma/
 obj-$(CONFIG_SOC_MT7621)	+= mt7621-dts/
diff --git a/drivers/staging/mt7621-pci/Kconfig b/drivers/staging/mt7621-pci/Kconfig
deleted file mode 100644
index ce58042f2f21..000000000000
--- a/drivers/staging/mt7621-pci/Kconfig
+++ /dev/null
@@ -1,8 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-config PCI_MT7621
-	tristate "MediaTek MT7621 PCI Controller"
-	depends on RALINK
-	select PCI_DRIVERS_GENERIC
-	help
-	  This selects a driver for the MediaTek MT7621 PCI Controller.
-
diff --git a/drivers/staging/mt7621-pci/Makefile b/drivers/staging/mt7621-pci/Makefile
deleted file mode 100644
index f4e651cf7ce3..000000000000
--- a/drivers/staging/mt7621-pci/Makefile
+++ /dev/null
@@ -1,2 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-obj-$(CONFIG_PCI_MT7621)       += pci-mt7621.o
diff --git a/drivers/staging/mt7621-pci/TODO b/drivers/staging/mt7621-pci/TODO
deleted file mode 100644
index d674a9ac85c1..000000000000
--- a/drivers/staging/mt7621-pci/TODO
+++ /dev/null
@@ -1,4 +0,0 @@
-
-- general code review and cleanup
-
-Cc: NeilBrown <neil@brown.name>
diff --git a/drivers/staging/mt7621-pci/mediatek,mt7621-pci.txt b/drivers/staging/mt7621-pci/mediatek,mt7621-pci.txt
deleted file mode 100644
index 327a68267309..000000000000
--- a/drivers/staging/mt7621-pci/mediatek,mt7621-pci.txt
+++ /dev/null
@@ -1,104 +0,0 @@
-MediaTek MT7621 PCIe controller
-
-Required properties:
-- compatible: "mediatek,mt7621-pci"
-- device_type: Must be "pci"
-- reg: Base addresses and lengths of the PCIe subsys and root ports.
-- bus-range: Range of bus numbers associated with this controller.
-- #address-cells: Address representation for root ports (must be 3)
-- pinctrl-names : The pin control state names.
-- pinctrl-0: The "default" pinctrl state.
-- #size-cells: Size representation for root ports (must be 2)
-- ranges: Ranges for the PCI memory and I/O regions.
-- #interrupt-cells: Must be 1
-- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties.
-  Please refer to the standard PCI bus binding document for a more detailed
-  explanation.
-- status: either "disabled" or "okay".
-- resets: Must contain an entry for each entry in reset-names.
-  See ../reset/reset.txt for details.
-- reset-names: Must be "pcie0", "pcie1", "pcieN"... based on the number of
-  root ports.
-- clocks: Must contain an entry for each entry in clock-names.
-  See ../clocks/clock-bindings.txt for details.
-- clock-names: Must be "pcie0", "pcie1", "pcieN"... based on the number of
-  root ports.
-- reset-gpios: GPIO specs for the reset pins.
-
-In addition, the device tree node must have sub-nodes describing each PCIe port
-interface, having the following mandatory properties:
-
-Required properties:
-- reg: Only the first four bytes are used to refer to the correct bus number
-      and device number.
-- #address-cells: Must be 3
-- #size-cells: Must be 2
-- ranges: Sub-ranges distributed from the PCIe controller node. An empty
-  property is sufficient.
-- bus-range: Range of bus numbers associated with this port.
-
-Example for MT7621:
-
-	pcie: pcie@1e140000 {
-		compatible = "mediatek,mt7621-pci";
-        reg = <0x1e140000 0x100    /* host-pci bridge registers */
-               0x1e142000 0x100    /* pcie port 0 RC control registers */
-               0x1e143000 0x100    /* pcie port 1 RC control registers */
-               0x1e144000 0x100>;  /* pcie port 2 RC control registers */
-
-		#address-cells = <3>;
-		#size-cells = <2>;
-
-		pinctrl-names = "default";
-		pinctrl-0 = <&pcie_pins>;
-
-		device_type = "pci";
-
-		bus-range = <0 255>;
-		ranges = <
-			0x02000000 0 0x00000000 0x60000000 0 0x10000000 /* pci memory */
-			0x01000000 0 0x00000000 0x1e160000 0 0x00010000 /* io space */
-		>;
-
-		#interrupt-cells = <1>;
-		interrupt-map-mask = <0xF0000 0 0 1>;
-		interrupt-map = <0x10000 0 0 1 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>,
-				<0x20000 0 0 1 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>,
-				<0x30000 0 0 1 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
-
-		status = "disabled";
-
-		resets = <&rstctrl 24 &rstctrl 25 &rstctrl 26>;
-		reset-names = "pcie0", "pcie1", "pcie2";
-		clocks = <&clkctrl 24 &clkctrl 25 &clkctrl 26>;
-		clock-names = "pcie0", "pcie1", "pcie2";
-
-		reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>,
-				<&gpio 8 GPIO_ACTIVE_LOW>,
-				<&gpio 7 GPIO_ACTIVE_LOW>;
-
-		pcie@0,0 {
-			reg = <0x0000 0 0 0 0>;
-			#address-cells = <3>;
-			#size-cells = <2>;
-			ranges;
-			bus-range = <0x00 0xff>;
-		};
-
-		pcie@1,0 {
-			reg = <0x0800 0 0 0 0>;
-			#address-cells = <3>;
-			#size-cells = <2>;
-			ranges;
-			bus-range = <0x00 0xff>;
-		};
-
-		pcie@2,0 {
-			reg = <0x1000 0 0 0 0>;
-			#address-cells = <3>;
-			#size-cells = <2>;
-			ranges;
-			bus-range = <0x00 0xff>;
-		};
-	};
-
-- 
2.25.1


^ permalink raw reply	[flat|nested] 10+ messages in thread

* [PATCH v2 3/3] MAINTAINERS: add myself as maintainer of the MT7621 PCI controller driver
  2021-06-09 14:01 [PATCH v2 0/3] PCI: mt7621: Add MediaTek MT7621 PCIe host controller driver Sergio Paracuellos
  2021-06-09 14:01 ` [PATCH v2 1/3] dt-bindings: mt7621-pci: PCIe binding documentation for MT7621 SoCs Sergio Paracuellos
  2021-06-09 14:01 ` [PATCH v2 2/3] PCI: mt7621: Add MediaTek MT7621 PCIe host controller driver Sergio Paracuellos
@ 2021-06-09 14:01 ` Sergio Paracuellos
  2021-06-17  6:00 ` [PATCH v2 0/3] PCI: mt7621: Add MediaTek MT7621 PCIe host " Sergio Paracuellos
  3 siblings, 0 replies; 10+ messages in thread
From: Sergio Paracuellos @ 2021-06-09 14:01 UTC (permalink / raw)
  To: linux-pci
  Cc: linux-mips, tsbogend, devicetree, matthias.bgg, john, bhelgaas,
	robh+dt, linux-staging, gregkh, neil, ilya.lipnitskiy,
	linux-kernel, pali

Add myself as maintainer of the PCie Controlller driver for
MT7621 SoCs.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 MAINTAINERS | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 9c55fdcc1514..2e58fba01289 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -11574,6 +11574,12 @@ S:	Maintained
 F:	Documentation/devicetree/bindings/i2c/i2c-mt7621.txt
 F:	drivers/i2c/busses/i2c-mt7621.c
 
+MEDIATEK MT7621 PCI CONTROLLER DRIVER
+M:	Sergio Paracuellos <sergio.paracuellos@gmail.com>
+S:	Maintained
+F:	Documentation/devicetree/bindings/pci/mediatek,mt7621-pci.yaml
+F:	drivers/pci/controller/pci-mt7621.c
+
 MEDIATEK MT7621 PHY PCI DRIVER
 M:	Sergio Paracuellos <sergio.paracuellos@gmail.com>
 S:	Maintained
-- 
2.25.1


^ permalink raw reply	[flat|nested] 10+ messages in thread

* Re: [PATCH v2 0/3] PCI: mt7621: Add MediaTek MT7621 PCIe host controller driver
  2021-06-09 14:01 [PATCH v2 0/3] PCI: mt7621: Add MediaTek MT7621 PCIe host controller driver Sergio Paracuellos
                   ` (2 preceding siblings ...)
  2021-06-09 14:01 ` [PATCH v2 3/3] MAINTAINERS: add myself as maintainer of the MT7621 PCI " Sergio Paracuellos
@ 2021-06-17  6:00 ` Sergio Paracuellos
  3 siblings, 0 replies; 10+ messages in thread
From: Sergio Paracuellos @ 2021-06-17  6:00 UTC (permalink / raw)
  To: linux-pci
  Cc: open list:MIPS, Thomas Bogendoerfer,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	Matthias Brugger, John Crispin, Bjorn Helgaas, Rob Herring,
	linux-staging, Greg KH, NeilBrown, Ilya Lipnitskiy, linux-kernel,
	Pali Rohár

Hi,

On Wed, Jun 9, 2021 at 4:02 PM Sergio Paracuellos
<sergio.paracuellos@gmail.com> wrote:
>
> MediaTek MT7621 PCIe subsys supports single Root complex (RC)
> with 3 Root Ports. Each Root Ports supports a Gen1 1-lane Link.
> Topology is as follows:
>
>                           MT7621 PCIe HOST Topology
>
>                                    .-------.
>                                    |       |
>                                    |  CPU  |
>                                    |       |
>                                    '-------'
>                                        |
>                                        |
>                                        |
>                                        v
>                               .------------------.
>                   .-----------|  HOST/PCI Bridge |------------.
>                   |           '------------------'            |     Type1
>          BUS0     |                     |                     |    Access
>                   v                     v                     v    On Bus0
>           .-------------.        .-------------.       .-------------.
>           | VIRTUAL P2P |        | VIRTUAL P2P |       | VIRTUAL P2P |
>           |    BUS0     |        |    BUS0     |       |    BUS0     |
>           |    DEV0     |        |    DEV1     |       |    DEV2     |
>           '-------------'        '-------------'       '-------------'
>     Type0        |          Type0       |         Type0       |
>    Access   BUS1 |         Access   BUS2|        Access   BUS3|
>    On Bus1       v         On Bus2      v        On Bus3      v
>            .----------.           .----------.          .----------.
>            | Device 0 |           | Device 0 |          | Device 0 |
>            |  Func 0  |           |  Func 0  |          |  Func 0  |
>            '----------'           '----------'          '----------'
>
> This driver has been very long time in staging and I have been cleaning
> it from its first versions where there was code kaos and PCI_LEGACY support.
> Original code came probably from openWRT based on mediatek's SDK code. There
> is no documentation at all about the mt7621 PCI subsystem.
> I have been cleaning it targeting mt7621 SoC which is the one I use in
> my GNUBee PC1 board and HiLink HLK-MT7621A evaluation board.
>
> Now I think is clean enough to be moved into 'drivers/pci/controller'.
> This driver is mips/ralink architecture and need 'mips_cps_numiocu()'
> to properly configure iocu regions for mips.
>
> This driver also uses already mainlined pci phy driver located in
> 'drivers/phy/ralink/phy-mt7621-pci.c'. There are two instances of
> the phy being the first one dual ported for pci0 and pci1, and the
> second one not dual ported dedicated to pci2. Because of writing twice
> some phy registers of the dual-ported one sometimes become in not
> confident boot cycles we have to take care of this when device link
> is checked here in controller driver. We power on the dual ported-phy
> if there is something connected in pcie0 or pcie1. In the same manner
> we have to properly disable it only if nothing is connected in of both
> pcie0 and pcie1 slots.
>
> Another thing that must be mentioned is that this driver uses IO
> in physical address 0x001e160000. IO_SPACE_LIMIT for MIPS is 0xffff
> so some generic PCI functions (like of_pci_range_to_resource) won't
> work and the resource ranges part for IO is set manually.

This has been fixed and now there is no need to set io resources manually.
See [0].

>
> Changes in v2:
>     - Make one commit moving driver directly from staging into
>      'drivers/pci/controllers' instead of two commits making
>      one add and a later remove.
>     - Update binding documentation moving 'clocks', 'resets' and
>      'phys' properties to child root bridge nodes.
>     - Update code to properly be able to use new bindings.
>     - Kconfig: add || (MIPS && COMPILE_TEST).
>     - Use {read/write}_relaxed versions.
>     - Use 'PCI_BASE_ADDRESS_0' instead of a custom definition.
>     - Avoid to set 'PCI_COMMAND_MASTER' and re-do functions
>      'mt7621_pcie_enable_ports' and 'mt7621_pcie_enable_port'.

I forgot to comment that all of these changes are rebased on the top
of staging-next.
Since this is a 'git mv' as I was told to do by Bjorn, last version of
the code is available
here [1] with the following added changes to the ones listed above
from previously submitted v1 series:

- Define PCI_IOBASE for mips (spaces.h) to avoid parsing io resources manually
so 'mt7621_pci_parse_request_of_pci_ranges' is not needed anymore.
- Don't store resources in driver private data but just get them to properly
set io window register and mips iocu memory regions.

Thanks in advance for your time.

Best regards,
    Sergio Paracuellos

[0]: https://lore.kernel.org/linux-staging/20210614100617.28753-1-sergio.paracuellos@gmail.com/T/#t
[1]: https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging.git/tree/drivers/staging/mt7621-pci/pci-mt7621.c?h=staging-next

>
> NOTE: Greg, I have maintained your Acked-by from previous series in
> delete driver commit and added in the one which is moving code here
> and delete the remaining stuff. If you are not ok with this, just
> let me now and I'll drop it and resend.
>
> Thanks in advance for your time.
>
> Best regards,
>     Sergio Paracuellos
>
> Sergio Paracuellos (3):
>   dt-bindings: mt7621-pci: PCIe binding documentation for MT7621 SoCs
>   PCI: mt7621: Add MediaTek MT7621 PCIe host controller driver
>   MAINTAINERS: add myself as maintainer of the MT7621 PCI controller
>     driver
>
>  .../bindings/pci/mediatek,mt7621-pci.yaml     | 142 ++++++++++++++++++
>  MAINTAINERS                                   |   6 +
>  arch/mips/ralink/Kconfig                      |   2 +-
>  drivers/pci/controller/Kconfig                |   8 +
>  drivers/pci/controller/Makefile               |   1 +
>  .../controller}/pci-mt7621.c                  |   0
>  drivers/staging/Kconfig                       |   2 -
>  drivers/staging/Makefile                      |   1 -
>  drivers/staging/mt7621-pci/Kconfig            |   8 -
>  drivers/staging/mt7621-pci/Makefile           |   2 -
>  drivers/staging/mt7621-pci/TODO               |   4 -
>  .../mt7621-pci/mediatek,mt7621-pci.txt        | 104 -------------
>  12 files changed, 158 insertions(+), 122 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/pci/mediatek,mt7621-pci.yaml
>  rename drivers/{staging/mt7621-pci => pci/controller}/pci-mt7621.c (100%)
>  delete mode 100644 drivers/staging/mt7621-pci/Kconfig
>  delete mode 100644 drivers/staging/mt7621-pci/Makefile
>  delete mode 100644 drivers/staging/mt7621-pci/TODO
>  delete mode 100644 drivers/staging/mt7621-pci/mediatek,mt7621-pci.txt
>
> --
> 2.25.1
>

^ permalink raw reply	[flat|nested] 10+ messages in thread

* Re: [PATCH v2 1/3] dt-bindings: mt7621-pci: PCIe binding documentation for MT7621 SoCs
  2021-06-09 14:01 ` [PATCH v2 1/3] dt-bindings: mt7621-pci: PCIe binding documentation for MT7621 SoCs Sergio Paracuellos
@ 2021-06-18 21:08   ` Rob Herring
  0 siblings, 0 replies; 10+ messages in thread
From: Rob Herring @ 2021-06-18 21:08 UTC (permalink / raw)
  To: Sergio Paracuellos
  Cc: pali, tsbogend, linux-kernel, neil, linux-mips, linux-pci, john,
	robh+dt, devicetree, ilya.lipnitskiy, matthias.bgg,
	linux-staging, bhelgaas, gregkh

On Wed, 09 Jun 2021 16:01:57 +0200, Sergio Paracuellos wrote:
> Add device tree binding documentation for PCIe in MT7621 SoCs.
> 
> Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
> ---
>  .../bindings/pci/mediatek,mt7621-pci.yaml     | 142 ++++++++++++++++++
>  1 file changed, 142 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/pci/mediatek,mt7621-pci.yaml
> 

Reviewed-by: Rob Herring <robh@kernel.org>

^ permalink raw reply	[flat|nested] 10+ messages in thread

* Re: [PATCH v2 2/3] PCI: mt7621: Add MediaTek MT7621 PCIe host controller driver
  2021-06-09 14:01 ` [PATCH v2 2/3] PCI: mt7621: Add MediaTek MT7621 PCIe host controller driver Sergio Paracuellos
@ 2021-08-05 10:32   ` Lorenzo Pieralisi
  2021-08-05 10:40     ` Sergio Paracuellos
  0 siblings, 1 reply; 10+ messages in thread
From: Lorenzo Pieralisi @ 2021-08-05 10:32 UTC (permalink / raw)
  To: Sergio Paracuellos
  Cc: linux-pci, linux-mips, tsbogend, devicetree, matthias.bgg, john,
	bhelgaas, robh+dt, linux-staging, gregkh, neil, ilya.lipnitskiy,
	linux-kernel, pali

On Wed, Jun 09, 2021 at 04:01:58PM +0200, Sergio Paracuellos wrote:
> Add driver for the PCIe controller of the MT7621 SoC.
> 
> Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
> Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
> ---
>  arch/mips/ralink/Kconfig                      |   2 +-
>  drivers/pci/controller/Kconfig                |   8 ++
>  drivers/pci/controller/Makefile               |   1 +
>  .../controller}/pci-mt7621.c                  |   0
>  drivers/staging/Kconfig                       |   2 -
>  drivers/staging/Makefile                      |   1 -
>  drivers/staging/mt7621-pci/Kconfig            |   8 --
>  drivers/staging/mt7621-pci/Makefile           |   2 -
>  drivers/staging/mt7621-pci/TODO               |   4 -
>  .../mt7621-pci/mediatek,mt7621-pci.txt        | 104 ------------------
>  10 files changed, 10 insertions(+), 122 deletions(-)
>  rename drivers/{staging/mt7621-pci => pci/controller}/pci-mt7621.c (100%)
>  delete mode 100644 drivers/staging/mt7621-pci/Kconfig
>  delete mode 100644 drivers/staging/mt7621-pci/Makefile
>  delete mode 100644 drivers/staging/mt7621-pci/TODO
>  delete mode 100644 drivers/staging/mt7621-pci/mediatek,mt7621-pci.txt
> 
> diff --git a/arch/mips/ralink/Kconfig b/arch/mips/ralink/Kconfig
> index ec4daa63c5e3..461e33d20c9c 100644
> --- a/arch/mips/ralink/Kconfig
> +++ b/arch/mips/ralink/Kconfig
> @@ -56,7 +56,7 @@ choice
>  		select MIPS_GIC
>  		select COMMON_CLK
>  		select CLKSRC_MIPS_GIC
> -		select HAVE_PCI if PCI_MT7621
> +		select HAVE_PCI
>  		select SOC_BUS
>  endchoice
>  
> diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
> index 2f2c8a1729f9..6b006df87884 100644
> --- a/drivers/pci/controller/Kconfig
> +++ b/drivers/pci/controller/Kconfig
> @@ -303,6 +303,14 @@ config PCIE_HISI_ERR
>  	  Say Y here if you want error handling support
>  	  for the PCIe controller's errors on HiSilicon HIP SoCs
>  
> +config PCI_MT7621
> +	bool "MediaTek MT7621 PCI Controller"
> +	depends on (RALINK && SOC_MT7621) || (MIPS && COMPILE_TEST)
> +	select PCI_DRIVERS_GENERIC

Can this be selected in arch/mips rather than here ?

Thanks,
Lorenzo

> +	default SOC_MT7621
> +	help
> +	  This selects a driver for the MediaTek MT7621 PCI Controller.
> +
>  source "drivers/pci/controller/dwc/Kconfig"
>  source "drivers/pci/controller/mobiveil/Kconfig"
>  source "drivers/pci/controller/cadence/Kconfig"
> diff --git a/drivers/pci/controller/Makefile b/drivers/pci/controller/Makefile
> index 63e3880a3e87..ac902dc4e1a9 100644
> --- a/drivers/pci/controller/Makefile
> +++ b/drivers/pci/controller/Makefile
> @@ -36,6 +36,7 @@ obj-$(CONFIG_VMD) += vmd.o
>  obj-$(CONFIG_PCIE_BRCMSTB) += pcie-brcmstb.o
>  obj-$(CONFIG_PCI_LOONGSON) += pci-loongson.o
>  obj-$(CONFIG_PCIE_HISI_ERR) += pcie-hisi-error.o
> +obj-$(CONFIG_PCI_MT7621) += pci-mt7621.o
>  # pcie-hisi.o quirks are needed even without CONFIG_PCIE_DW
>  obj-y				+= dwc/
>  obj-y				+= mobiveil/
> diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/pci/controller/pci-mt7621.c
> similarity index 100%
> rename from drivers/staging/mt7621-pci/pci-mt7621.c
> rename to drivers/pci/controller/pci-mt7621.c
> diff --git a/drivers/staging/Kconfig b/drivers/staging/Kconfig
> index b7ae5bdc4eb5..9a21d730ab2b 100644
> --- a/drivers/staging/Kconfig
> +++ b/drivers/staging/Kconfig
> @@ -86,8 +86,6 @@ source "drivers/staging/vc04_services/Kconfig"
>  
>  source "drivers/staging/pi433/Kconfig"
>  
> -source "drivers/staging/mt7621-pci/Kconfig"
> -
>  source "drivers/staging/mt7621-dma/Kconfig"
>  
>  source "drivers/staging/ralink-gdma/Kconfig"
> diff --git a/drivers/staging/Makefile b/drivers/staging/Makefile
> index 075c979bfe7c..b7b4916761d4 100644
> --- a/drivers/staging/Makefile
> +++ b/drivers/staging/Makefile
> @@ -33,7 +33,6 @@ obj-$(CONFIG_KS7010)		+= ks7010/
>  obj-$(CONFIG_GREYBUS)		+= greybus/
>  obj-$(CONFIG_BCM2835_VCHIQ)	+= vc04_services/
>  obj-$(CONFIG_PI433)		+= pi433/
> -obj-$(CONFIG_PCI_MT7621)	+= mt7621-pci/
>  obj-$(CONFIG_SOC_MT7621)	+= mt7621-dma/
>  obj-$(CONFIG_DMA_RALINK)	+= ralink-gdma/
>  obj-$(CONFIG_SOC_MT7621)	+= mt7621-dts/
> diff --git a/drivers/staging/mt7621-pci/Kconfig b/drivers/staging/mt7621-pci/Kconfig
> deleted file mode 100644
> index ce58042f2f21..000000000000
> --- a/drivers/staging/mt7621-pci/Kconfig
> +++ /dev/null
> @@ -1,8 +0,0 @@
> -# SPDX-License-Identifier: GPL-2.0
> -config PCI_MT7621
> -	tristate "MediaTek MT7621 PCI Controller"
> -	depends on RALINK
> -	select PCI_DRIVERS_GENERIC
> -	help
> -	  This selects a driver for the MediaTek MT7621 PCI Controller.
> -
> diff --git a/drivers/staging/mt7621-pci/Makefile b/drivers/staging/mt7621-pci/Makefile
> deleted file mode 100644
> index f4e651cf7ce3..000000000000
> --- a/drivers/staging/mt7621-pci/Makefile
> +++ /dev/null
> @@ -1,2 +0,0 @@
> -# SPDX-License-Identifier: GPL-2.0
> -obj-$(CONFIG_PCI_MT7621)       += pci-mt7621.o
> diff --git a/drivers/staging/mt7621-pci/TODO b/drivers/staging/mt7621-pci/TODO
> deleted file mode 100644
> index d674a9ac85c1..000000000000
> --- a/drivers/staging/mt7621-pci/TODO
> +++ /dev/null
> @@ -1,4 +0,0 @@
> -
> -- general code review and cleanup
> -
> -Cc: NeilBrown <neil@brown.name>
> diff --git a/drivers/staging/mt7621-pci/mediatek,mt7621-pci.txt b/drivers/staging/mt7621-pci/mediatek,mt7621-pci.txt
> deleted file mode 100644
> index 327a68267309..000000000000
> --- a/drivers/staging/mt7621-pci/mediatek,mt7621-pci.txt
> +++ /dev/null
> @@ -1,104 +0,0 @@
> -MediaTek MT7621 PCIe controller
> -
> -Required properties:
> -- compatible: "mediatek,mt7621-pci"
> -- device_type: Must be "pci"
> -- reg: Base addresses and lengths of the PCIe subsys and root ports.
> -- bus-range: Range of bus numbers associated with this controller.
> -- #address-cells: Address representation for root ports (must be 3)
> -- pinctrl-names : The pin control state names.
> -- pinctrl-0: The "default" pinctrl state.
> -- #size-cells: Size representation for root ports (must be 2)
> -- ranges: Ranges for the PCI memory and I/O regions.
> -- #interrupt-cells: Must be 1
> -- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties.
> -  Please refer to the standard PCI bus binding document for a more detailed
> -  explanation.
> -- status: either "disabled" or "okay".
> -- resets: Must contain an entry for each entry in reset-names.
> -  See ../reset/reset.txt for details.
> -- reset-names: Must be "pcie0", "pcie1", "pcieN"... based on the number of
> -  root ports.
> -- clocks: Must contain an entry for each entry in clock-names.
> -  See ../clocks/clock-bindings.txt for details.
> -- clock-names: Must be "pcie0", "pcie1", "pcieN"... based on the number of
> -  root ports.
> -- reset-gpios: GPIO specs for the reset pins.
> -
> -In addition, the device tree node must have sub-nodes describing each PCIe port
> -interface, having the following mandatory properties:
> -
> -Required properties:
> -- reg: Only the first four bytes are used to refer to the correct bus number
> -      and device number.
> -- #address-cells: Must be 3
> -- #size-cells: Must be 2
> -- ranges: Sub-ranges distributed from the PCIe controller node. An empty
> -  property is sufficient.
> -- bus-range: Range of bus numbers associated with this port.
> -
> -Example for MT7621:
> -
> -	pcie: pcie@1e140000 {
> -		compatible = "mediatek,mt7621-pci";
> -        reg = <0x1e140000 0x100    /* host-pci bridge registers */
> -               0x1e142000 0x100    /* pcie port 0 RC control registers */
> -               0x1e143000 0x100    /* pcie port 1 RC control registers */
> -               0x1e144000 0x100>;  /* pcie port 2 RC control registers */
> -
> -		#address-cells = <3>;
> -		#size-cells = <2>;
> -
> -		pinctrl-names = "default";
> -		pinctrl-0 = <&pcie_pins>;
> -
> -		device_type = "pci";
> -
> -		bus-range = <0 255>;
> -		ranges = <
> -			0x02000000 0 0x00000000 0x60000000 0 0x10000000 /* pci memory */
> -			0x01000000 0 0x00000000 0x1e160000 0 0x00010000 /* io space */
> -		>;
> -
> -		#interrupt-cells = <1>;
> -		interrupt-map-mask = <0xF0000 0 0 1>;
> -		interrupt-map = <0x10000 0 0 1 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>,
> -				<0x20000 0 0 1 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>,
> -				<0x30000 0 0 1 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
> -
> -		status = "disabled";
> -
> -		resets = <&rstctrl 24 &rstctrl 25 &rstctrl 26>;
> -		reset-names = "pcie0", "pcie1", "pcie2";
> -		clocks = <&clkctrl 24 &clkctrl 25 &clkctrl 26>;
> -		clock-names = "pcie0", "pcie1", "pcie2";
> -
> -		reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>,
> -				<&gpio 8 GPIO_ACTIVE_LOW>,
> -				<&gpio 7 GPIO_ACTIVE_LOW>;
> -
> -		pcie@0,0 {
> -			reg = <0x0000 0 0 0 0>;
> -			#address-cells = <3>;
> -			#size-cells = <2>;
> -			ranges;
> -			bus-range = <0x00 0xff>;
> -		};
> -
> -		pcie@1,0 {
> -			reg = <0x0800 0 0 0 0>;
> -			#address-cells = <3>;
> -			#size-cells = <2>;
> -			ranges;
> -			bus-range = <0x00 0xff>;
> -		};
> -
> -		pcie@2,0 {
> -			reg = <0x1000 0 0 0 0>;
> -			#address-cells = <3>;
> -			#size-cells = <2>;
> -			ranges;
> -			bus-range = <0x00 0xff>;
> -		};
> -	};
> -
> -- 
> 2.25.1
> 

^ permalink raw reply	[flat|nested] 10+ messages in thread

* Re: [PATCH v2 2/3] PCI: mt7621: Add MediaTek MT7621 PCIe host controller driver
  2021-08-05 10:32   ` Lorenzo Pieralisi
@ 2021-08-05 10:40     ` Sergio Paracuellos
  2021-08-05 10:45       ` Lorenzo Pieralisi
  0 siblings, 1 reply; 10+ messages in thread
From: Sergio Paracuellos @ 2021-08-05 10:40 UTC (permalink / raw)
  To: Lorenzo Pieralisi
  Cc: linux-pci, open list:MIPS, Thomas Bogendoerfer,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	Matthias Brugger, John Crispin, Bjorn Helgaas, Rob Herring,
	linux-staging, Greg KH, NeilBrown, Ilya Lipnitskiy, linux-kernel,
	Pali Rohár

Hi Lorenzo,

On Thu, Aug 5, 2021 at 12:32 PM Lorenzo Pieralisi
<lorenzo.pieralisi@arm.com> wrote:
>
> On Wed, Jun 09, 2021 at 04:01:58PM +0200, Sergio Paracuellos wrote:
> > Add driver for the PCIe controller of the MT7621 SoC.
> >
> > Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
> > Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
> > ---
> >  arch/mips/ralink/Kconfig                      |   2 +-
> >  drivers/pci/controller/Kconfig                |   8 ++
> >  drivers/pci/controller/Makefile               |   1 +
> >  .../controller}/pci-mt7621.c                  |   0
> >  drivers/staging/Kconfig                       |   2 -
> >  drivers/staging/Makefile                      |   1 -
> >  drivers/staging/mt7621-pci/Kconfig            |   8 --
> >  drivers/staging/mt7621-pci/Makefile           |   2 -
> >  drivers/staging/mt7621-pci/TODO               |   4 -
> >  .../mt7621-pci/mediatek,mt7621-pci.txt        | 104 ------------------
> >  10 files changed, 10 insertions(+), 122 deletions(-)
> >  rename drivers/{staging/mt7621-pci => pci/controller}/pci-mt7621.c (100%)
> >  delete mode 100644 drivers/staging/mt7621-pci/Kconfig
> >  delete mode 100644 drivers/staging/mt7621-pci/Makefile
> >  delete mode 100644 drivers/staging/mt7621-pci/TODO
> >  delete mode 100644 drivers/staging/mt7621-pci/mediatek,mt7621-pci.txt
> >
> > diff --git a/arch/mips/ralink/Kconfig b/arch/mips/ralink/Kconfig
> > index ec4daa63c5e3..461e33d20c9c 100644
> > --- a/arch/mips/ralink/Kconfig
> > +++ b/arch/mips/ralink/Kconfig
> > @@ -56,7 +56,7 @@ choice
> >               select MIPS_GIC
> >               select COMMON_CLK
> >               select CLKSRC_MIPS_GIC
> > -             select HAVE_PCI if PCI_MT7621
> > +             select HAVE_PCI
> >               select SOC_BUS
> >  endchoice
> >
> > diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
> > index 2f2c8a1729f9..6b006df87884 100644
> > --- a/drivers/pci/controller/Kconfig
> > +++ b/drivers/pci/controller/Kconfig
> > @@ -303,6 +303,14 @@ config PCIE_HISI_ERR
> >         Say Y here if you want error handling support
> >         for the PCIe controller's errors on HiSilicon HIP SoCs
> >
> > +config PCI_MT7621
> > +     bool "MediaTek MT7621 PCI Controller"
> > +     depends on (RALINK && SOC_MT7621) || (MIPS && COMPILE_TEST)
> > +     select PCI_DRIVERS_GENERIC
>
> Can this be selected in arch/mips rather than here ?

No real problem for me, but I was suggested by Bjorn and Pali to put
all the driver inside 'drivers/pci/controller'. Do you mean to move
all to arch/mips or only the Kconfig part?

Thanks,
    Sergio Paracuellos

>
> Thanks,
> Lorenzo
>
> > +     default SOC_MT7621
> > +     help
> > +       This selects a driver for the MediaTek MT7621 PCI Controller.
> > +
> >  source "drivers/pci/controller/dwc/Kconfig"
> >  source "drivers/pci/controller/mobiveil/Kconfig"
> >  source "drivers/pci/controller/cadence/Kconfig"
> > diff --git a/drivers/pci/controller/Makefile b/drivers/pci/controller/Makefile
> > index 63e3880a3e87..ac902dc4e1a9 100644
> > --- a/drivers/pci/controller/Makefile
> > +++ b/drivers/pci/controller/Makefile
> > @@ -36,6 +36,7 @@ obj-$(CONFIG_VMD) += vmd.o
> >  obj-$(CONFIG_PCIE_BRCMSTB) += pcie-brcmstb.o
> >  obj-$(CONFIG_PCI_LOONGSON) += pci-loongson.o
> >  obj-$(CONFIG_PCIE_HISI_ERR) += pcie-hisi-error.o
> > +obj-$(CONFIG_PCI_MT7621) += pci-mt7621.o
> >  # pcie-hisi.o quirks are needed even without CONFIG_PCIE_DW
> >  obj-y                                += dwc/
> >  obj-y                                += mobiveil/
> > diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/pci/controller/pci-mt7621.c
> > similarity index 100%
> > rename from drivers/staging/mt7621-pci/pci-mt7621.c
> > rename to drivers/pci/controller/pci-mt7621.c
> > diff --git a/drivers/staging/Kconfig b/drivers/staging/Kconfig
> > index b7ae5bdc4eb5..9a21d730ab2b 100644
> > --- a/drivers/staging/Kconfig
> > +++ b/drivers/staging/Kconfig
> > @@ -86,8 +86,6 @@ source "drivers/staging/vc04_services/Kconfig"
> >
> >  source "drivers/staging/pi433/Kconfig"
> >
> > -source "drivers/staging/mt7621-pci/Kconfig"
> > -
> >  source "drivers/staging/mt7621-dma/Kconfig"
> >
> >  source "drivers/staging/ralink-gdma/Kconfig"
> > diff --git a/drivers/staging/Makefile b/drivers/staging/Makefile
> > index 075c979bfe7c..b7b4916761d4 100644
> > --- a/drivers/staging/Makefile
> > +++ b/drivers/staging/Makefile
> > @@ -33,7 +33,6 @@ obj-$(CONFIG_KS7010)                += ks7010/
> >  obj-$(CONFIG_GREYBUS)                += greybus/
> >  obj-$(CONFIG_BCM2835_VCHIQ)  += vc04_services/
> >  obj-$(CONFIG_PI433)          += pi433/
> > -obj-$(CONFIG_PCI_MT7621)     += mt7621-pci/
> >  obj-$(CONFIG_SOC_MT7621)     += mt7621-dma/
> >  obj-$(CONFIG_DMA_RALINK)     += ralink-gdma/
> >  obj-$(CONFIG_SOC_MT7621)     += mt7621-dts/
> > diff --git a/drivers/staging/mt7621-pci/Kconfig b/drivers/staging/mt7621-pci/Kconfig
> > deleted file mode 100644
> > index ce58042f2f21..000000000000
> > --- a/drivers/staging/mt7621-pci/Kconfig
> > +++ /dev/null
> > @@ -1,8 +0,0 @@
> > -# SPDX-License-Identifier: GPL-2.0
> > -config PCI_MT7621
> > -     tristate "MediaTek MT7621 PCI Controller"
> > -     depends on RALINK
> > -     select PCI_DRIVERS_GENERIC
> > -     help
> > -       This selects a driver for the MediaTek MT7621 PCI Controller.
> > -
> > diff --git a/drivers/staging/mt7621-pci/Makefile b/drivers/staging/mt7621-pci/Makefile
> > deleted file mode 100644
> > index f4e651cf7ce3..000000000000
> > --- a/drivers/staging/mt7621-pci/Makefile
> > +++ /dev/null
> > @@ -1,2 +0,0 @@
> > -# SPDX-License-Identifier: GPL-2.0
> > -obj-$(CONFIG_PCI_MT7621)       += pci-mt7621.o
> > diff --git a/drivers/staging/mt7621-pci/TODO b/drivers/staging/mt7621-pci/TODO
> > deleted file mode 100644
> > index d674a9ac85c1..000000000000
> > --- a/drivers/staging/mt7621-pci/TODO
> > +++ /dev/null
> > @@ -1,4 +0,0 @@
> > -
> > -- general code review and cleanup
> > -
> > -Cc: NeilBrown <neil@brown.name>
> > diff --git a/drivers/staging/mt7621-pci/mediatek,mt7621-pci.txt b/drivers/staging/mt7621-pci/mediatek,mt7621-pci.txt
> > deleted file mode 100644
> > index 327a68267309..000000000000
> > --- a/drivers/staging/mt7621-pci/mediatek,mt7621-pci.txt
> > +++ /dev/null
> > @@ -1,104 +0,0 @@
> > -MediaTek MT7621 PCIe controller
> > -
> > -Required properties:
> > -- compatible: "mediatek,mt7621-pci"
> > -- device_type: Must be "pci"
> > -- reg: Base addresses and lengths of the PCIe subsys and root ports.
> > -- bus-range: Range of bus numbers associated with this controller.
> > -- #address-cells: Address representation for root ports (must be 3)
> > -- pinctrl-names : The pin control state names.
> > -- pinctrl-0: The "default" pinctrl state.
> > -- #size-cells: Size representation for root ports (must be 2)
> > -- ranges: Ranges for the PCI memory and I/O regions.
> > -- #interrupt-cells: Must be 1
> > -- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties.
> > -  Please refer to the standard PCI bus binding document for a more detailed
> > -  explanation.
> > -- status: either "disabled" or "okay".
> > -- resets: Must contain an entry for each entry in reset-names.
> > -  See ../reset/reset.txt for details.
> > -- reset-names: Must be "pcie0", "pcie1", "pcieN"... based on the number of
> > -  root ports.
> > -- clocks: Must contain an entry for each entry in clock-names.
> > -  See ../clocks/clock-bindings.txt for details.
> > -- clock-names: Must be "pcie0", "pcie1", "pcieN"... based on the number of
> > -  root ports.
> > -- reset-gpios: GPIO specs for the reset pins.
> > -
> > -In addition, the device tree node must have sub-nodes describing each PCIe port
> > -interface, having the following mandatory properties:
> > -
> > -Required properties:
> > -- reg: Only the first four bytes are used to refer to the correct bus number
> > -      and device number.
> > -- #address-cells: Must be 3
> > -- #size-cells: Must be 2
> > -- ranges: Sub-ranges distributed from the PCIe controller node. An empty
> > -  property is sufficient.
> > -- bus-range: Range of bus numbers associated with this port.
> > -
> > -Example for MT7621:
> > -
> > -     pcie: pcie@1e140000 {
> > -             compatible = "mediatek,mt7621-pci";
> > -        reg = <0x1e140000 0x100    /* host-pci bridge registers */
> > -               0x1e142000 0x100    /* pcie port 0 RC control registers */
> > -               0x1e143000 0x100    /* pcie port 1 RC control registers */
> > -               0x1e144000 0x100>;  /* pcie port 2 RC control registers */
> > -
> > -             #address-cells = <3>;
> > -             #size-cells = <2>;
> > -
> > -             pinctrl-names = "default";
> > -             pinctrl-0 = <&pcie_pins>;
> > -
> > -             device_type = "pci";
> > -
> > -             bus-range = <0 255>;
> > -             ranges = <
> > -                     0x02000000 0 0x00000000 0x60000000 0 0x10000000 /* pci memory */
> > -                     0x01000000 0 0x00000000 0x1e160000 0 0x00010000 /* io space */
> > -             >;
> > -
> > -             #interrupt-cells = <1>;
> > -             interrupt-map-mask = <0xF0000 0 0 1>;
> > -             interrupt-map = <0x10000 0 0 1 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>,
> > -                             <0x20000 0 0 1 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>,
> > -                             <0x30000 0 0 1 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
> > -
> > -             status = "disabled";
> > -
> > -             resets = <&rstctrl 24 &rstctrl 25 &rstctrl 26>;
> > -             reset-names = "pcie0", "pcie1", "pcie2";
> > -             clocks = <&clkctrl 24 &clkctrl 25 &clkctrl 26>;
> > -             clock-names = "pcie0", "pcie1", "pcie2";
> > -
> > -             reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>,
> > -                             <&gpio 8 GPIO_ACTIVE_LOW>,
> > -                             <&gpio 7 GPIO_ACTIVE_LOW>;
> > -
> > -             pcie@0,0 {
> > -                     reg = <0x0000 0 0 0 0>;
> > -                     #address-cells = <3>;
> > -                     #size-cells = <2>;
> > -                     ranges;
> > -                     bus-range = <0x00 0xff>;
> > -             };
> > -
> > -             pcie@1,0 {
> > -                     reg = <0x0800 0 0 0 0>;
> > -                     #address-cells = <3>;
> > -                     #size-cells = <2>;
> > -                     ranges;
> > -                     bus-range = <0x00 0xff>;
> > -             };
> > -
> > -             pcie@2,0 {
> > -                     reg = <0x1000 0 0 0 0>;
> > -                     #address-cells = <3>;
> > -                     #size-cells = <2>;
> > -                     ranges;
> > -                     bus-range = <0x00 0xff>;
> > -             };
> > -     };
> > -
> > --
> > 2.25.1
> >

^ permalink raw reply	[flat|nested] 10+ messages in thread

* Re: [PATCH v2 2/3] PCI: mt7621: Add MediaTek MT7621 PCIe host controller driver
  2021-08-05 10:40     ` Sergio Paracuellos
@ 2021-08-05 10:45       ` Lorenzo Pieralisi
  2021-08-05 10:50         ` Sergio Paracuellos
  0 siblings, 1 reply; 10+ messages in thread
From: Lorenzo Pieralisi @ 2021-08-05 10:45 UTC (permalink / raw)
  To: Sergio Paracuellos
  Cc: linux-pci, open list:MIPS, Thomas Bogendoerfer,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	Matthias Brugger, John Crispin, Bjorn Helgaas, Rob Herring,
	linux-staging, Greg KH, NeilBrown, Ilya Lipnitskiy, linux-kernel,
	Pali Rohár

On Thu, Aug 05, 2021 at 12:40:02PM +0200, Sergio Paracuellos wrote:
> Hi Lorenzo,
> 
> On Thu, Aug 5, 2021 at 12:32 PM Lorenzo Pieralisi
> <lorenzo.pieralisi@arm.com> wrote:
> >
> > On Wed, Jun 09, 2021 at 04:01:58PM +0200, Sergio Paracuellos wrote:
> > > Add driver for the PCIe controller of the MT7621 SoC.
> > >
> > > Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
> > > Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
> > > ---
> > >  arch/mips/ralink/Kconfig                      |   2 +-
> > >  drivers/pci/controller/Kconfig                |   8 ++
> > >  drivers/pci/controller/Makefile               |   1 +
> > >  .../controller}/pci-mt7621.c                  |   0
> > >  drivers/staging/Kconfig                       |   2 -
> > >  drivers/staging/Makefile                      |   1 -
> > >  drivers/staging/mt7621-pci/Kconfig            |   8 --
> > >  drivers/staging/mt7621-pci/Makefile           |   2 -
> > >  drivers/staging/mt7621-pci/TODO               |   4 -
> > >  .../mt7621-pci/mediatek,mt7621-pci.txt        | 104 ------------------
> > >  10 files changed, 10 insertions(+), 122 deletions(-)
> > >  rename drivers/{staging/mt7621-pci => pci/controller}/pci-mt7621.c (100%)
> > >  delete mode 100644 drivers/staging/mt7621-pci/Kconfig
> > >  delete mode 100644 drivers/staging/mt7621-pci/Makefile
> > >  delete mode 100644 drivers/staging/mt7621-pci/TODO
> > >  delete mode 100644 drivers/staging/mt7621-pci/mediatek,mt7621-pci.txt
> > >
> > > diff --git a/arch/mips/ralink/Kconfig b/arch/mips/ralink/Kconfig
> > > index ec4daa63c5e3..461e33d20c9c 100644
> > > --- a/arch/mips/ralink/Kconfig
> > > +++ b/arch/mips/ralink/Kconfig
> > > @@ -56,7 +56,7 @@ choice
> > >               select MIPS_GIC
> > >               select COMMON_CLK
> > >               select CLKSRC_MIPS_GIC
> > > -             select HAVE_PCI if PCI_MT7621
> > > +             select HAVE_PCI
> > >               select SOC_BUS
> > >  endchoice
> > >
> > > diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
> > > index 2f2c8a1729f9..6b006df87884 100644
> > > --- a/drivers/pci/controller/Kconfig
> > > +++ b/drivers/pci/controller/Kconfig
> > > @@ -303,6 +303,14 @@ config PCIE_HISI_ERR
> > >         Say Y here if you want error handling support
> > >         for the PCIe controller's errors on HiSilicon HIP SoCs
> > >
> > > +config PCI_MT7621
> > > +     bool "MediaTek MT7621 PCI Controller"
> > > +     depends on (RALINK && SOC_MT7621) || (MIPS && COMPILE_TEST)
> > > +     select PCI_DRIVERS_GENERIC
> >
> > Can this be selected in arch/mips rather than here ?
> 
> No real problem for me, but I was suggested by Bjorn and Pali to put
> all the driver inside 'drivers/pci/controller'. Do you mean to move
> all to arch/mips or only the Kconfig part?

Only:

select PCI_DRIVERS_GENERIC

given that's an arch/mips internal.

Thanks,
Lorenzo

> 
> Thanks,
>     Sergio Paracuellos
> 
> >
> > Thanks,
> > Lorenzo
> >
> > > +     default SOC_MT7621
> > > +     help
> > > +       This selects a driver for the MediaTek MT7621 PCI Controller.
> > > +
> > >  source "drivers/pci/controller/dwc/Kconfig"
> > >  source "drivers/pci/controller/mobiveil/Kconfig"
> > >  source "drivers/pci/controller/cadence/Kconfig"
> > > diff --git a/drivers/pci/controller/Makefile b/drivers/pci/controller/Makefile
> > > index 63e3880a3e87..ac902dc4e1a9 100644
> > > --- a/drivers/pci/controller/Makefile
> > > +++ b/drivers/pci/controller/Makefile
> > > @@ -36,6 +36,7 @@ obj-$(CONFIG_VMD) += vmd.o
> > >  obj-$(CONFIG_PCIE_BRCMSTB) += pcie-brcmstb.o
> > >  obj-$(CONFIG_PCI_LOONGSON) += pci-loongson.o
> > >  obj-$(CONFIG_PCIE_HISI_ERR) += pcie-hisi-error.o
> > > +obj-$(CONFIG_PCI_MT7621) += pci-mt7621.o
> > >  # pcie-hisi.o quirks are needed even without CONFIG_PCIE_DW
> > >  obj-y                                += dwc/
> > >  obj-y                                += mobiveil/
> > > diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/pci/controller/pci-mt7621.c
> > > similarity index 100%
> > > rename from drivers/staging/mt7621-pci/pci-mt7621.c
> > > rename to drivers/pci/controller/pci-mt7621.c
> > > diff --git a/drivers/staging/Kconfig b/drivers/staging/Kconfig
> > > index b7ae5bdc4eb5..9a21d730ab2b 100644
> > > --- a/drivers/staging/Kconfig
> > > +++ b/drivers/staging/Kconfig
> > > @@ -86,8 +86,6 @@ source "drivers/staging/vc04_services/Kconfig"
> > >
> > >  source "drivers/staging/pi433/Kconfig"
> > >
> > > -source "drivers/staging/mt7621-pci/Kconfig"
> > > -
> > >  source "drivers/staging/mt7621-dma/Kconfig"
> > >
> > >  source "drivers/staging/ralink-gdma/Kconfig"
> > > diff --git a/drivers/staging/Makefile b/drivers/staging/Makefile
> > > index 075c979bfe7c..b7b4916761d4 100644
> > > --- a/drivers/staging/Makefile
> > > +++ b/drivers/staging/Makefile
> > > @@ -33,7 +33,6 @@ obj-$(CONFIG_KS7010)                += ks7010/
> > >  obj-$(CONFIG_GREYBUS)                += greybus/
> > >  obj-$(CONFIG_BCM2835_VCHIQ)  += vc04_services/
> > >  obj-$(CONFIG_PI433)          += pi433/
> > > -obj-$(CONFIG_PCI_MT7621)     += mt7621-pci/
> > >  obj-$(CONFIG_SOC_MT7621)     += mt7621-dma/
> > >  obj-$(CONFIG_DMA_RALINK)     += ralink-gdma/
> > >  obj-$(CONFIG_SOC_MT7621)     += mt7621-dts/
> > > diff --git a/drivers/staging/mt7621-pci/Kconfig b/drivers/staging/mt7621-pci/Kconfig
> > > deleted file mode 100644
> > > index ce58042f2f21..000000000000
> > > --- a/drivers/staging/mt7621-pci/Kconfig
> > > +++ /dev/null
> > > @@ -1,8 +0,0 @@
> > > -# SPDX-License-Identifier: GPL-2.0
> > > -config PCI_MT7621
> > > -     tristate "MediaTek MT7621 PCI Controller"
> > > -     depends on RALINK
> > > -     select PCI_DRIVERS_GENERIC
> > > -     help
> > > -       This selects a driver for the MediaTek MT7621 PCI Controller.
> > > -
> > > diff --git a/drivers/staging/mt7621-pci/Makefile b/drivers/staging/mt7621-pci/Makefile
> > > deleted file mode 100644
> > > index f4e651cf7ce3..000000000000
> > > --- a/drivers/staging/mt7621-pci/Makefile
> > > +++ /dev/null
> > > @@ -1,2 +0,0 @@
> > > -# SPDX-License-Identifier: GPL-2.0
> > > -obj-$(CONFIG_PCI_MT7621)       += pci-mt7621.o
> > > diff --git a/drivers/staging/mt7621-pci/TODO b/drivers/staging/mt7621-pci/TODO
> > > deleted file mode 100644
> > > index d674a9ac85c1..000000000000
> > > --- a/drivers/staging/mt7621-pci/TODO
> > > +++ /dev/null
> > > @@ -1,4 +0,0 @@
> > > -
> > > -- general code review and cleanup
> > > -
> > > -Cc: NeilBrown <neil@brown.name>
> > > diff --git a/drivers/staging/mt7621-pci/mediatek,mt7621-pci.txt b/drivers/staging/mt7621-pci/mediatek,mt7621-pci.txt
> > > deleted file mode 100644
> > > index 327a68267309..000000000000
> > > --- a/drivers/staging/mt7621-pci/mediatek,mt7621-pci.txt
> > > +++ /dev/null
> > > @@ -1,104 +0,0 @@
> > > -MediaTek MT7621 PCIe controller
> > > -
> > > -Required properties:
> > > -- compatible: "mediatek,mt7621-pci"
> > > -- device_type: Must be "pci"
> > > -- reg: Base addresses and lengths of the PCIe subsys and root ports.
> > > -- bus-range: Range of bus numbers associated with this controller.
> > > -- #address-cells: Address representation for root ports (must be 3)
> > > -- pinctrl-names : The pin control state names.
> > > -- pinctrl-0: The "default" pinctrl state.
> > > -- #size-cells: Size representation for root ports (must be 2)
> > > -- ranges: Ranges for the PCI memory and I/O regions.
> > > -- #interrupt-cells: Must be 1
> > > -- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties.
> > > -  Please refer to the standard PCI bus binding document for a more detailed
> > > -  explanation.
> > > -- status: either "disabled" or "okay".
> > > -- resets: Must contain an entry for each entry in reset-names.
> > > -  See ../reset/reset.txt for details.
> > > -- reset-names: Must be "pcie0", "pcie1", "pcieN"... based on the number of
> > > -  root ports.
> > > -- clocks: Must contain an entry for each entry in clock-names.
> > > -  See ../clocks/clock-bindings.txt for details.
> > > -- clock-names: Must be "pcie0", "pcie1", "pcieN"... based on the number of
> > > -  root ports.
> > > -- reset-gpios: GPIO specs for the reset pins.
> > > -
> > > -In addition, the device tree node must have sub-nodes describing each PCIe port
> > > -interface, having the following mandatory properties:
> > > -
> > > -Required properties:
> > > -- reg: Only the first four bytes are used to refer to the correct bus number
> > > -      and device number.
> > > -- #address-cells: Must be 3
> > > -- #size-cells: Must be 2
> > > -- ranges: Sub-ranges distributed from the PCIe controller node. An empty
> > > -  property is sufficient.
> > > -- bus-range: Range of bus numbers associated with this port.
> > > -
> > > -Example for MT7621:
> > > -
> > > -     pcie: pcie@1e140000 {
> > > -             compatible = "mediatek,mt7621-pci";
> > > -        reg = <0x1e140000 0x100    /* host-pci bridge registers */
> > > -               0x1e142000 0x100    /* pcie port 0 RC control registers */
> > > -               0x1e143000 0x100    /* pcie port 1 RC control registers */
> > > -               0x1e144000 0x100>;  /* pcie port 2 RC control registers */
> > > -
> > > -             #address-cells = <3>;
> > > -             #size-cells = <2>;
> > > -
> > > -             pinctrl-names = "default";
> > > -             pinctrl-0 = <&pcie_pins>;
> > > -
> > > -             device_type = "pci";
> > > -
> > > -             bus-range = <0 255>;
> > > -             ranges = <
> > > -                     0x02000000 0 0x00000000 0x60000000 0 0x10000000 /* pci memory */
> > > -                     0x01000000 0 0x00000000 0x1e160000 0 0x00010000 /* io space */
> > > -             >;
> > > -
> > > -             #interrupt-cells = <1>;
> > > -             interrupt-map-mask = <0xF0000 0 0 1>;
> > > -             interrupt-map = <0x10000 0 0 1 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>,
> > > -                             <0x20000 0 0 1 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>,
> > > -                             <0x30000 0 0 1 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
> > > -
> > > -             status = "disabled";
> > > -
> > > -             resets = <&rstctrl 24 &rstctrl 25 &rstctrl 26>;
> > > -             reset-names = "pcie0", "pcie1", "pcie2";
> > > -             clocks = <&clkctrl 24 &clkctrl 25 &clkctrl 26>;
> > > -             clock-names = "pcie0", "pcie1", "pcie2";
> > > -
> > > -             reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>,
> > > -                             <&gpio 8 GPIO_ACTIVE_LOW>,
> > > -                             <&gpio 7 GPIO_ACTIVE_LOW>;
> > > -
> > > -             pcie@0,0 {
> > > -                     reg = <0x0000 0 0 0 0>;
> > > -                     #address-cells = <3>;
> > > -                     #size-cells = <2>;
> > > -                     ranges;
> > > -                     bus-range = <0x00 0xff>;
> > > -             };
> > > -
> > > -             pcie@1,0 {
> > > -                     reg = <0x0800 0 0 0 0>;
> > > -                     #address-cells = <3>;
> > > -                     #size-cells = <2>;
> > > -                     ranges;
> > > -                     bus-range = <0x00 0xff>;
> > > -             };
> > > -
> > > -             pcie@2,0 {
> > > -                     reg = <0x1000 0 0 0 0>;
> > > -                     #address-cells = <3>;
> > > -                     #size-cells = <2>;
> > > -                     ranges;
> > > -                     bus-range = <0x00 0xff>;
> > > -             };
> > > -     };
> > > -
> > > --
> > > 2.25.1
> > >

^ permalink raw reply	[flat|nested] 10+ messages in thread

* Re: [PATCH v2 2/3] PCI: mt7621: Add MediaTek MT7621 PCIe host controller driver
  2021-08-05 10:45       ` Lorenzo Pieralisi
@ 2021-08-05 10:50         ` Sergio Paracuellos
  0 siblings, 0 replies; 10+ messages in thread
From: Sergio Paracuellos @ 2021-08-05 10:50 UTC (permalink / raw)
  To: Lorenzo Pieralisi
  Cc: linux-pci, open list:MIPS, Thomas Bogendoerfer,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	Matthias Brugger, John Crispin, Bjorn Helgaas, Rob Herring,
	linux-staging, Greg KH, NeilBrown, Ilya Lipnitskiy, linux-kernel,
	Pali Rohár

On Thu, Aug 5, 2021 at 12:45 PM Lorenzo Pieralisi
<lorenzo.pieralisi@arm.com> wrote:
>
> On Thu, Aug 05, 2021 at 12:40:02PM +0200, Sergio Paracuellos wrote:
> > Hi Lorenzo,
> >
> > On Thu, Aug 5, 2021 at 12:32 PM Lorenzo Pieralisi
> > <lorenzo.pieralisi@arm.com> wrote:
> > >
> > > On Wed, Jun 09, 2021 at 04:01:58PM +0200, Sergio Paracuellos wrote:
> > > > Add driver for the PCIe controller of the MT7621 SoC.
> > > >
> > > > Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
> > > > Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
> > > > ---
> > > >  arch/mips/ralink/Kconfig                      |   2 +-
> > > >  drivers/pci/controller/Kconfig                |   8 ++
> > > >  drivers/pci/controller/Makefile               |   1 +
> > > >  .../controller}/pci-mt7621.c                  |   0
> > > >  drivers/staging/Kconfig                       |   2 -
> > > >  drivers/staging/Makefile                      |   1 -
> > > >  drivers/staging/mt7621-pci/Kconfig            |   8 --
> > > >  drivers/staging/mt7621-pci/Makefile           |   2 -
> > > >  drivers/staging/mt7621-pci/TODO               |   4 -
> > > >  .../mt7621-pci/mediatek,mt7621-pci.txt        | 104 ------------------
> > > >  10 files changed, 10 insertions(+), 122 deletions(-)
> > > >  rename drivers/{staging/mt7621-pci => pci/controller}/pci-mt7621.c (100%)
> > > >  delete mode 100644 drivers/staging/mt7621-pci/Kconfig
> > > >  delete mode 100644 drivers/staging/mt7621-pci/Makefile
> > > >  delete mode 100644 drivers/staging/mt7621-pci/TODO
> > > >  delete mode 100644 drivers/staging/mt7621-pci/mediatek,mt7621-pci.txt
> > > >
> > > > diff --git a/arch/mips/ralink/Kconfig b/arch/mips/ralink/Kconfig
> > > > index ec4daa63c5e3..461e33d20c9c 100644
> > > > --- a/arch/mips/ralink/Kconfig
> > > > +++ b/arch/mips/ralink/Kconfig
> > > > @@ -56,7 +56,7 @@ choice
> > > >               select MIPS_GIC
> > > >               select COMMON_CLK
> > > >               select CLKSRC_MIPS_GIC
> > > > -             select HAVE_PCI if PCI_MT7621
> > > > +             select HAVE_PCI
> > > >               select SOC_BUS
> > > >  endchoice
> > > >
> > > > diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
> > > > index 2f2c8a1729f9..6b006df87884 100644
> > > > --- a/drivers/pci/controller/Kconfig
> > > > +++ b/drivers/pci/controller/Kconfig
> > > > @@ -303,6 +303,14 @@ config PCIE_HISI_ERR
> > > >         Say Y here if you want error handling support
> > > >         for the PCIe controller's errors on HiSilicon HIP SoCs
> > > >
> > > > +config PCI_MT7621
> > > > +     bool "MediaTek MT7621 PCI Controller"
> > > > +     depends on (RALINK && SOC_MT7621) || (MIPS && COMPILE_TEST)
> > > > +     select PCI_DRIVERS_GENERIC
> > >
> > > Can this be selected in arch/mips rather than here ?
> >
> > No real problem for me, but I was suggested by Bjorn and Pali to put
> > all the driver inside 'drivers/pci/controller'. Do you mean to move
> > all to arch/mips or only the Kconfig part?
>
> Only:
>
> select PCI_DRIVERS_GENERIC
>
> given that's an arch/mips internal.
>

Ah, ok. I misread your comment, sorry. I will put it there and send v3.

Thanks,
    Sergio Paracuellos

> Thanks,
> Lorenzo
>
> >
> > Thanks,
> >     Sergio Paracuellos
> >
> > >
> > > Thanks,
> > > Lorenzo
> > >
> > > > +     default SOC_MT7621
> > > > +     help
> > > > +       This selects a driver for the MediaTek MT7621 PCI Controller.
> > > > +
> > > >  source "drivers/pci/controller/dwc/Kconfig"
> > > >  source "drivers/pci/controller/mobiveil/Kconfig"
> > > >  source "drivers/pci/controller/cadence/Kconfig"
> > > > diff --git a/drivers/pci/controller/Makefile b/drivers/pci/controller/Makefile
> > > > index 63e3880a3e87..ac902dc4e1a9 100644
> > > > --- a/drivers/pci/controller/Makefile
> > > > +++ b/drivers/pci/controller/Makefile
> > > > @@ -36,6 +36,7 @@ obj-$(CONFIG_VMD) += vmd.o
> > > >  obj-$(CONFIG_PCIE_BRCMSTB) += pcie-brcmstb.o
> > > >  obj-$(CONFIG_PCI_LOONGSON) += pci-loongson.o
> > > >  obj-$(CONFIG_PCIE_HISI_ERR) += pcie-hisi-error.o
> > > > +obj-$(CONFIG_PCI_MT7621) += pci-mt7621.o
> > > >  # pcie-hisi.o quirks are needed even without CONFIG_PCIE_DW
> > > >  obj-y                                += dwc/
> > > >  obj-y                                += mobiveil/
> > > > diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/pci/controller/pci-mt7621.c
> > > > similarity index 100%
> > > > rename from drivers/staging/mt7621-pci/pci-mt7621.c
> > > > rename to drivers/pci/controller/pci-mt7621.c
> > > > diff --git a/drivers/staging/Kconfig b/drivers/staging/Kconfig
> > > > index b7ae5bdc4eb5..9a21d730ab2b 100644
> > > > --- a/drivers/staging/Kconfig
> > > > +++ b/drivers/staging/Kconfig
> > > > @@ -86,8 +86,6 @@ source "drivers/staging/vc04_services/Kconfig"
> > > >
> > > >  source "drivers/staging/pi433/Kconfig"
> > > >
> > > > -source "drivers/staging/mt7621-pci/Kconfig"
> > > > -
> > > >  source "drivers/staging/mt7621-dma/Kconfig"
> > > >
> > > >  source "drivers/staging/ralink-gdma/Kconfig"
> > > > diff --git a/drivers/staging/Makefile b/drivers/staging/Makefile
> > > > index 075c979bfe7c..b7b4916761d4 100644
> > > > --- a/drivers/staging/Makefile
> > > > +++ b/drivers/staging/Makefile
> > > > @@ -33,7 +33,6 @@ obj-$(CONFIG_KS7010)                += ks7010/
> > > >  obj-$(CONFIG_GREYBUS)                += greybus/
> > > >  obj-$(CONFIG_BCM2835_VCHIQ)  += vc04_services/
> > > >  obj-$(CONFIG_PI433)          += pi433/
> > > > -obj-$(CONFIG_PCI_MT7621)     += mt7621-pci/
> > > >  obj-$(CONFIG_SOC_MT7621)     += mt7621-dma/
> > > >  obj-$(CONFIG_DMA_RALINK)     += ralink-gdma/
> > > >  obj-$(CONFIG_SOC_MT7621)     += mt7621-dts/
> > > > diff --git a/drivers/staging/mt7621-pci/Kconfig b/drivers/staging/mt7621-pci/Kconfig
> > > > deleted file mode 100644
> > > > index ce58042f2f21..000000000000
> > > > --- a/drivers/staging/mt7621-pci/Kconfig
> > > > +++ /dev/null
> > > > @@ -1,8 +0,0 @@
> > > > -# SPDX-License-Identifier: GPL-2.0
> > > > -config PCI_MT7621
> > > > -     tristate "MediaTek MT7621 PCI Controller"
> > > > -     depends on RALINK
> > > > -     select PCI_DRIVERS_GENERIC
> > > > -     help
> > > > -       This selects a driver for the MediaTek MT7621 PCI Controller.
> > > > -
> > > > diff --git a/drivers/staging/mt7621-pci/Makefile b/drivers/staging/mt7621-pci/Makefile
> > > > deleted file mode 100644
> > > > index f4e651cf7ce3..000000000000
> > > > --- a/drivers/staging/mt7621-pci/Makefile
> > > > +++ /dev/null
> > > > @@ -1,2 +0,0 @@
> > > > -# SPDX-License-Identifier: GPL-2.0
> > > > -obj-$(CONFIG_PCI_MT7621)       += pci-mt7621.o
> > > > diff --git a/drivers/staging/mt7621-pci/TODO b/drivers/staging/mt7621-pci/TODO
> > > > deleted file mode 100644
> > > > index d674a9ac85c1..000000000000
> > > > --- a/drivers/staging/mt7621-pci/TODO
> > > > +++ /dev/null
> > > > @@ -1,4 +0,0 @@
> > > > -
> > > > -- general code review and cleanup
> > > > -
> > > > -Cc: NeilBrown <neil@brown.name>
> > > > diff --git a/drivers/staging/mt7621-pci/mediatek,mt7621-pci.txt b/drivers/staging/mt7621-pci/mediatek,mt7621-pci.txt
> > > > deleted file mode 100644
> > > > index 327a68267309..000000000000
> > > > --- a/drivers/staging/mt7621-pci/mediatek,mt7621-pci.txt
> > > > +++ /dev/null
> > > > @@ -1,104 +0,0 @@
> > > > -MediaTek MT7621 PCIe controller
> > > > -
> > > > -Required properties:
> > > > -- compatible: "mediatek,mt7621-pci"
> > > > -- device_type: Must be "pci"
> > > > -- reg: Base addresses and lengths of the PCIe subsys and root ports.
> > > > -- bus-range: Range of bus numbers associated with this controller.
> > > > -- #address-cells: Address representation for root ports (must be 3)
> > > > -- pinctrl-names : The pin control state names.
> > > > -- pinctrl-0: The "default" pinctrl state.
> > > > -- #size-cells: Size representation for root ports (must be 2)
> > > > -- ranges: Ranges for the PCI memory and I/O regions.
> > > > -- #interrupt-cells: Must be 1
> > > > -- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties.
> > > > -  Please refer to the standard PCI bus binding document for a more detailed
> > > > -  explanation.
> > > > -- status: either "disabled" or "okay".
> > > > -- resets: Must contain an entry for each entry in reset-names.
> > > > -  See ../reset/reset.txt for details.
> > > > -- reset-names: Must be "pcie0", "pcie1", "pcieN"... based on the number of
> > > > -  root ports.
> > > > -- clocks: Must contain an entry for each entry in clock-names.
> > > > -  See ../clocks/clock-bindings.txt for details.
> > > > -- clock-names: Must be "pcie0", "pcie1", "pcieN"... based on the number of
> > > > -  root ports.
> > > > -- reset-gpios: GPIO specs for the reset pins.
> > > > -
> > > > -In addition, the device tree node must have sub-nodes describing each PCIe port
> > > > -interface, having the following mandatory properties:
> > > > -
> > > > -Required properties:
> > > > -- reg: Only the first four bytes are used to refer to the correct bus number
> > > > -      and device number.
> > > > -- #address-cells: Must be 3
> > > > -- #size-cells: Must be 2
> > > > -- ranges: Sub-ranges distributed from the PCIe controller node. An empty
> > > > -  property is sufficient.
> > > > -- bus-range: Range of bus numbers associated with this port.
> > > > -
> > > > -Example for MT7621:
> > > > -
> > > > -     pcie: pcie@1e140000 {
> > > > -             compatible = "mediatek,mt7621-pci";
> > > > -        reg = <0x1e140000 0x100    /* host-pci bridge registers */
> > > > -               0x1e142000 0x100    /* pcie port 0 RC control registers */
> > > > -               0x1e143000 0x100    /* pcie port 1 RC control registers */
> > > > -               0x1e144000 0x100>;  /* pcie port 2 RC control registers */
> > > > -
> > > > -             #address-cells = <3>;
> > > > -             #size-cells = <2>;
> > > > -
> > > > -             pinctrl-names = "default";
> > > > -             pinctrl-0 = <&pcie_pins>;
> > > > -
> > > > -             device_type = "pci";
> > > > -
> > > > -             bus-range = <0 255>;
> > > > -             ranges = <
> > > > -                     0x02000000 0 0x00000000 0x60000000 0 0x10000000 /* pci memory */
> > > > -                     0x01000000 0 0x00000000 0x1e160000 0 0x00010000 /* io space */
> > > > -             >;
> > > > -
> > > > -             #interrupt-cells = <1>;
> > > > -             interrupt-map-mask = <0xF0000 0 0 1>;
> > > > -             interrupt-map = <0x10000 0 0 1 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>,
> > > > -                             <0x20000 0 0 1 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>,
> > > > -                             <0x30000 0 0 1 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
> > > > -
> > > > -             status = "disabled";
> > > > -
> > > > -             resets = <&rstctrl 24 &rstctrl 25 &rstctrl 26>;
> > > > -             reset-names = "pcie0", "pcie1", "pcie2";
> > > > -             clocks = <&clkctrl 24 &clkctrl 25 &clkctrl 26>;
> > > > -             clock-names = "pcie0", "pcie1", "pcie2";
> > > > -
> > > > -             reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>,
> > > > -                             <&gpio 8 GPIO_ACTIVE_LOW>,
> > > > -                             <&gpio 7 GPIO_ACTIVE_LOW>;
> > > > -
> > > > -             pcie@0,0 {
> > > > -                     reg = <0x0000 0 0 0 0>;
> > > > -                     #address-cells = <3>;
> > > > -                     #size-cells = <2>;
> > > > -                     ranges;
> > > > -                     bus-range = <0x00 0xff>;
> > > > -             };
> > > > -
> > > > -             pcie@1,0 {
> > > > -                     reg = <0x0800 0 0 0 0>;
> > > > -                     #address-cells = <3>;
> > > > -                     #size-cells = <2>;
> > > > -                     ranges;
> > > > -                     bus-range = <0x00 0xff>;
> > > > -             };
> > > > -
> > > > -             pcie@2,0 {
> > > > -                     reg = <0x1000 0 0 0 0>;
> > > > -                     #address-cells = <3>;
> > > > -                     #size-cells = <2>;
> > > > -                     ranges;
> > > > -                     bus-range = <0x00 0xff>;
> > > > -             };
> > > > -     };
> > > > -
> > > > --
> > > > 2.25.1
> > > >

^ permalink raw reply	[flat|nested] 10+ messages in thread

end of thread, other threads:[~2021-08-05 10:50 UTC | newest]

Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-06-09 14:01 [PATCH v2 0/3] PCI: mt7621: Add MediaTek MT7621 PCIe host controller driver Sergio Paracuellos
2021-06-09 14:01 ` [PATCH v2 1/3] dt-bindings: mt7621-pci: PCIe binding documentation for MT7621 SoCs Sergio Paracuellos
2021-06-18 21:08   ` Rob Herring
2021-06-09 14:01 ` [PATCH v2 2/3] PCI: mt7621: Add MediaTek MT7621 PCIe host controller driver Sergio Paracuellos
2021-08-05 10:32   ` Lorenzo Pieralisi
2021-08-05 10:40     ` Sergio Paracuellos
2021-08-05 10:45       ` Lorenzo Pieralisi
2021-08-05 10:50         ` Sergio Paracuellos
2021-06-09 14:01 ` [PATCH v2 3/3] MAINTAINERS: add myself as maintainer of the MT7621 PCI " Sergio Paracuellos
2021-06-17  6:00 ` [PATCH v2 0/3] PCI: mt7621: Add MediaTek MT7621 PCIe host " Sergio Paracuellos

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