From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
To: Stephen Boyd <sboyd@kernel.org>
Cc: Michael Turquette <mturquette@baylibre.com>,
Rob Herring <robh+dt@kernel.org>, John Crispin <john@phrozen.org>,
Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
Greg KH <gregkh@linuxfoundation.org>,
Chuanhong Guo <gch981213@gmail.com>,
Weijie Gao <hackpascal@gmail.com>,
COMMON CLK FRAMEWORK <linux-clk@vger.kernel.org>,
linux-kernel <linux-kernel@vger.kernel.org>,
"open list:MIPS <linux-mips@vger.kernel.org>,
open list:STAGING SUBSYSTEM <devel@driverdev.osuosl.org>,
NeilBrown <neil@brown.name>,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
<devicetree@vger.kernel.org>
Subject: Re: [PATCH v4 2/6] dt: bindings: add mt7621-clk device tree binding documentation
Date: Thu, 17 Dec 2020 11:38:37 +0100 [thread overview]
Message-ID: <CAMhs-H9SiZ90NYCGL+3ad9UR7CDUiA1gb99ZcfHp10=SZtVPpg@mail.gmail.com> (raw)
In-Reply-To: <160820116913.1580929.15821601182796836787@swboyd.mtv.corp.google.com>
On Thu, Dec 17, 2020 at 11:32 AM Stephen Boyd <sboyd@kernel.org> wrote:
>
> Quoting Sergio Paracuellos (2020-12-17 02:14:10)
> > On Thu, Dec 17, 2020 at 11:07 AM Stephen Boyd <sboyd@kernel.org> wrote:
> > >
> > > Quoting Sergio Paracuellos (2020-12-17 02:01:39)
> > > >
> > > > On Thu, Dec 17, 2020 at 9:58 AM Stephen Boyd <sboyd@kernel.org> wrote:
> > > > >
> > > > > Quoting Sergio Paracuellos (2020-11-22 01:55:52)
> > > > >
> > > > > > diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml
> > > > > > new file mode 100644
> > > > > > index 000000000000..6aca4c1a4a46
> > > > > > --- /dev/null
> > > > > > +++ b/Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml
> > > > >
> > > > > > + compatible = "mediatek,mt7621-sysc", "syscon";
> > > > > > + reg = <0x0 0x100>;
> > > > > > +
> > > > > > + pll {
> > > > >
> > > > > clock-controller? Why can't the parent device be the clk provider and
> > > > > have #clock-cells?
> > > > >
> > > >
> > > > I don't get your point, sorry. Can you please explain this a bit more
> > > > or point to me to an example to understand the real meaning of this?
> > >
> > > It looks like this is a made up child node of syscon so that a driver
> > > can probe in the kernel. It would be more DT friendly to create a
> > > platform device from the parent node's driver, or just register the clks
> > > with the framework directly in that driver.
> >
> > We cannot create a platform device because we need clocks available in
> > 'plat_time_init' before setting up the timer for the GIC.
> > The only way I see to avoid this syscon and having this as a child
> > node is to use architecture operations in
> > 'arch/mips/include/asm/mach-ralink/ralink_regs.h'
> > instead of getting a phandle using the regmap is being currently used...
>
> Can that be done with
>
> CLK_OF_DECLARE_DRIVER("mediatek,mt7621-sysc", my_timer_clk_init)
>
> ? Is the syscon used anywhere besides by the clk driver?
Yes, for example all the gates use them to access SYSC_REG_CLKCFG1 in
all of their 'mt7621_gate_ops' and also in all 'recalc_rate' functions
where SYSC_REG_SYSTEM_CONFIG0, is readed.
next prev parent reply other threads:[~2020-12-17 10:39 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-22 9:55 [PATCH v4 0/6] MIPS: ralink: add CPU clock detection and clock driver for MT7621 Sergio Paracuellos
2020-11-22 9:55 ` [PATCH v4 1/6] dt-bindings: clock: add dt binding header for mt7621 clocks Sergio Paracuellos
2020-11-22 9:55 ` [PATCH v4 2/6] dt: bindings: add mt7621-clk device tree binding documentation Sergio Paracuellos
2020-12-17 8:58 ` Stephen Boyd
2020-12-17 10:01 ` Sergio Paracuellos
[not found] ` <160819962346.1580929.2348154780751858972@swboyd.mtv.corp.google.com>
2020-12-17 10:14 ` Sergio Paracuellos
2020-12-17 10:32 ` Stephen Boyd
2020-12-17 10:38 ` Sergio Paracuellos [this message]
2020-12-17 10:50 ` Stephen Boyd
2020-12-17 10:54 ` Sergio Paracuellos
2020-12-17 15:04 ` Rob Herring
2020-12-17 15:12 ` Sergio Paracuellos
2020-11-22 9:55 ` [PATCH v4 3/6] clk: ralink: add clock driver for mt7621 SoC Sergio Paracuellos
2020-12-17 9:09 ` Stephen Boyd
2020-12-17 9:54 ` Sergio Paracuellos
[not found] ` <160819993289.1580929.17666667936736079931@swboyd.mtv.corp.google.com>
2020-12-17 10:21 ` Sergio Paracuellos
2020-11-22 9:55 ` [PATCH v4 4/6] staging: mt7621-dts: make use of new 'mt7621-clk' Sergio Paracuellos
2020-11-22 9:55 ` [PATCH v4 5/6] staging: mt7621-dts: use valid vendor 'mediatek' instead of invalid 'mtk' Sergio Paracuellos
2020-11-22 9:55 ` [PATCH v4 6/6] MAINTAINERS: add MT7621 CLOCK maintainer Sergio Paracuellos
2020-12-10 6:55 ` [PATCH v4 0/6] MIPS: ralink: add CPU clock detection and clock driver for MT7621 Sergio Paracuellos
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to='CAMhs-H9SiZ90NYCGL+3ad9UR7CDUiA1gb99ZcfHp10=SZtVPpg@mail.gmail.com' \
--to=sergio.paracuellos@gmail.com \
--cc=devicetree@vger.kernel.org \
--cc=gch981213@gmail.com \
--cc=gregkh@linuxfoundation.org \
--cc=hackpascal@gmail.com \
--cc=john@phrozen.org \
--cc=linux-clk@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=mturquette@baylibre.com \
--cc=robh+dt@kernel.org \
--cc=sboyd@kernel.org \
--cc=tsbogend@alpha.franken.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).