From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.7 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C021DC432C0 for ; Mon, 18 Nov 2019 09:23:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 90CDA2073A for ; Mon, 18 Nov 2019 09:23:02 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20150623.gappssmtp.com header.i=@baylibre-com.20150623.gappssmtp.com header.b="xkAD0lAA" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726940AbfKRJXB (ORCPT ); Mon, 18 Nov 2019 04:23:01 -0500 Received: from mail-ot1-f66.google.com ([209.85.210.66]:37461 "EHLO mail-ot1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726614AbfKRJXA (ORCPT ); Mon, 18 Nov 2019 04:23:00 -0500 Received: by mail-ot1-f66.google.com with SMTP id d5so13889180otp.4 for ; Mon, 18 Nov 2019 01:22:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=pFR3llPqLc9xR1rrhErYhQ9Np0pKks1TZnUYHHrrRUA=; b=xkAD0lAA56gY4bQ9ijcGMcEwSp2xt3Cl4rQTLy1jbTkDKHLd06l1Vf+9asPzk9f5y9 qhYeCfoGuAy/zCGuCkfoQzT4HcIrC2VuP9yL2rbPP7vp/G2/VuqrqbMBkty0d+dUPvGL Of6gq7BsBPGf2L3B/79FWDnyPUKxX9QYoTcnO/ZmaYPMw4wcparF/NRZaaxDsc50vJ2p FEfsm/xveCH6I8a669jHCzNtCTz4+mQVnP2lNoDbCJcvn75sHcnUW1KtaVw2cbVMEjvj +or6nEgar+TUUTj41/Fv5fw4+bQmG5pYK3R3gBMzYvNx8M1sbfDaEfos4Coeo4ps1jcc lqCQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=pFR3llPqLc9xR1rrhErYhQ9Np0pKks1TZnUYHHrrRUA=; b=LdASj5/QKilBs6Lqg5uaueL4rlaP/D5S22RuvRmeXpQfACZAkOm7+7OZOXMSMODoRu NVr31MKHa7TMqy7MEa2/1FHZnzCqcVXFnbmcyJADF6NAxkOViena8Z1egl77T3GANNyq rVlXaj0rQ2gGsa91XivIAswAQZvUoD0m2oXl3CHC4GXvtUkWsZdFOQWKcdrKYZf4wR0t SFHQgAHYOgwBMaftB67wBRg3uW1iZ7odHP4YQVmkjtYRDc+2ec6eOyFxvhpK5ZWH/u9M 8jFXkNQJ0UkcSpfagv3W3xE6Pbv4fx56A69JW0dWgcceXwWPuXux13fdH1c7EPv+UOdN Bnsw== X-Gm-Message-State: APjAAAV6IenbO3MCD2UddMepfbsCLOimbxBItkze98UrywxKPc83jXnv ciOqF2TOwr6YpO2ce67dWeHpGRwDxAJ+T0ZvwwjI2w== X-Google-Smtp-Source: APXvYqyRoHKVrD1n4Cgd2I6KuFKGN+l5TEEMBuB1e1/s+Se/6WFkJqKeypIw9NLQvd2TOZfc864qCstM5dnQvWHwiLE= X-Received: by 2002:a9d:68d4:: with SMTP id i20mr9552898oto.194.1574068977604; Mon, 18 Nov 2019 01:22:57 -0800 (PST) MIME-Version: 1.0 References: <41bf40586bb8f725dc8401696856ecd4a75df748.1574059625.git.matti.vaittinen@fi.rohmeurope.com> In-Reply-To: <41bf40586bb8f725dc8401696856ecd4a75df748.1574059625.git.matti.vaittinen@fi.rohmeurope.com> From: Bartosz Golaszewski Date: Mon, 18 Nov 2019 10:22:46 +0100 Message-ID: Subject: Re: [PATCH v5 14/16] gpio: bd71828: Initial support for ROHM BD71828 PMIC GPIOs To: Matti Vaittinen Cc: Matti Vaittinen , Lee Jones , Jacek Anaszewski , Pavel Machek , Dan Murphy , Rob Herring , Mark Rutland , Liam Girdwood , Mark Brown , Jonathan Corbet , Michael Turquette , Stephen Boyd , Linus Walleij , Alessandro Zummo , Alexandre Belloni , Mauro Carvalho Chehab , Jeff Kirsher , Wolfram Sang , Marek Szyprowski , Heiner Kallweit , Nicholas Mc Guire , Phil Edworthy , Linux LED Subsystem , linux-devicetree , LKML , linux-doc , linux-clk , linux-gpio , linux-rtc@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org pon., 18 lis 2019 o 08:01 Matti Vaittinen napisa=C5=82(a): > > ROHM BD71828 PMIC contains 4 pins which can be configured by OTP > to be used for general purposes. First 3 can be used as outputs > and 4.th pin can be used as input. Allow them to be controlled > via GPIO framework. > > The driver assumes all of the pins are configured as GPIOs and > trusts that the reserved pins in other OTP configurations are > excluded from control using "gpio-reserved-ranges" device tree > property (or left untouched by GPIO users). > > Typical use for 4.th pin (input) is to use it as HALL sensor > input so that this pin state is toggled when HALL sensor detects > LID position change (from close to open or open to close). PMIC > HW implements some extra logic which allows PMIC to power-up the > system when this pin is toggled. Please see the data sheet for > details of GPIO options which can be selected by OTP settings. > > Signed-off-by: Matti Vaittinen > --- > > No changes from v4 > > drivers/gpio/Kconfig | 12 +++ > drivers/gpio/Makefile | 1 + > drivers/gpio/gpio-bd71828.c | 159 ++++++++++++++++++++++++++++++++++++ > 3 files changed, 172 insertions(+) > create mode 100644 drivers/gpio/gpio-bd71828.c > > diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig > index 38e096e6925f..b4089096f7f2 100644 > --- a/drivers/gpio/Kconfig > +++ b/drivers/gpio/Kconfig > @@ -994,6 +994,18 @@ config GPIO_BD70528 > This driver can also be built as a module. If so, the module > will be called gpio-bd70528. > > +config GPIO_BD71828 > + tristate "ROHM BD71828 GPIO support" > + depends on MFD_ROHM_BD71828 > + help > + Support for GPIOs on ROHM BD71828 PMIC. There are three GPIOs > + available on the ROHM PMIC in total. The GPIOs are limited to > + outputs only and pins must be configured to GPIO outputs by > + OTP. Enable this only if you want to use these pins as outputs. > + > + This driver can also be built as a module. If so, the module > + will be called gpio-bd71828. > + > config GPIO_BD9571MWV > tristate "ROHM BD9571 GPIO support" > depends on MFD_BD9571MWV > diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile > index d2fd19c15bae..034b38996579 100644 > --- a/drivers/gpio/Makefile > +++ b/drivers/gpio/Makefile > @@ -35,6 +35,7 @@ obj-$(CONFIG_GPIO_ASPEED) +=3D gpio-aspeed.= o > obj-$(CONFIG_GPIO_ATH79) +=3D gpio-ath79.o > obj-$(CONFIG_GPIO_BCM_KONA) +=3D gpio-bcm-kona.o > obj-$(CONFIG_GPIO_BD70528) +=3D gpio-bd70528.o > +obj-$(CONFIG_GPIO_BD71828) +=3D gpio-bd71828.o > obj-$(CONFIG_GPIO_BD9571MWV) +=3D gpio-bd9571mwv.o > obj-$(CONFIG_GPIO_BRCMSTB) +=3D gpio-brcmstb.o > obj-$(CONFIG_GPIO_BT8XX) +=3D gpio-bt8xx.o > diff --git a/drivers/gpio/gpio-bd71828.c b/drivers/gpio/gpio-bd71828.c > new file mode 100644 > index 000000000000..04aade9e0a4d > --- /dev/null > +++ b/drivers/gpio/gpio-bd71828.c > @@ -0,0 +1,159 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +// Copyright (C) 2018 ROHM Semiconductors > + > +#include > +#include > +#include > +#include > +#include > + > +#define GPIO_OUT_REG(off) (BD71828_REG_GPIO_CTRL1 + (off)) > +#define HALL_GPIO_OFFSET 3 > + > +/* > + * These defines can be removed when > + * "gpio: Add definition for GPIO direction" > + * (9208b1e77d6e8e9776f34f46ef4079ecac9c3c25 in GPIO tree) gets merged, > + */ > +#ifndef GPIO_LINE_DIRECTION_IN > + #define GPIO_LINE_DIRECTION_IN 1 > + #define GPIO_LINE_DIRECTION_OUT 0 > +#endif > + > +struct bd71828_gpio { > + struct rohm_regmap_dev chip; > + struct gpio_chip gpio; > +}; > + > +static void bd71828_gpio_set(struct gpio_chip *chip, unsigned int offset= , > + int value) > +{ > + int ret; > + struct bd71828_gpio *bdgpio =3D gpiochip_get_data(chip); > + u8 val =3D (value) ? BD71828_GPIO_OUT_HI : BD71828_GPIO_OUT_LO; > + > + /* > + * The HALL input pin can only be used as input. If this is the p= in > + * we are dealing with - then we are done > + */ > + if (offset =3D=3D HALL_GPIO_OFFSET) > + return; > + > + ret =3D regmap_update_bits(bdgpio->chip.regmap, GPIO_OUT_REG(offs= et), > + BD71828_GPIO_OUT_MASK, val); > + if (ret) > + dev_err(bdgpio->chip.dev, "Could not set gpio to %d\n", v= alue); > +} > + > +static int bd71828_gpio_get(struct gpio_chip *chip, unsigned int offset) > +{ > + int ret; > + unsigned int val; > + struct bd71828_gpio *bdgpio =3D gpiochip_get_data(chip); > + > + if (offset =3D=3D HALL_GPIO_OFFSET) > + ret =3D regmap_read(bdgpio->chip.regmap, BD71828_REG_IO_S= TAT, > + &val); > + else > + ret =3D regmap_read(bdgpio->chip.regmap, GPIO_OUT_REG(off= set), > + &val); > + if (!ret) > + ret =3D (val & BD71828_GPIO_OUT_MASK); > + > + return ret; > +} > + > +static int bd71828_gpio_set_config(struct gpio_chip *chip, unsigned int = offset, > + unsigned long config) > +{ > + struct bd71828_gpio *bdgpio =3D gpiochip_get_data(chip); > + > + if (offset =3D=3D HALL_GPIO_OFFSET) > + return -ENOTSUPP; > + > + switch (pinconf_to_config_param(config)) { > + case PIN_CONFIG_DRIVE_OPEN_DRAIN: > + return regmap_update_bits(bdgpio->chip.regmap, > + GPIO_OUT_REG(offset), > + BD71828_GPIO_DRIVE_MASK, > + BD71828_GPIO_OPEN_DRAIN); > + case PIN_CONFIG_DRIVE_PUSH_PULL: > + return regmap_update_bits(bdgpio->chip.regmap, > + GPIO_OUT_REG(offset), > + BD71828_GPIO_DRIVE_MASK, > + BD71828_GPIO_PUSH_PULL); > + default: > + break; > + } > + return -ENOTSUPP; > +} > + > +static int bd71828_get_direction(struct gpio_chip *chip, unsigned int of= fset) > +{ > + /* > + * Pin usage is selected by OTP data. We can't read it runtime. H= ence > + * we trust that if the pin is not excluded by "gpio-reserved-ran= ges" > + * the OTP configuration is set to OUT. (Other pins but HALL inpu= t pin > + * on BD71828 can't really be used for general purpose input - in= put > + * states are used for specific cases like regulator control or > + * PMIC_ON_REQ. > + */ > + if (offset =3D=3D HALL_GPIO_OFFSET) > + return GPIO_LINE_DIRECTION_IN; > + > + return GPIO_LINE_DIRECTION_OUT; > +} > + > +static int bd71828_probe(struct platform_device *pdev) > +{ > + struct bd71828_gpio *bdgpio; > + struct rohm_regmap_dev *bd71828; > + > + bd71828 =3D dev_get_drvdata(pdev->dev.parent); > + if (!bd71828) { > + dev_err(&pdev->dev, "No MFD driver data\n"); > + return -EINVAL; > + } > + > + bdgpio =3D devm_kzalloc(&pdev->dev, sizeof(*bdgpio), > + GFP_KERNEL); > + if (!bdgpio) > + return -ENOMEM; > + > + bdgpio->chip.dev =3D &pdev->dev; > + bdgpio->gpio.parent =3D pdev->dev.parent; > + bdgpio->gpio.label =3D "bd71828-gpio"; > + bdgpio->gpio.owner =3D THIS_MODULE; > + bdgpio->gpio.get_direction =3D bd71828_get_direction; > + bdgpio->gpio.set_config =3D bd71828_gpio_set_config; > + bdgpio->gpio.can_sleep =3D true; > + bdgpio->gpio.get =3D bd71828_gpio_get; > + bdgpio->gpio.set =3D bd71828_gpio_set; > + bdgpio->gpio.base =3D -1; > + > + /* > + * See if we need some implementation to mark some PINs as > + * not controllable based on DT info or if core can handle > + * "gpio-reserved-ranges" and exclude them from control > + */ > + bdgpio->gpio.ngpio =3D 4; > + bdgpio->gpio.of_node =3D pdev->dev.parent->of_node; > + bdgpio->chip.regmap =3D bd71828->regmap; > + > + return devm_gpiochip_add_data(&pdev->dev, &bdgpio->gpio, > + bdgpio); > +} > + > +static struct platform_driver bd71828_gpio =3D { > + .driver =3D { > + .name =3D "bd71828-gpio" > + }, > + .probe =3D bd71828_probe, > +}; > + > +module_platform_driver(bd71828_gpio); > + > +MODULE_AUTHOR("Matti Vaittinen "); > +MODULE_DESCRIPTION("BD71828 voltage regulator driver"); > +MODULE_LICENSE("GPL"); > +MODULE_ALIAS("platform:bd71828-gpio"); > -- > 2.21.0 > > > -- > Matti Vaittinen, Linux device drivers > ROHM Semiconductors, Finland SWDC > Kiviharjunlenkki 1E > 90220 OULU > FINLAND > > ~~~ "I don't think so," said Rene Descartes. Just then he vanished ~~~ > Simon says - in Latin please. > ~~~ "non cogito me" dixit Rene Descarte, deinde evanescavit ~~~ > Thanks to Simon Glass for the translation =3D] Reviewed-by: Bartosz Golaszewski