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[209.85.128.177]) by smtp.gmail.com with ESMTPSA id b13-20020a05620a088d00b0069fd2a10ef7sm4325466qka.100.2022.05.03.08.53.34 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 03 May 2022 08:53:34 -0700 (PDT) Received: by mail-yw1-f177.google.com with SMTP id 00721157ae682-2f863469afbso160412567b3.0; Tue, 03 May 2022 08:53:34 -0700 (PDT) X-Received: by 2002:a81:6588:0:b0:2f8:b75e:1e1a with SMTP id z130-20020a816588000000b002f8b75e1e1amr16162028ywb.358.1651593214307; Tue, 03 May 2022 08:53:34 -0700 (PDT) MIME-Version: 1.0 References: <20220429143505.88208-1-clement.leger@bootlin.com> <20220429143505.88208-5-clement.leger@bootlin.com> In-Reply-To: <20220429143505.88208-5-clement.leger@bootlin.com> From: Geert Uytterhoeven Date: Tue, 3 May 2022 17:53:10 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [net-next v2 04/12] net: pcs: add Renesas MII converter driver To: =?UTF-8?B?Q2zDqW1lbnQgTMOpZ2Vy?= Cc: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Geert Uytterhoeven , Magnus Damm , Heiner Kallweit , Russell King , Thomas Petazzoni , Herve Codina , =?UTF-8?Q?Miqu=C3=A8l_Raynal?= , Milan Stevanovic , Jimmy Lalande , Pascal Eberhard , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, netdev@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8BIT Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Clément, On Fri, Apr 29, 2022 at 4:36 PM Clément Léger wrote: > Add a PCS driver for the MII converter that is present on the Renesas > RZ/N1 SoC. This MII converter is reponsible for converting MII to > RMII/RGMII or act as a MII pass-trough. Exposing it as a PCS allows to > reuse it in both the switch driver and the stmmac driver. Currently, > this driver only allows the PCS to be used by the dual Cortex-A7 > subsystem since the register locking system is not used. > > Signed-off-by: Clément Léger > --- a/drivers/net/pcs/Kconfig > +++ b/drivers/net/pcs/Kconfig > @@ -18,4 +18,11 @@ config PCS_LYNX > This module provides helpers to phylink for managing the Lynx PCS > which is part of the Layerscape and QorIQ Ethernet SERDES. > > +config PCS_RZN1_MIIC > + tristate "Renesas RZ/N1 MII converter" depends on ARCH_RZN1 || COMPILE_TEST > + help > + This module provides a driver for the MII converter that is available > + on RZ/N1 SoCs. This PCS convert MII to RMII/RGMII or can be set in converts > + pass-through mode for MII. > + > --- /dev/null > +++ b/drivers/net/pcs/pcs-rzn1-miic.c > +static int miic_probe(struct platform_device *pdev) > +{ > + struct device *dev = &pdev->dev; > + struct miic *miic; > + u32 mode_cfg; > + int ret; > + > + ret = miic_parse_dt(dev, &mode_cfg); > + if (ret < 0) > + return -EINVAL; > + > + miic = devm_kzalloc(dev, sizeof(*miic), GFP_KERNEL); > + if (!miic) > + return -ENOMEM; > + > + spin_lock_init(&miic->lock); > + miic->dev = dev; > + miic->base = devm_platform_ioremap_resource(pdev, 0); > + if (!miic->base) > + return -EINVAL; > + > + miic->nclk = devm_clk_bulk_get_all(dev, &miic->clks); > + if (miic->nclk < 0) > + return miic->nclk; > + > + ret = clk_bulk_prepare_enable(miic->nclk, miic->clks); > + if (ret) > + return ret; As you don't seem to need any knowledge about the clocks' properties, perhaps you can use Runtime PM instead? Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds