From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 30FADC4320E for ; Tue, 10 Aug 2021 09:24:41 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 18AB660F55 for ; Tue, 10 Aug 2021 09:24:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238951AbhHJJZB (ORCPT ); Tue, 10 Aug 2021 05:25:01 -0400 Received: from mail-ua1-f52.google.com ([209.85.222.52]:36701 "EHLO mail-ua1-f52.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234739AbhHJJY5 (ORCPT ); Tue, 10 Aug 2021 05:24:57 -0400 Received: by mail-ua1-f52.google.com with SMTP id v3so8300356uau.3; Tue, 10 Aug 2021 02:24:35 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=ICqADYaP1A14+MyANtx/aXP29/vtA2xTZTvUmJgQydA=; b=qX1PtnwZCIwCfUbDCXChUb0CPdkFiFLNtSVl2zNY5SrQLc4dwYn7dlXYV9uK1fC3td 1j4pNAC0ZXFsAJad7ZyrDFjHaJhsKROh02IC7hUhMwD/ylLiyouwEKmbJokVaUp0Sx8F 3UXmZZeM3+OOqUDo15igvAaTRJ+yRbWlcorGiSSZK2cpaQ+xX8UxG07Kvvg51lDuw4/Q Zb0nsNyWXDMjcFhGOeNivYaq62eRAKUuckRa8n32WhSwix6IgjHitqmm011qvyUUn1x+ GALJJ7Lpzb6xJqRrAUrdAkmMAaGwwcFLO9nW8efdFGSzFjrCfTfomgNp/m/dxGijih5n RE2Q== X-Gm-Message-State: AOAM532kfE0CW/qybN+lV015IYZRN28l2h/3LfLSXHc8TKgC04/D3qKV hDD2LJs+dXhmpBsOrhyDafq7tIhQeIegzMhMH5Y= X-Google-Smtp-Source: ABdhPJx0+WKs4BIH2VfJ9bQwS28hkA/EVWEvawlX2BcIkosS8SlaxLrvTttwLfx7NXsyDcZcgZofzopA9Ko/fGvHiyM= X-Received: by 2002:ab0:1d05:: with SMTP id j5mr5141579uak.2.1628587473228; Tue, 10 Aug 2021 02:24:33 -0700 (PDT) MIME-Version: 1.0 References: <20210727112328.18809-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20210727112328.18809-5-prabhakar.mahadev-lad.rj@bp.renesas.com> In-Reply-To: <20210727112328.18809-5-prabhakar.mahadev-lad.rj@bp.renesas.com> From: Geert Uytterhoeven Date: Tue, 10 Aug 2021 11:24:22 +0200 Message-ID: Subject: Re: [PATCH v4 4/4] arm64: dts: renesas: rzg2l-smarc: Add scif0 pins To: Lad Prabhakar Cc: Rob Herring , Linus Walleij , Magnus Damm , "open list:GPIO SUBSYSTEM" , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , Linux-Renesas , Linux Kernel Mailing List , Prabhakar , Biju Das Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Prabhakar, On Tue, Jul 27, 2021 at 1:23 PM Lad Prabhakar wrote: > Add scif0 pins in pinctrl node and update the scif0 node > to include pinctrl properties. > > Signed-off-by: Lad Prabhakar > Reviewed-by: Biju Das Thanks for your patch! Reviewed-by: Geert Uytterhoeven As this depends on the pin control driver, which goes in through a different path, I think I have to postpone this to v5.16. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds