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[209.85.128.178]) by smtp.gmail.com with ESMTPSA id w22-20020a05620a445600b006bb83c2be40sm15971178qkp.59.2022.09.08.00.07.11 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 08 Sep 2022 00:07:11 -0700 (PDT) Received: by mail-yw1-f178.google.com with SMTP id 00721157ae682-3321c2a8d4cso153897197b3.5; Thu, 08 Sep 2022 00:07:11 -0700 (PDT) X-Received: by 2002:a25:8247:0:b0:6a9:443a:cc0b with SMTP id d7-20020a258247000000b006a9443acc0bmr6067365ybn.89.1662620461133; Thu, 08 Sep 2022 00:01:01 -0700 (PDT) MIME-Version: 1.0 References: <7423117.EvYhyI6sBW@kista> <84f28dc3-3b65-ea70-4fa4-765d0c773c28@microchip.com> In-Reply-To: <84f28dc3-3b65-ea70-4fa4-765d0c773c28@microchip.com> From: Geert Uytterhoeven Date: Thu, 8 Sep 2022 09:00:49 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH 00/12] riscv: Allwinner D1 platform support To: Conor Dooley Cc: Jernej Skrabec , Samuel Holland , Palmer Dabbelt , Chen-Yu Tsai , linux-sunxi@lists.linux.dev, Paul Walmsley , Albert Ou , linux-riscv , Rob Herring , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , Linux Kernel Mailing List , Krzysztof Kozlowski , Arnd Bergmann , Olof Johansson Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8BIT Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Conor, CC soc people On Wed, Sep 7, 2022 at 10:43 PM wrote: > On 06/09/2022 21:29, Jernej Škrabec wrote: > > Dne četrtek, 01. september 2022 ob 20:10:13 CEST je Palmer Dabbelt napisal(a): > >> On Sun, 14 Aug 2022 22:08:03 PDT (-0700), samuel@sholland.org wrote: > >>> arch/riscv/boot/dts/allwinner/sun20i-d1-clockworkpi-v3.14.dts create > >>> mode 100644 > >>> arch/riscv/boot/dts/allwinner/sun20i-d1-common-regulators.dtsi create > >>> mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-devterm-v3.14.dts > >>> create mode 100644 > >>> arch/riscv/boot/dts/allwinner/sun20i-d1-dongshan-nezha-stu.dts create > >>> mode 100644 > >>> arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel-480p.dts > >>> create mode 100644 > >>> arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel-720p.dts > >>> create mode 100644 > >>> arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel.dtsi create > >>> mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-dock.dts > >>> create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv.dts > >>> create mode 100644 > >>> arch/riscv/boot/dts/allwinner/sun20i-d1-mangopi-mq-pro.dts create mode > >>> 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts create mode > >>> 100644 arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi > >> > >> I'm assuming these are aimed at the RISC-V tree? I'm generally OK with > >> that, though the DT folks have pointed out a handful of issues that look > >> pretty reasonable to me. > > > > DT changes for Allwinner ARM SoCs go trough sunxi tree. Should this be handled > > differently for RISC-V? > > Microchip RISC-V DT go via a Microchip tree to Palmer. The other stuff gets > picked directly by him as it has no clear "owner". I think it would be nice > to be consistent for the new {renesas,sunxi} stuff and send those via vendor > trees to Palmer too. Just my 2 cents... Wasn't the intention behind the rename s/arm-soc/soc/ to start accepting PRs for non-arm DT, too? Especially if we start having dependencies due to riscv DTS files including arm64 DTS snippets through scripts/dtc/include-prefixes/arm64/. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds