From: Geert Uytterhoeven <geert@linux-m68k.org>
To: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Cc: Marc Zyngier <maz@kernel.org>,
Thomas Gleixner <tglx@linutronix.de>,
Rob Herring <robh+dt@kernel.org>,
Linus Walleij <linus.walleij@linaro.org>,
Geert Uytterhoeven <geert+renesas@glider.be>,
Magnus Damm <magnus.damm@gmail.com>,
Bartosz Golaszewski <bgolaszewski@baylibre.com>,
Philipp Zabel <p.zabel@pengutronix.de>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
<devicetree@vger.kernel.org>,
Linux-Renesas <linux-renesas-soc@vger.kernel.org>,
"open list:GPIO SUBSYSTEM" <linux-gpio@vger.kernel.org>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
Prabhakar <prabhakar.csengg@gmail.com>,
Biju Das <biju.das.jz@bp.renesas.com>
Subject: Re: [RFC PATCH v3 0/7] Renesas RZ/G2L IRQC support
Date: Fri, 12 Nov 2021 15:12:29 +0100 [thread overview]
Message-ID: <CAMuHMdWmvPgAeS1o8aubaYBihuFrggoVkpT8XtnTZ6nq-VXn9A@mail.gmail.com> (raw)
In-Reply-To: <20211110225808.16388-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
Hi Prabhakar,
On Wed, Nov 10, 2021 at 11:58 PM Lad Prabhakar
<prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> The RZ/G2L Interrupt Controller is a front-end for the GIC found on
> Renesas RZ/G2L SoC's with below pins:
> - IRQ sense select for 8 external interrupts, mapped to 8 GIC SPI interrupts
> - GPIO pins used as external interrupt input pins out of GPIOINT0-122 a
> maximum of only 32 can be mapped to 32 GIC SPI interrupts,
> - NMI edge select.
>
> _____________
> | GIC |
> | ________ |
> ____________ | | | |
> NMI ------------------------------------>| | SPI0-479 | | GIC-600| |
> _______ | |------------>| | |
> | | | | PPI16-31 | | | |
> | | IRQ0-IRQ8 | IRQC |------------>| | |
IRQ0-IRQ7?
> P0_P48_4 ------>| GPIO |---------------->| | | |________| |
> | |GPIOINT0-122 | | | |
> | |---------------->| TINT0-31 | | |
> |______| |__________| |____________|
>
> The proposed RFC patches, add the IRQ domains in GPIO (pinctrl driver) and the
> IRQC driver. The IRQC domain handles the actual SPI interrupt and upon reception
> of the interrupt it propagates to the GPIO IRQ domain to handle virq.
> Out of GPIOINT0-122 only 32 can be mapped to GIC SPI, this mapping is handled by
> the IRQC driver.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
next prev parent reply other threads:[~2021-11-12 14:12 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-10 22:58 [RFC PATCH v3 0/7] Renesas RZ/G2L IRQC support Lad Prabhakar
2021-11-10 22:58 ` [RFC PATCH v3 1/7] dt-bindings: interrupt-controller: Add Renesas RZ/G2L Interrupt Controller Lad Prabhakar
2021-11-19 16:52 ` Rob Herring
2021-11-10 22:58 ` [RFC PATCH v3 2/7] irqchip: Add RZ/G2L IA55 Interrupt Controller driver Lad Prabhakar
2021-12-10 14:37 ` Marc Zyngier
2021-11-10 22:58 ` [RFC PATCH v3 3/7] soc: renesas: Enable IRQC driver for RZ/G2L Lad Prabhakar
2021-11-10 22:58 ` [RFC PATCH v3 4/7] gpio: gpiolib: Allow free() callback to be overridden Lad Prabhakar
2021-11-10 22:58 ` [RFC PATCH v3 5/7] gpio: gpiolib: Add ngirq member to struct gpio_irq_chip Lad Prabhakar
2021-11-11 20:52 ` Andy Shevchenko
2021-11-11 21:15 ` Lad, Prabhakar
2021-11-10 22:58 ` [RFC PATCH v3 6/7] pinctrl: renesas: pinctrl-rzg2l: Add IRQ domain to handle GPIO interrupt Lad Prabhakar
2021-11-10 22:58 ` [RFC PATCH v3 7/7] arm64: dts: renesas: r9a07g044: Add IRQC node to SoC DTSI Lad Prabhakar
2021-11-12 14:12 ` Geert Uytterhoeven [this message]
2021-11-12 14:22 ` [RFC PATCH v3 0/7] Renesas RZ/G2L IRQC support Lad, Prabhakar
2021-11-22 19:25 ` Lad, Prabhakar
2021-12-10 1:08 ` Lad, Prabhakar
2021-12-10 2:04 ` Linus Walleij
2021-12-10 9:37 ` Lad, Prabhakar
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