From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B81ADC433FE for ; Mon, 13 Sep 2021 08:05:27 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A07C6603E9 for ; Mon, 13 Sep 2021 08:05:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237846AbhIMIGk (ORCPT ); Mon, 13 Sep 2021 04:06:40 -0400 Received: from mail-vs1-f47.google.com ([209.85.217.47]:37610 "EHLO mail-vs1-f47.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237797AbhIMIGi (ORCPT ); Mon, 13 Sep 2021 04:06:38 -0400 Received: by mail-vs1-f47.google.com with SMTP id i23so7629360vsj.4; Mon, 13 Sep 2021 01:05:23 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=hIy/WF41WnhInRxQvOeLA91NgtT/ad5oPS0o2VKCwNg=; b=H1wPdid9exSg992pPXhiMALn/wP/WluGxrpodaX1dXaLk5agS9mbY2yNT/LkDIvVP/ UZq0eLqXKW7eiJTLtNyHs2ag19/bQH+yVAxbR29EcWipIPoPzZG9ElYun+7fXCnXnwX5 IGPlyOI1hteTd1Pdfrzj0zi1d8CVrpkEIIcydKhybo/8re/g1YBa1SZegn9cDo3pcGb6 AVzZZFG749rmuw0sgd3vELdS7+mOoNgCQA0dPXnvsC6y1CtZEhCnYgi235Wka8tiOG7a VEgvxC3ecjIHdzth723jUqYenqYkfyv1FM9ow6wP+cSm5Yn66Sb0ZpZfy1gQyjdErZxb Rsqg== X-Gm-Message-State: AOAM530VG9N7DxeRHM1vO5J8LwqJ9TG+eb6JgvYQbfSapGTk4gsb3BEi pWWWWr86mWYNoTuhl4l6qTo2eWsii/w249BGYUiJYdoi7/w= X-Google-Smtp-Source: ABdhPJy5qS7cAHC3Wj9WuuKOmYXH4sq8/3ktX7gWNSl8zk/qKzaCAAZqM9h3ouNfCut0fUdqY/dAAiCGCBBDbPtKIvo= X-Received: by 2002:a05:6102:3112:: with SMTP id e18mr2487715vsh.50.1631520322815; Mon, 13 Sep 2021 01:05:22 -0700 (PDT) MIME-Version: 1.0 References: <20200624195811.435857-1-maz@kernel.org> <20200624195811.435857-8-maz@kernel.org> <875yv8d91b.wl-maz@kernel.org> <874kaqdi2z.wl-maz@kernel.org> In-Reply-To: From: Geert Uytterhoeven Date: Mon, 13 Sep 2021 10:05:11 +0200 Message-ID: Subject: Re: [PATCH v2 07/17] irqchip/gic: Atomically update affinity To: Magnus Damm Cc: Marc Zyngier , Russell King , Linux ARM , Linux Kernel Mailing List , Will Deacon , Catalin Marinas , Thomas Gleixner , Jason Cooper , Sumit Garg , Valentin Schneider , Florian Fainelli , Gregory Clement , Andrew Lunn , Android Kernel Team , stable , Magnus Damm , =?UTF-8?Q?Niklas_S=C3=B6derlund?= , Linux-Renesas Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Magnus, On Sun, Sep 12, 2021 at 7:40 AM Magnus Damm wrote: > On Sun, Sep 12, 2021 at 4:32 AM Marc Zyngier wrote: > > On Sat, 11 Sep 2021 03:49:20 +0100, > > Magnus Damm wrote: > > > On Fri, Sep 10, 2021 at 10:19 PM Geert Uytterhoeven > > > wrote: > > > > On Fri, Sep 10, 2021 at 12:23 PM Marc Zyngier wrote: > > > > > On Thu, 09 Sep 2021 16:22:01 +0100, > > > > > Geert Uytterhoeven wrote: > > > > GIC: enabling workaround for broken byte access > > > > > > Indeed, byte access is unsupported according to the EMEV2 documentation. > > > > > > The EMEV2 documentation R19UH0036EJ0600 Chapter 7 Interrupt Control on > > > page 97 says: > > > "Interrupt registers can be accessed via the APB bus, in 32-bit units" > > > "For details about register functions, see ARM Generic Interrupt > > > Controller Architecture Specification Architecture version 1.0" > > > The file "R19UH0036EJ0600_1Chip.pdf" is the 6th edition version > > > published in 2010 and is not marked as confidential. > > > > This is as bad as it gets. Do you know if any other Renesas platform > > is affected by the same issue? > > Next time we have a beer together I would be happy to show you some > legacy interrupt controller code. =) > > EMEV2 and the Emma Mobile product line came from the NEC Electronics > side that got merged into Renesas Electronics in 2010. Historically > NEC Electronics mainly used MIPS I've been told, and the Emma Mobile > SoCs were one of the earlier Cortex-A9 adopters. That might have > something to do with the rather loose interpretation of the spec. Indeed. I used to work on products using EMMA1 and EMMA2, and they were MIPS-based (vr4120A for EMMA2, IIRC). Later variants (EMMA2H and EMMA3?) did include a small ARM core for standby control. > Renesas SoCs from a similar era: > AP4 (sh7372) AP4EVB (Cortex-A8 + INTCA/INTCS) This is no longer supported upstream (and not affected, as no GIC). > R-Mobile A1 (r8a7740) Armadillo-800-EVA (Cortex-A9 + INTCA/INTCS) R-Mobile A1 has GIC (PL390), too, and is not affected. > R-Car M1A (r8a7778) Bock-W (Cortex-A9 + GIC) > R-Car H1 (r8a7779) Marzen (4 x Cortex-A9 + GIC) > Emma Mobile EMEV2 KZM9D (2 x Cortex-A9 + GIC) > SH-Mobile AG5 (sh73a0) KZM9G (2 x Cortex-A9 + GIC) All of these (except for EMEV2) are fine, too. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds