From: Geert Uytterhoeven <geert@linux-m68k.org>
To: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Cc: Magnus Damm <magnus.damm@gmail.com>,
Rob Herring <robh+dt@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
Linux-Renesas <linux-renesas-soc@vger.kernel.org>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
<devicetree@vger.kernel.org>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
linux-clk <linux-clk@vger.kernel.org>,
Linux ARM <linux-arm-kernel@lists.infradead.org>,
Prabhakar <prabhakar.csengg@gmail.com>,
Biju Das <biju.das.jz@bp.renesas.com>
Subject: Re: [PATCH v3 08/11] clk: renesas: Add CPG core wrapper for RZ/G2L SoC
Date: Thu, 10 Jun 2021 15:03:48 +0200 [thread overview]
Message-ID: <CAMuHMdXR0y7d2hRi35YsTT2rdOtRzFirGwbVnbUVO2d3yV=mwg@mail.gmail.com> (raw)
In-Reply-To: <20210609153230.6967-9-prabhakar.mahadev-lad.rj@bp.renesas.com>
Hi Prabhakar,
On Wed, Jun 9, 2021 at 5:33 PM Lad Prabhakar
<prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> Add CPG core wrapper for RZ/G2L family.
>
> Based on a patch in the BSP by Binh Nguyen
> <binh.nguyen.jz@renesas.com>.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Thanks for your patch!
> --- a/drivers/clk/renesas/Kconfig
> +++ b/drivers/clk/renesas/Kconfig
> @@ -182,6 +182,11 @@ config CLK_RCAR_USB2_CLOCK_SEL
> help
> This is a driver for R-Car USB2 clock selector
>
> +config CLK_RZG2L
> + bool "Renesas RZ/G2L SoC clock support" if COMPILE_TEST && !ARCH_RENESAS
s/SoC/family/?
I think "if COMPILE_TEST", as all other entries are using, is sufficient.
> + depends on ARCH_RENESAS || COMPILE_TEST
I think this can be dropped.
> + select RESET_CONTROLLER
> +
> # Generic
> --- /dev/null
> +++ b/drivers/clk/renesas/renesas-rzg2l-cpg.c
> +static struct clk
> +*rzg2l_cpg_clk_src_twocell_get(struct of_phandle_args *clkspec,
> + void *data)
> +{
> + unsigned int clkidx = clkspec->args[1];
> + struct rzg2l_cpg_priv *priv = data;
> + struct device *dev = priv->dev;
> + const char *type;
> + struct clk *clk;
> +
> + switch (clkspec->args[0]) {
> + case CPG_CORE:
> + type = "core";
> + if (clkidx > priv->last_dt_core_clk) {
> + dev_err(dev, "Invalid %s clock index %u\n", type, clkidx);
> + return ERR_PTR(-EINVAL);
> + }
> + clk = priv->clks[clkidx];
> + break;
> +
> + case CPG_MOD:
> + type = "module";
> + if (clkidx > priv->num_core_clks + priv->num_mod_clks) {
The range of module clocks in DT specifiers starts at zero, so
if (clkidx > priv->num_mod_clks) {
> + dev_err(dev, "Invalid %s clock index %u\n", type,
> + clkidx);
> + return ERR_PTR(-EINVAL);
> + }
> + clk = priv->clks[priv->num_core_clks + clkidx];
> + break;
> +
> + default:
> + dev_err(dev, "Invalid CPG clock type %u\n", clkspec->args[0]);
> + return ERR_PTR(-EINVAL);
> + }
> +
> + if (IS_ERR(clk))
> + dev_err(dev, "Cannot get %s clock %u: %ld", type, clkidx,
> + PTR_ERR(clk));
> + else
> + dev_dbg(dev, "clock (%u, %u) is %pC at %lu Hz\n",
> + clkspec->args[0], clkspec->args[1], clk,
> + clk_get_rate(clk));
> + return clk;
> +}
With the above fixed:
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
I can fix these while applying.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
next prev parent reply other threads:[~2021-06-10 13:04 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-09 15:32 [PATCH v3 00/11] Add new Renesas RZ/G2L SoC and Renesas RZ/G2L SMARC EVK support Lad Prabhakar
2021-06-09 15:32 ` [PATCH v3 01/11] dt-bindings: arm: renesas: Document Renesas RZ/G2UL SoC Lad Prabhakar
2021-06-09 15:32 ` [PATCH v3 02/11] dt-bindings: arm: renesas: Document Renesas RZ/G2{L,LC} SoC variants Lad Prabhakar
2021-06-09 15:32 ` [PATCH v3 03/11] dt-bindings: arm: renesas: Document SMARC EVK Lad Prabhakar
2021-06-09 15:32 ` [PATCH v3 04/11] soc: renesas: Add ARCH_R9A07G044 for the new RZ/G2L SoC's Lad Prabhakar
2021-06-09 15:32 ` [PATCH v3 05/11] arm64: defconfig: Enable ARCH_R9A07G044 Lad Prabhakar
2021-06-09 15:32 ` [PATCH v3 06/11] clk: renesas: Define RZ/G2L CPG Clock Definitions Lad Prabhakar
2021-06-10 12:31 ` Geert Uytterhoeven
2021-06-09 15:32 ` [PATCH v3 07/11] dt-bindings: clock: renesas: Document RZ/G2L SoC CPG driver Lad Prabhakar
2021-06-10 12:30 ` Geert Uytterhoeven
2021-06-10 12:31 ` Geert Uytterhoeven
2021-06-09 15:32 ` [PATCH v3 08/11] clk: renesas: Add CPG core wrapper for RZ/G2L SoC Lad Prabhakar
2021-06-10 13:03 ` Geert Uytterhoeven [this message]
2021-06-10 14:05 ` Lad, Prabhakar
2021-06-09 15:32 ` [PATCH v3 09/11] clk: renesas: Add support for R9A07G044 SoC Lad Prabhakar
2021-06-10 13:04 ` Geert Uytterhoeven
2021-06-09 15:32 ` [PATCH v3 10/11] arm64: dts: renesas: Add initial DTSI for RZ/G2{L,LC} SoC's Lad Prabhakar
2021-06-10 12:34 ` Geert Uytterhoeven
2021-06-09 15:32 ` [PATCH v3 11/11] arm64: dts: renesas: Add initial device tree for RZ/G2L SMARC EVK Lad Prabhakar
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