From: Brian Gerst <brgerst@gmail.com>
To: Xin Li <xin3.li@intel.com>
Cc: linux-kernel@vger.kernel.org, x86@kernel.org, tglx@linutronix.de,
mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com,
hpa@zytor.com
Subject: Re: [PATCH 6/6] x86/gsseg: use the LKGS instruction if available for load_gs_index()
Date: Fri, 7 Oct 2022 12:18:45 -0400 [thread overview]
Message-ID: <CAMzpN2iccL5kNa2UaBXppiLnoNWrpwJd74+uBrB_63N0F5F5Xg@mail.gmail.com> (raw)
In-Reply-To: <20221006154041.13001-7-xin3.li@intel.com>
On Thu, Oct 6, 2022 at 12:19 PM Xin Li <xin3.li@intel.com> wrote:
>
> From: "H. Peter Anvin (Intel)" <hpa@zytor.com>
>
> The LKGS instruction atomically loads a segment descriptor into the
> %gs descriptor registers, *except* that %gs.base is unchanged, and the
> base is instead loaded into MSR_IA32_KERNEL_GS_BASE, which is exactly
> what we want this function to do.
>
> Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
> Signed-off-by: Xin Li <xin3.li@intel.com>
> ---
> arch/x86/include/asm/gsseg.h | 28 +++++++++++++++++++++++++++-
> 1 file changed, 27 insertions(+), 1 deletion(-)
>
> diff --git a/arch/x86/include/asm/gsseg.h b/arch/x86/include/asm/gsseg.h
> index 5e3b56a17098..b8a6a98d88b8 100644
> --- a/arch/x86/include/asm/gsseg.h
> +++ b/arch/x86/include/asm/gsseg.h
> @@ -3,15 +3,41 @@
> #define _ASM_X86_GSSEG_H
>
> #include <linux/types.h>
> +
> +#include <asm/asm.h>
> +#include <asm/cpufeature.h>
> +#include <asm/alternative.h>
> #include <asm/processor.h>
> +#include <asm/nops.h>
>
> #ifdef CONFIG_X86_64
>
> extern asmlinkage void asm_load_gs_index(u16 selector);
>
> +#define LKGS_DI _ASM_BYTES(0xf2,0x0f,0x00,0xf7)
> +
> static inline void native_load_gs_index(unsigned int selector)
> {
> - asm_load_gs_index(selector);
> + u16 sel = selector;
> +
> + /*
> + * Note: the fixup is used for the LKGS instruction, but
> + * it needs to be attached to the primary instruction sequence
> + * as it isn't something that gets patched.
> + *
> + * %rax is provided to the assembly routine as a scratch
> + * register.
> + */
> + alternative_io("1: call asm_load_gs_index\n"
> + ".pushsection \".fixup\",\"ax\"\n"
> + "2: xorl %k[sel], %k[sel]\n"
> + " jmp 1b\n"
> + ".popsection\n"
> + _ASM_EXTABLE(1b, 2b),
> + _ASM_BYTES(0x3e) LKGS_DI,
> + X86_FEATURE_LKGS,
> + ASM_OUTPUT2([sel] "+D" (sel), ASM_CALL_CONSTRAINT),
> + ASM_NO_INPUT_CLOBBER(_ASM_AX));
> }
>
> #endif /* CONFIG_X86_64 */
> --
> 2.34.1
There are not that many call sites, so using something like this
(incorporating Peter Z's suggestion for the exception handler) would
be better from a code readability perspective vs. a tiny increase in
code size.
if (static_cpu_has(X86_FEATURE_LKGS))
asm volatile("1: " LKGS_DI
_ASM_EXTABLE_TYPE_REG(1b, 1b,
EX_TYPE_ZERO_REG, %k[sel])
: [sel] "+D" (sel) : : "memory");
else
asm_load_gs_index(sel);
--
Brian Gerst
next prev parent reply other threads:[~2022-10-07 16:19 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-06 15:40 [PATCH 0/6] Enable LKGS instruction Xin Li
2022-10-06 15:40 ` [PATCH 1/6] x86/cpufeature: add cpu feature bit for LKGS Xin Li
2022-10-06 15:40 ` [PATCH 2/6] x86/opcode: add LKGS instruction to x86-opcode-map Xin Li
2022-10-06 15:40 ` [PATCH 3/6] x86/gsseg: make asm_load_gs_index() take an u16 Xin Li
2022-10-06 15:40 ` [PATCH 4/6] x86/gsseg: move local_irq_save/restore() into asm_load_gs_index() Xin Li
2022-10-07 14:50 ` Peter Zijlstra
2022-10-07 17:47 ` H. Peter Anvin
2022-10-06 15:40 ` [PATCH 5/6] x86/gsseg: move load_gs_index() to its own header file Xin Li
2022-10-07 15:40 ` Brian Gerst
2022-10-07 17:43 ` H. Peter Anvin
2022-10-07 22:41 ` Li, Xin3
2022-10-06 15:40 ` [PATCH 6/6] x86/gsseg: use the LKGS instruction if available for load_gs_index() Xin Li
2022-10-07 14:47 ` Peter Zijlstra
2022-10-07 17:45 ` H. Peter Anvin
2022-10-07 18:07 ` Li, Xin3
2022-10-07 18:49 ` H. Peter Anvin
2022-10-07 18:01 ` Li, Xin3
2022-10-07 19:24 ` Peter Zijlstra
2022-10-07 20:03 ` H. Peter Anvin
2022-10-07 20:23 ` Peter Zijlstra
2022-10-07 20:33 ` H. Peter Anvin
2022-10-08 5:32 ` Li, Xin3
2022-10-08 7:16 ` H. Peter Anvin
2022-10-10 4:21 ` Li, Xin3
2022-10-14 4:36 ` Li, Xin3
2022-10-07 14:52 ` Peter Zijlstra
2022-10-07 15:09 ` Peter Zijlstra
2022-10-08 5:31 ` Li, Xin3
2022-10-07 16:18 ` Brian Gerst [this message]
2022-10-08 5:40 ` Li, Xin3
2022-10-08 12:40 ` Brian Gerst
2022-10-10 4:32 ` Li, Xin3
2022-10-10 4:51 ` H. Peter Anvin
2022-10-10 7:53 ` Peter Zijlstra
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