From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753301AbcIFBWX (ORCPT ); Mon, 5 Sep 2016 21:22:23 -0400 Received: from mail-wm0-f68.google.com ([74.125.82.68]:36372 "EHLO mail-wm0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752887AbcIFBWV (ORCPT ); Mon, 5 Sep 2016 21:22:21 -0400 MIME-Version: 1.0 In-Reply-To: <95a853538da28c64dfc877c60549ec79ed7a5d69.1452294700.git.luto@kernel.org> References: <95a853538da28c64dfc877c60549ec79ed7a5d69.1452294700.git.luto@kernel.org> From: Wanpeng Li Date: Tue, 6 Sep 2016 09:22:18 +0800 Message-ID: Subject: Re: [RFC 05/13] x86/mm: Add barriers and document switch_mm-vs-flush synchronization To: Andy Lutomirski Cc: "the arch/x86 maintainers" , "linux-kernel@vger.kernel.org" , Borislav Petkov , Brian Gerst , Dave Hansen , Linus Torvalds , Oleg Nesterov , "linux-mm@kvack.org" , stable@vger.kernel.org Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Andy, 2016-01-09 7:15 GMT+08:00 Andy Lutomirski : > When switch_mm activates a new pgd, it also sets a bit that tells > other CPUs that the pgd is in use so that tlb flush IPIs will be > sent. In order for that to work correctly, the bit needs to be > visible prior to loading the pgd and therefore starting to fill the > local TLB. > > Document all the barriers that make this work correctly and add a > couple that were missing. > > Cc: stable@vger.kernel.org > Signed-off-by: Andy Lutomirski > --- > arch/x86/include/asm/mmu_context.h | 33 ++++++++++++++++++++++++++++++++- > arch/x86/mm/tlb.c | 29 ++++++++++++++++++++++++++--- > 2 files changed, 58 insertions(+), 4 deletions(-) > > diff --git a/arch/x86/include/asm/mmu_context.h b/arch/x86/include/asm/mmu_context.h > index 379cd3658799..1edc9cd198b8 100644 > --- a/arch/x86/include/asm/mmu_context.h > +++ b/arch/x86/include/asm/mmu_context.h > @@ -116,8 +116,34 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, > #endif > cpumask_set_cpu(cpu, mm_cpumask(next)); > > - /* Re-load page tables */ > + /* > + * Re-load page tables. > + * > + * This logic has an ordering constraint: > + * > + * CPU 0: Write to a PTE for 'next' > + * CPU 0: load bit 1 in mm_cpumask. if nonzero, send IPI. > + * CPU 1: set bit 1 in next's mm_cpumask > + * CPU 1: load from the PTE that CPU 0 writes (implicit) > + * > + * We need to prevent an outcome in which CPU 1 observes > + * the new PTE value and CPU 0 observes bit 1 clear in > + * mm_cpumask. (If that occurs, then the IPI will never > + * be sent, and CPU 0's TLB will contain a stale entry.) I misunderstand this comments, CPU0 write to a PTE for 'next', and CPU0 observes bit 1 clear in mm_cpumask, so CPU0 won't kick IPI to CPU1, why CPU0's TLB will contain a stale entry instead of CPU1? Regards, Wanpeng Li