[PATCH 0/3] Rename sifive L2 cache to sifive CCACHE

[PATCH 0/3] Rename sifive L2 cache to sifive CCACHE

[Zong Li]

Since composible cache may be L3 cache if private L2 cache exists, we
should use its original name "composible cache" to prevent confusion.

This patchset contains the modification which is related to ccache, such
as DT binding and EDAC driver.

Greentime Hu (1):
  soc: sifive: l2 cache: Rename SiFive L2 cache to composible cache.

Zong Li (2):
  dt-bindings: sifive-ccache: rename SiFive L2 cache to composible cache
  EDAC/sifive: use sifive_ccache instead of sifive_l2

 ...ifive-l2-cache.yaml => sifive-ccache.yaml} |   6 +-
 drivers/edac/Kconfig                          |   2 +-
 drivers/edac/sifive_edac.c                    |  12 +-
 drivers/soc/sifive/Kconfig                    |   7 +-
 drivers/soc/sifive/Makefile                   |   2 +-
 drivers/soc/sifive/sifive_ccache.c            | 221 ++++++++++++++++
 drivers/soc/sifive/sifive_l2_cache.c          | 237 ------------------
 include/soc/sifive/sifive_ccache.h            |  16 ++
 include/soc/sifive/sifive_l2_cache.h          |  16 --
 9 files changed, 253 insertions(+), 266 deletions(-)
 rename Documentation/devicetree/bindings/riscv/{sifive-l2-cache.yaml => sifive-ccache.yaml} (92%)
 create mode 100644 drivers/soc/sifive/sifive_ccache.c
 delete mode 100644 drivers/soc/sifive/sifive_l2_cache.c
 create mode 100644 include/soc/sifive/sifive_ccache.h
 delete mode 100644 include/soc/sifive/sifive_l2_cache.h

-- 
2.17.1

[PATCH 1/3] dt-bindings: sifive-ccache: rename SiFive L2 cache to composible cache

[Zong Li]

Since composible cache may be L3 cache if private L2 cache exists, it
should use its original name composible cache to prevent confusion.

Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
Signed-off-by: Zong Li <zong.li@sifive.com>
---
 .../riscv/{sifive-l2-cache.yaml => sifive-ccache.yaml}      | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)
 rename Documentation/devicetree/bindings/riscv/{sifive-l2-cache.yaml => sifive-ccache.yaml} (92%)

diff --git a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml b/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml
similarity index 92%
rename from Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
rename to Documentation/devicetree/bindings/riscv/sifive-ccache.yaml
index 69cdab18d629..1a64a5384e36 100644
--- a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
+++ b/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml
@@ -12,8 +12,8 @@ maintainers:
   - Paul Walmsley  <paul.walmsley@sifive.com>
 
 description:
-  The SiFive Level 2 Cache Controller is used to provide access to fast copies
-  of memory for masters in a Core Complex. The Level 2 Cache Controller also
+  The SiFive Composable Cache Controller is used to provide access to fast copies
+  of memory for masters in a Core Complex. The Composable Cache Controller also
   acts as directory-based coherency manager.
   All the properties in ePAPR/DeviceTree specification applies for this platform.
 
@@ -27,6 +27,7 @@ select:
         enum:
           - sifive,fu540-c000-ccache
           - sifive,fu740-c000-ccache
+          - sifive,ccache0
 
   required:
     - compatible
@@ -37,6 +38,7 @@ properties:
       - enum:
           - sifive,fu540-c000-ccache
           - sifive,fu740-c000-ccache
+          - sifive,ccache0
       - const: cache
 
   cache-block-size:
-- 
2.17.1

[PATCH 2/3] soc: sifive: l2 cache: Rename SiFive L2 cache to composible cache.

[Zong Li]

From: Greentime Hu <greentime.hu@sifive.com>

Since composible cache may be L3 cache if pL2 cache exists, we should use
its original name composible cache to prevent confusion.

Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
Signed-off-by: Zong Li <zong.li@sifive.com>
---
 drivers/soc/sifive/Kconfig           |   7 +-
 drivers/soc/sifive/Makefile          |   2 +-
 drivers/soc/sifive/sifive_ccache.c   | 221 +++++++++++++++++++++++++
 drivers/soc/sifive/sifive_l2_cache.c | 237 ---------------------------
 include/soc/sifive/sifive_ccache.h   |  16 ++
 include/soc/sifive/sifive_l2_cache.h |  16 --
 6 files changed, 242 insertions(+), 257 deletions(-)
 create mode 100644 drivers/soc/sifive/sifive_ccache.c
 delete mode 100644 drivers/soc/sifive/sifive_l2_cache.c
 create mode 100644 include/soc/sifive/sifive_ccache.h
 delete mode 100644 include/soc/sifive/sifive_l2_cache.h

diff --git a/drivers/soc/sifive/Kconfig b/drivers/soc/sifive/Kconfig
index 58cf8c40d08d..3d65d2771f9a 100644
--- a/drivers/soc/sifive/Kconfig
+++ b/drivers/soc/sifive/Kconfig
@@ -2,9 +2,10 @@
 
 if SOC_SIFIVE
 
-config SIFIVE_L2
-	bool "Sifive L2 Cache controller"
+config SIFIVE_CCACHE
+	bool "Sifive composable Cache controller"
+	default y
 	help
-	  Support for the L2 cache controller on SiFive platforms.
+	  Support for the composable cache controller on SiFive platforms.
 
 endif
diff --git a/drivers/soc/sifive/Makefile b/drivers/soc/sifive/Makefile
index b5caff77938f..1f5dc339bf82 100644
--- a/drivers/soc/sifive/Makefile
+++ b/drivers/soc/sifive/Makefile
@@ -1,3 +1,3 @@
 # SPDX-License-Identifier: GPL-2.0
 
-obj-$(CONFIG_SIFIVE_L2)	+= sifive_l2_cache.o
+obj-$(CONFIG_SIFIVE_CCACHE)	+= sifive_ccache.o
diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c
new file mode 100644
index 000000000000..46ce33db7d30
--- /dev/null
+++ b/drivers/soc/sifive/sifive_ccache.c
@@ -0,0 +1,221 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * SiFive composable cache controller Driver
+ *
+ * Copyright (C) 2018-2019 SiFive, Inc.
+ *
+ */
+#include <linux/debugfs.h>
+#include <linux/interrupt.h>
+#include <linux/of_irq.h>
+#include <linux/of_address.h>
+#include <linux/device.h>
+#include <asm/cacheinfo.h>
+#include <soc/sifive/sifive_ccache.h>
+
+#define SIFIVE_CCACHE_DIRECCFIX_LOW 0x100
+#define SIFIVE_CCACHE_DIRECCFIX_HIGH 0x104
+#define SIFIVE_CCACHE_DIRECCFIX_COUNT 0x108
+
+#define SIFIVE_CCACHE_DATECCFIX_LOW 0x140
+#define SIFIVE_CCACHE_DATECCFIX_HIGH 0x144
+#define SIFIVE_CCACHE_DATECCFIX_COUNT 0x148
+
+#define SIFIVE_CCACHE_DATECCFAIL_LOW 0x160
+#define SIFIVE_CCACHE_DATECCFAIL_HIGH 0x164
+#define SIFIVE_CCACHE_DATECCFAIL_COUNT 0x168
+
+#define SIFIVE_CCACHE_CONFIG 0x00
+#define SIFIVE_CCACHE_WAYENABLE 0x08
+#define SIFIVE_CCACHE_ECCINJECTERR 0x40
+
+#define SIFIVE_CCACHE_MAX_ECCINTR 3
+
+static void __iomem *ccache_base;
+static int level;
+static int g_irq[SIFIVE_CCACHE_MAX_ECCINTR];
+static struct riscv_cacheinfo_ops ccache_cache_ops;
+
+enum {
+	DIR_CORR = 0,
+	DATA_CORR,
+	DATA_UNCORR,
+};
+
+#ifdef CONFIG_DEBUG_FS
+static struct dentry *sifive_test;
+
+static ssize_t ccache_write(struct file *file, const char __user *data,
+			size_t count, loff_t *ppos)
+{
+	unsigned int val;
+
+	if (kstrtouint_from_user(data, count, 0, &val))
+		return -EINVAL;
+	if ((val < 0xFF) || (val >= 0x10000 && val < 0x100FF))
+		writel(val, ccache_base + SIFIVE_CCACHE_ECCINJECTERR);
+	else
+		return -EINVAL;
+	return count;
+}
+
+static const struct file_operations ccache_fops = {
+	.owner = THIS_MODULE,
+	.open = simple_open,
+	.write = ccache_write
+};
+
+static void setup_sifive_debug(void)
+{
+	sifive_test = debugfs_create_dir("sifive_ccache_cache", NULL);
+
+	debugfs_create_file("sifive_debug_inject_error", 0200,
+			    sifive_test, NULL, &ccache_fops);
+}
+#endif
+
+static void ccache_config_read(void)
+{
+	u32 regval, val;
+
+	regval = readl(ccache_base + SIFIVE_CCACHE_CONFIG);
+	val = regval & 0xFF;
+	pr_info("CCACHE: No. of Banks in the cache: %d\n", val);
+	val = (regval & 0xFF00) >> 8;
+	pr_info("CCACHE: No. of ways per bank: %d\n", val);
+	val = (regval & 0xFF0000) >> 16;
+	pr_info("CCACHE: Sets per bank: %llu\n", (uint64_t)1 << val);
+	val = (regval & 0xFF000000) >> 24;
+	pr_info("CCACHE: Bytes per cache block: %llu\n", (uint64_t)1 << val);
+
+	regval = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE);
+	pr_info("CCACHE: Index of the largest way enabled: %d\n", regval);
+}
+
+static const struct of_device_id sifive_ccache_ids[] = {
+	{ .compatible = "sifive,fu540-c000-ccache" },
+	{ .compatible = "sifive,ccache0" },
+	{ /* end of table */ },
+};
+
+static ATOMIC_NOTIFIER_HEAD(ccache_err_chain);
+
+int register_sifive_ccache_error_notifier(struct notifier_block *nb)
+{
+	return atomic_notifier_chain_register(&ccache_err_chain, nb);
+}
+EXPORT_SYMBOL_GPL(register_sifive_ccache_error_notifier);
+
+int unregister_sifive_ccache_error_notifier(struct notifier_block *nb)
+{
+	return atomic_notifier_chain_unregister(&ccache_err_chain, nb);
+}
+EXPORT_SYMBOL_GPL(unregister_sifive_ccache_error_notifier);
+
+static int ccache_largest_wayenabled(void)
+{
+	return readl(ccache_base + SIFIVE_CCACHE_WAYENABLE) & 0xFF;
+}
+
+static ssize_t number_of_ways_enabled_show(struct device *dev,
+					   struct device_attribute *attr,
+					   char *buf)
+{
+	return sprintf(buf, "%u\n", ccache_largest_wayenabled());
+}
+
+static DEVICE_ATTR_RO(number_of_ways_enabled);
+
+static struct attribute *priv_attrs[] = {
+	&dev_attr_number_of_ways_enabled.attr,
+	NULL,
+};
+
+static const struct attribute_group priv_attr_group = {
+	.attrs = priv_attrs,
+};
+
+static const struct attribute_group *ccache_get_priv_group(struct cacheinfo *this_leaf)
+{
+	/* We want to use private group for composable cache only */
+	if (this_leaf->level == level)
+		return &priv_attr_group;
+	else
+		return NULL;
+}
+
+static irqreturn_t ccache_int_handler(int irq, void *device)
+{
+	unsigned int add_h, add_l;
+
+	if (irq == g_irq[DIR_CORR]) {
+		add_h = readl(ccache_base + SIFIVE_CCACHE_DIRECCFIX_HIGH);
+		add_l = readl(ccache_base + SIFIVE_CCACHE_DIRECCFIX_LOW);
+		pr_err("CCACHE: DirError @ 0x%08X.%08X\n", add_h, add_l);
+		/* Reading this register clears the DirError interrupt sig */
+		readl(ccache_base + SIFIVE_CCACHE_DIRECCFIX_COUNT);
+		atomic_notifier_call_chain(&ccache_err_chain, SIFIVE_CCACHE_ERR_TYPE_CE,
+					   "DirECCFix");
+	}
+	if (irq == g_irq[DATA_CORR]) {
+		add_h = readl(ccache_base + SIFIVE_CCACHE_DATECCFIX_HIGH);
+		add_l = readl(ccache_base + SIFIVE_CCACHE_DATECCFIX_LOW);
+		pr_err("CCACHE: DataError @ 0x%08X.%08X\n", add_h, add_l);
+		/* Reading this register clears the DataError interrupt sig */
+		readl(ccache_base + SIFIVE_CCACHE_DATECCFIX_COUNT);
+		atomic_notifier_call_chain(&ccache_err_chain, SIFIVE_CCACHE_ERR_TYPE_CE,
+					   "DatECCFix");
+	}
+	if (irq == g_irq[DATA_UNCORR]) {
+		add_h = readl(ccache_base + SIFIVE_CCACHE_DATECCFAIL_HIGH);
+		add_l = readl(ccache_base + SIFIVE_CCACHE_DATECCFAIL_LOW);
+		pr_err("CCACHE: DataFail @ 0x%08X.%08X\n", add_h, add_l);
+		/* Reading this register clears the DataFail interrupt sig */
+		readl(ccache_base + SIFIVE_CCACHE_DATECCFAIL_COUNT);
+		atomic_notifier_call_chain(&ccache_err_chain, SIFIVE_CCACHE_ERR_TYPE_UE,
+					   "DatECCFail");
+	}
+
+	return IRQ_HANDLED;
+}
+
+static int __init sifive_ccache_init(void)
+{
+	struct device_node *np;
+	struct resource res;
+	int i, rc;
+
+	np = of_find_matching_node(NULL, sifive_ccache_ids);
+	if (!np)
+		return -ENODEV;
+
+	if (of_address_to_resource(np, 0, &res))
+		return -ENODEV;
+
+	if (of_property_read_u32(np, "cache-level", &level))
+		return -ENODEV;
+
+	ccache_base = ioremap(res.start, resource_size(&res));
+	if (!ccache_base)
+		return -ENOMEM;
+
+	for (i = 0; i < SIFIVE_CCACHE_MAX_ECCINTR; i++) {
+		g_irq[i] = irq_of_parse_and_map(np, i);
+		rc = request_irq(g_irq[i], ccache_int_handler, 0, "ccache_ecc", NULL);
+		if (rc) {
+			pr_err("CCACHE: Could not request IRQ %d\n", g_irq[i]);
+			return rc;
+		}
+	}
+
+	ccache_config_read();
+
+	ccache_cache_ops.get_priv_group = ccache_get_priv_group;
+	riscv_set_cacheinfo_ops(&ccache_cache_ops);
+
+#ifdef CONFIG_DEBUG_FS
+	setup_sifive_debug();
+#endif
+	return 0;
+}
+device_initcall(sifive_ccache_init);
diff --git a/drivers/soc/sifive/sifive_l2_cache.c b/drivers/soc/sifive/sifive_l2_cache.c
deleted file mode 100644
index 59640a1d0b28..000000000000
--- a/drivers/soc/sifive/sifive_l2_cache.c
+++ /dev/null
@@ -1,237 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * SiFive L2 cache controller Driver
- *
- * Copyright (C) 2018-2019 SiFive, Inc.
- *
- */
-#include <linux/debugfs.h>
-#include <linux/interrupt.h>
-#include <linux/of_irq.h>
-#include <linux/of_address.h>
-#include <linux/device.h>
-#include <asm/cacheinfo.h>
-#include <soc/sifive/sifive_l2_cache.h>
-
-#define SIFIVE_L2_DIRECCFIX_LOW 0x100
-#define SIFIVE_L2_DIRECCFIX_HIGH 0x104
-#define SIFIVE_L2_DIRECCFIX_COUNT 0x108
-
-#define SIFIVE_L2_DIRECCFAIL_LOW 0x120
-#define SIFIVE_L2_DIRECCFAIL_HIGH 0x124
-#define SIFIVE_L2_DIRECCFAIL_COUNT 0x128
-
-#define SIFIVE_L2_DATECCFIX_LOW 0x140
-#define SIFIVE_L2_DATECCFIX_HIGH 0x144
-#define SIFIVE_L2_DATECCFIX_COUNT 0x148
-
-#define SIFIVE_L2_DATECCFAIL_LOW 0x160
-#define SIFIVE_L2_DATECCFAIL_HIGH 0x164
-#define SIFIVE_L2_DATECCFAIL_COUNT 0x168
-
-#define SIFIVE_L2_CONFIG 0x00
-#define SIFIVE_L2_WAYENABLE 0x08
-#define SIFIVE_L2_ECCINJECTERR 0x40
-
-#define SIFIVE_L2_MAX_ECCINTR 4
-
-static void __iomem *l2_base;
-static int g_irq[SIFIVE_L2_MAX_ECCINTR];
-static struct riscv_cacheinfo_ops l2_cache_ops;
-
-enum {
-	DIR_CORR = 0,
-	DATA_CORR,
-	DATA_UNCORR,
-	DIR_UNCORR,
-};
-
-#ifdef CONFIG_DEBUG_FS
-static struct dentry *sifive_test;
-
-static ssize_t l2_write(struct file *file, const char __user *data,
-			size_t count, loff_t *ppos)
-{
-	unsigned int val;
-
-	if (kstrtouint_from_user(data, count, 0, &val))
-		return -EINVAL;
-	if ((val < 0xFF) || (val >= 0x10000 && val < 0x100FF))
-		writel(val, l2_base + SIFIVE_L2_ECCINJECTERR);
-	else
-		return -EINVAL;
-	return count;
-}
-
-static const struct file_operations l2_fops = {
-	.owner = THIS_MODULE,
-	.open = simple_open,
-	.write = l2_write
-};
-
-static void setup_sifive_debug(void)
-{
-	sifive_test = debugfs_create_dir("sifive_l2_cache", NULL);
-
-	debugfs_create_file("sifive_debug_inject_error", 0200,
-			    sifive_test, NULL, &l2_fops);
-}
-#endif
-
-static void l2_config_read(void)
-{
-	u32 regval, val;
-
-	regval = readl(l2_base + SIFIVE_L2_CONFIG);
-	val = regval & 0xFF;
-	pr_info("L2CACHE: No. of Banks in the cache: %d\n", val);
-	val = (regval & 0xFF00) >> 8;
-	pr_info("L2CACHE: No. of ways per bank: %d\n", val);
-	val = (regval & 0xFF0000) >> 16;
-	pr_info("L2CACHE: Sets per bank: %llu\n", (uint64_t)1 << val);
-	val = (regval & 0xFF000000) >> 24;
-	pr_info("L2CACHE: Bytes per cache block: %llu\n", (uint64_t)1 << val);
-
-	regval = readl(l2_base + SIFIVE_L2_WAYENABLE);
-	pr_info("L2CACHE: Index of the largest way enabled: %d\n", regval);
-}
-
-static const struct of_device_id sifive_l2_ids[] = {
-	{ .compatible = "sifive,fu540-c000-ccache" },
-	{ .compatible = "sifive,fu740-c000-ccache" },
-	{ /* end of table */ },
-};
-
-static ATOMIC_NOTIFIER_HEAD(l2_err_chain);
-
-int register_sifive_l2_error_notifier(struct notifier_block *nb)
-{
-	return atomic_notifier_chain_register(&l2_err_chain, nb);
-}
-EXPORT_SYMBOL_GPL(register_sifive_l2_error_notifier);
-
-int unregister_sifive_l2_error_notifier(struct notifier_block *nb)
-{
-	return atomic_notifier_chain_unregister(&l2_err_chain, nb);
-}
-EXPORT_SYMBOL_GPL(unregister_sifive_l2_error_notifier);
-
-static int l2_largest_wayenabled(void)
-{
-	return readl(l2_base + SIFIVE_L2_WAYENABLE) & 0xFF;
-}
-
-static ssize_t number_of_ways_enabled_show(struct device *dev,
-					   struct device_attribute *attr,
-					   char *buf)
-{
-	return sprintf(buf, "%u\n", l2_largest_wayenabled());
-}
-
-static DEVICE_ATTR_RO(number_of_ways_enabled);
-
-static struct attribute *priv_attrs[] = {
-	&dev_attr_number_of_ways_enabled.attr,
-	NULL,
-};
-
-static const struct attribute_group priv_attr_group = {
-	.attrs = priv_attrs,
-};
-
-static const struct attribute_group *l2_get_priv_group(struct cacheinfo *this_leaf)
-{
-	/* We want to use private group for L2 cache only */
-	if (this_leaf->level == 2)
-		return &priv_attr_group;
-	else
-		return NULL;
-}
-
-static irqreturn_t l2_int_handler(int irq, void *device)
-{
-	unsigned int add_h, add_l;
-
-	if (irq == g_irq[DIR_CORR]) {
-		add_h = readl(l2_base + SIFIVE_L2_DIRECCFIX_HIGH);
-		add_l = readl(l2_base + SIFIVE_L2_DIRECCFIX_LOW);
-		pr_err("L2CACHE: DirError @ 0x%08X.%08X\n", add_h, add_l);
-		/* Reading this register clears the DirError interrupt sig */
-		readl(l2_base + SIFIVE_L2_DIRECCFIX_COUNT);
-		atomic_notifier_call_chain(&l2_err_chain, SIFIVE_L2_ERR_TYPE_CE,
-					   "DirECCFix");
-	}
-	if (irq == g_irq[DIR_UNCORR]) {
-		add_h = readl(l2_base + SIFIVE_L2_DIRECCFAIL_HIGH);
-		add_l = readl(l2_base + SIFIVE_L2_DIRECCFAIL_LOW);
-		/* Reading this register clears the DirFail interrupt sig */
-		readl(l2_base + SIFIVE_L2_DIRECCFAIL_COUNT);
-		atomic_notifier_call_chain(&l2_err_chain, SIFIVE_L2_ERR_TYPE_UE,
-					   "DirECCFail");
-		panic("L2CACHE: DirFail @ 0x%08X.%08X\n", add_h, add_l);
-	}
-	if (irq == g_irq[DATA_CORR]) {
-		add_h = readl(l2_base + SIFIVE_L2_DATECCFIX_HIGH);
-		add_l = readl(l2_base + SIFIVE_L2_DATECCFIX_LOW);
-		pr_err("L2CACHE: DataError @ 0x%08X.%08X\n", add_h, add_l);
-		/* Reading this register clears the DataError interrupt sig */
-		readl(l2_base + SIFIVE_L2_DATECCFIX_COUNT);
-		atomic_notifier_call_chain(&l2_err_chain, SIFIVE_L2_ERR_TYPE_CE,
-					   "DatECCFix");
-	}
-	if (irq == g_irq[DATA_UNCORR]) {
-		add_h = readl(l2_base + SIFIVE_L2_DATECCFAIL_HIGH);
-		add_l = readl(l2_base + SIFIVE_L2_DATECCFAIL_LOW);
-		pr_err("L2CACHE: DataFail @ 0x%08X.%08X\n", add_h, add_l);
-		/* Reading this register clears the DataFail interrupt sig */
-		readl(l2_base + SIFIVE_L2_DATECCFAIL_COUNT);
-		atomic_notifier_call_chain(&l2_err_chain, SIFIVE_L2_ERR_TYPE_UE,
-					   "DatECCFail");
-	}
-
-	return IRQ_HANDLED;
-}
-
-static int __init sifive_l2_init(void)
-{
-	struct device_node *np;
-	struct resource res;
-	int i, rc, intr_num;
-
-	np = of_find_matching_node(NULL, sifive_l2_ids);
-	if (!np)
-		return -ENODEV;
-
-	if (of_address_to_resource(np, 0, &res))
-		return -ENODEV;
-
-	l2_base = ioremap(res.start, resource_size(&res));
-	if (!l2_base)
-		return -ENOMEM;
-
-	intr_num = of_property_count_u32_elems(np, "interrupts");
-	if (!intr_num) {
-		pr_err("L2CACHE: no interrupts property\n");
-		return -ENODEV;
-	}
-
-	for (i = 0; i < intr_num; i++) {
-		g_irq[i] = irq_of_parse_and_map(np, i);
-		rc = request_irq(g_irq[i], l2_int_handler, 0, "l2_ecc", NULL);
-		if (rc) {
-			pr_err("L2CACHE: Could not request IRQ %d\n", g_irq[i]);
-			return rc;
-		}
-	}
-
-	l2_config_read();
-
-	l2_cache_ops.get_priv_group = l2_get_priv_group;
-	riscv_set_cacheinfo_ops(&l2_cache_ops);
-
-#ifdef CONFIG_DEBUG_FS
-	setup_sifive_debug();
-#endif
-	return 0;
-}
-device_initcall(sifive_l2_init);
diff --git a/include/soc/sifive/sifive_ccache.h b/include/soc/sifive/sifive_ccache.h
new file mode 100644
index 000000000000..16576d678ea8
--- /dev/null
+++ b/include/soc/sifive/sifive_ccache.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * SiFive composable Cache Controller header file
+ *
+ */
+
+#ifndef __SOC_SIFIVE_CCACHE_H
+#define __SOC_SIFIVE_CCACHE_H
+
+extern int register_sifive_ccache_error_notifier(struct notifier_block *nb);
+extern int unregister_sifive_ccache_error_notifier(struct notifier_block *nb);
+
+#define SIFIVE_CCACHE_ERR_TYPE_CE 0
+#define SIFIVE_CCACHE_ERR_TYPE_UE 1
+
+#endif /* __SOC_SIFIVE_CCACHE_H */
diff --git a/include/soc/sifive/sifive_l2_cache.h b/include/soc/sifive/sifive_l2_cache.h
deleted file mode 100644
index 92ade10ed67e..000000000000
--- a/include/soc/sifive/sifive_l2_cache.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * SiFive L2 Cache Controller header file
- *
- */
-
-#ifndef __SOC_SIFIVE_L2_CACHE_H
-#define __SOC_SIFIVE_L2_CACHE_H
-
-extern int register_sifive_l2_error_notifier(struct notifier_block *nb);
-extern int unregister_sifive_l2_error_notifier(struct notifier_block *nb);
-
-#define SIFIVE_L2_ERR_TYPE_CE 0
-#define SIFIVE_L2_ERR_TYPE_UE 1
-
-#endif /* __SOC_SIFIVE_L2_CACHE_H */
-- 
2.17.1

[PATCH 3/3] EDAC/sifive: use sifive_ccache instead of sifive_l2

[Zong Li]

The sifive L2 has been renamed to sifive CCACHE, EDAC driver needs to
apply the change as well

Signed-off-by: Zong Li <zong.li@sifive.com>
---
 drivers/edac/Kconfig       |  2 +-
 drivers/edac/sifive_edac.c | 12 ++++++------
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
index 17562cf1fe97..456602d373b7 100644
--- a/drivers/edac/Kconfig
+++ b/drivers/edac/Kconfig
@@ -473,7 +473,7 @@ config EDAC_ALTERA_SDMMC
 
 config EDAC_SIFIVE
 	bool "Sifive platform EDAC driver"
-	depends on EDAC=y && SIFIVE_L2
+	depends on EDAC=y && SIFIVE_CCACHE
 	help
 	  Support for error detection and correction on the SiFive SoCs.
 
diff --git a/drivers/edac/sifive_edac.c b/drivers/edac/sifive_edac.c
index ee800aec7d47..b844e2626fd5 100644
--- a/drivers/edac/sifive_edac.c
+++ b/drivers/edac/sifive_edac.c
@@ -2,7 +2,7 @@
 /*
  * SiFive Platform EDAC Driver
  *
- * Copyright (C) 2018-2019 SiFive, Inc.
+ * Copyright (C) 2018-2022 SiFive, Inc.
  *
  * This driver is partially based on octeon_edac-pc.c
  *
@@ -10,7 +10,7 @@
 #include <linux/edac.h>
 #include <linux/platform_device.h>
 #include "edac_module.h"
-#include <soc/sifive/sifive_l2_cache.h>
+#include <soc/sifive/sifive_ccache.h>
 
 #define DRVNAME "sifive_edac"
 
@@ -32,9 +32,9 @@ int ecc_err_event(struct notifier_block *this, unsigned long event, void *ptr)
 
 	p = container_of(this, struct sifive_edac_priv, notifier);
 
-	if (event == SIFIVE_L2_ERR_TYPE_UE)
+	if (event == SIFIVE_CCACHE_ERR_TYPE_UE)
 		edac_device_handle_ue(p->dci, 0, 0, msg);
-	else if (event == SIFIVE_L2_ERR_TYPE_CE)
+	else if (event == SIFIVE_CCACHE_ERR_TYPE_CE)
 		edac_device_handle_ce(p->dci, 0, 0, msg);
 
 	return NOTIFY_OK;
@@ -67,7 +67,7 @@ static int ecc_register(struct platform_device *pdev)
 		goto err;
 	}
 
-	register_sifive_l2_error_notifier(&p->notifier);
+	register_sifive_ccache_error_notifier(&p->notifier);
 
 	return 0;
 
@@ -81,7 +81,7 @@ static int ecc_unregister(struct platform_device *pdev)
 {
 	struct sifive_edac_priv *p = platform_get_drvdata(pdev);
 
-	unregister_sifive_l2_error_notifier(&p->notifier);
+	unregister_sifive_ccache_error_notifier(&p->notifier);
 	edac_device_del_device(&pdev->dev);
 	edac_device_free_ctl_info(p->dci);
 
-- 
2.17.1

Re: [PATCH 1/3] dt-bindings: sifive-ccache: rename SiFive L2 cache to composible cache

[Conor.Dooley]

Hey Zong,
Couple quick comments for you:

On 29/08/2022 07:22, Zong Li wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> Since composible cache may be L3 cache if private L2 cache exists, it

s/composible/composable

> should use its original name composible cache to prevent confusion.

s/composible/composable

> 
> Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
> Signed-off-by: Zong Li <zong.li@sifive.com>
> ---
>   .../riscv/{sifive-l2-cache.yaml => sifive-ccache.yaml}      | 6 ++++--
>   1 file changed, 4 insertions(+), 2 deletions(-)
>   rename Documentation/devicetree/bindings/riscv/{sifive-l2-cache.yaml => sifive-ccache.yaml} (92%)
> 
> diff --git a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml b/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml
> similarity index 92%
> rename from Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
> rename to Documentation/devicetree/bindings/riscv/sifive-ccache.yaml
> index 69cdab18d629..1a64a5384e36 100644
> --- a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
> +++ b/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml

Binding filenames are supposed to match the first compatible. Since
it was not named that way in the first place, I suppose naming after
the generic compatible makes the most sense. The correct filename
would then be "sifive,ccache0.yaml"

> @@ -12,8 +12,8 @@ maintainers:
>     - Paul Walmsley  <paul.walmsley@sifive.com>
> 
>   description:
> -  The SiFive Level 2 Cache Controller is used to provide access to fast copies
> -  of memory for masters in a Core Complex. The Level 2 Cache Controller also
> +  The SiFive Composable Cache Controller is used to provide access to fast copies
> +  of memory for masters in a Core Complex. The Composable Cache Controller also
>     acts as directory-based coherency manager.
>     All the properties in ePAPR/DeviceTree specification applies for this platform.
> 
> @@ -27,6 +27,7 @@ select:
>           enum:
>             - sifive,fu540-c000-ccache
>             - sifive,fu740-c000-ccache
> +          - sifive,ccache0

Despite what the commit message says, this is more than a rename.
Thanks,
Conor.

> 
>     required:
>       - compatible
> @@ -37,6 +38,7 @@ properties:
>         - enum:
>             - sifive,fu540-c000-ccache
>             - sifive,fu740-c000-ccache
> +          - sifive,ccache0
>         - const: cache
> 
>     cache-block-size:
> --
> 2.17.1
> 

Re: [PATCH 2/3] soc: sifive: l2 cache: Rename SiFive L2 cache to composible cache.

[Conor.Dooley]

Hey Zong,

On 29/08/2022 07:22, Zong Li wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> From: Greentime Hu <greentime.hu@sifive.com>
> 
> Since composible cache may be L3 cache if pL2 cache exists, we should use
> its original name composible cache to prevent confusion.
> 
> Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
> Signed-off-by: Zong Li <zong.li@sifive.com>
> ---
>   drivers/soc/sifive/Kconfig           |   7 +-
>   drivers/soc/sifive/Makefile          |   2 +-
>   drivers/soc/sifive/sifive_ccache.c   | 221 +++++++++++++++++++++++++
>   drivers/soc/sifive/sifive_l2_cache.c | 237 ---------------------------

Where did the 16 lines go? Could you please split renames off from any
other changes so that it is easier to see what has changed?

>   include/soc/sifive/sifive_ccache.h   |  16 ++
>   include/soc/sifive/sifive_l2_cache.h |  16 --
>   6 files changed, 242 insertions(+), 257 deletions(-)
>   create mode 100644 drivers/soc/sifive/sifive_ccache.c
>   delete mode 100644 drivers/soc/sifive/sifive_l2_cache.c
>   create mode 100644 include/soc/sifive/sifive_ccache.h
>   delete mode 100644 include/soc/sifive/sifive_l2_cache.h
> 
> diff --git a/drivers/soc/sifive/Kconfig b/drivers/soc/sifive/Kconfig
> index 58cf8c40d08d..3d65d2771f9a 100644
> --- a/drivers/soc/sifive/Kconfig
> +++ b/drivers/soc/sifive/Kconfig
> @@ -2,9 +2,10 @@
> 
>   if SOC_SIFIVE
> 
> -config SIFIVE_L2
> -       bool "Sifive L2 Cache controller"
> +config SIFIVE_CCACHE
> +       bool "Sifive composable Cache controller"
> +       default y

Changing this to default on is not a rename of the file..
This should be in a different patch.

>          help
> -         Support for the L2 cache controller on SiFive platforms.
> +         Support for the composable cache controller on SiFive platforms.
> 
>   endif
> diff --git a/drivers/soc/sifive/Makefile b/drivers/soc/sifive/Makefile
> index b5caff77938f..1f5dc339bf82 100644
> --- a/drivers/soc/sifive/Makefile
> +++ b/drivers/soc/sifive/Makefile
> @@ -1,3 +1,3 @@
>   # SPDX-License-Identifier: GPL-2.0
> 
> -obj-$(CONFIG_SIFIVE_L2)        += sifive_l2_cache.o
> +obj-$(CONFIG_SIFIVE_CCACHE)    += sifive_ccache.o
> diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c
> new file mode 100644
> index 000000000000..46ce33db7d30
> --- /dev/null
> +++ b/drivers/soc/sifive/sifive_ccache.c
> @@ -0,0 +1,221 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * SiFive composable cache controller Driver
> + *
> + * Copyright (C) 2018-2019 SiFive, Inc.
> + *
> + */
> +#include <linux/debugfs.h>
> +#include <linux/interrupt.h>
> +#include <linux/of_irq.h>
> +#include <linux/of_address.h>
> +#include <linux/device.h>
> +#include <asm/cacheinfo.h>
> +#include <soc/sifive/sifive_ccache.h>
> +
> +#define SIFIVE_CCACHE_DIRECCFIX_LOW 0x100
> +#define SIFIVE_CCACHE_DIRECCFIX_HIGH 0x104
> +#define SIFIVE_CCACHE_DIRECCFIX_COUNT 0x108
> +
> +#define SIFIVE_CCACHE_DATECCFIX_LOW 0x140
> +#define SIFIVE_CCACHE_DATECCFIX_HIGH 0x144
> +#define SIFIVE_CCACHE_DATECCFIX_COUNT 0x148
> +
> +#define SIFIVE_CCACHE_DATECCFAIL_LOW 0x160
> +#define SIFIVE_CCACHE_DATECCFAIL_HIGH 0x164
> +#define SIFIVE_CCACHE_DATECCFAIL_COUNT 0x168
> +
> +#define SIFIVE_CCACHE_CONFIG 0x00
> +#define SIFIVE_CCACHE_WAYENABLE 0x08
> +#define SIFIVE_CCACHE_ECCINJECTERR 0x40

 From what I can see, you've also changed these around too?
Please generate the patch's diff so that the rename is detected & the
diff shows only what changed in the file. The -M option is what you
are looking for.

I have a couple other comments to make about what's changed here other,
thatn the rename but I will do so against a v2 where the diff is usable.

Thanks,
Conor.

> +
> +#define SIFIVE_CCACHE_MAX_ECCINTR 3

Re: [PATCH 1/3] dt-bindings: sifive-ccache: rename SiFive L2 cache to composible cache

[Zong Li]

On Mon, Aug 29, 2022 at 2:45 PM <Conor.Dooley@microchip.com> wrote:
>
> Hey Zong,
> Couple quick comments for you:
>
> On 29/08/2022 07:22, Zong Li wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >
> > Since composible cache may be L3 cache if private L2 cache exists, it
>
> s/composible/composable
>
> > should use its original name composible cache to prevent confusion.
>
> s/composible/composable
>

I will fix it in each patch.

> >
> > Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
> > Signed-off-by: Zong Li <zong.li@sifive.com>
> > ---
> >   .../riscv/{sifive-l2-cache.yaml => sifive-ccache.yaml}      | 6 ++++--
> >   1 file changed, 4 insertions(+), 2 deletions(-)
> >   rename Documentation/devicetree/bindings/riscv/{sifive-l2-cache.yaml => sifive-ccache.yaml} (92%)
> >
> > diff --git a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml b/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml
> > similarity index 92%
> > rename from Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
> > rename to Documentation/devicetree/bindings/riscv/sifive-ccache.yaml
> > index 69cdab18d629..1a64a5384e36 100644
> > --- a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
> > +++ b/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml
>
> Binding filenames are supposed to match the first compatible. Since
> it was not named that way in the first place, I suppose naming after
> the generic compatible makes the most sense. The correct filename
> would then be "sifive,ccache0.yaml"
>

Thanks for pointing this out. Let me change the filename.

> > @@ -12,8 +12,8 @@ maintainers:
> >     - Paul Walmsley  <paul.walmsley@sifive.com>
> >
> >   description:
> > -  The SiFive Level 2 Cache Controller is used to provide access to fast copies
> > -  of memory for masters in a Core Complex. The Level 2 Cache Controller also
> > +  The SiFive Composable Cache Controller is used to provide access to fast copies
> > +  of memory for masters in a Core Complex. The Composable Cache Controller also
> >     acts as directory-based coherency manager.
> >     All the properties in ePAPR/DeviceTree specification applies for this platform.
> >
> > @@ -27,6 +27,7 @@ select:
> >           enum:
> >             - sifive,fu540-c000-ccache
> >             - sifive,fu740-c000-ccache
> > +          - sifive,ccache0
>
> Despite what the commit message says, this is more than a rename.
> Thanks,
> Conor.
>
> >
> >     required:
> >       - compatible
> > @@ -37,6 +38,7 @@ properties:
> >         - enum:
> >             - sifive,fu540-c000-ccache
> >             - sifive,fu740-c000-ccache
> > +          - sifive,ccache0
> >         - const: cache
> >
> >     cache-block-size:
> > --
> > 2.17.1
> >
>

Re: [PATCH 2/3] soc: sifive: l2 cache: Rename SiFive L2 cache to composible cache.

[Zong Li]

On Mon, Aug 29, 2022 at 3:05 PM <Conor.Dooley@microchip.com> wrote:
>
> Hey Zong,
>
> On 29/08/2022 07:22, Zong Li wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >
> > From: Greentime Hu <greentime.hu@sifive.com>
> >
> > Since composible cache may be L3 cache if pL2 cache exists, we should use
> > its original name composible cache to prevent confusion.
> >
> > Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
> > Signed-off-by: Zong Li <zong.li@sifive.com>
> > ---
> >   drivers/soc/sifive/Kconfig           |   7 +-
> >   drivers/soc/sifive/Makefile          |   2 +-
> >   drivers/soc/sifive/sifive_ccache.c   | 221 +++++++++++++++++++++++++
> >   drivers/soc/sifive/sifive_l2_cache.c | 237 ---------------------------
>
> Where did the 16 lines go? Could you please split renames off from any
> other changes so that it is easier to see what has changed?

As your suggestion, we should separate the difference from this patch

>
> >   include/soc/sifive/sifive_ccache.h   |  16 ++
> >   include/soc/sifive/sifive_l2_cache.h |  16 --
> >   6 files changed, 242 insertions(+), 257 deletions(-)
> >   create mode 100644 drivers/soc/sifive/sifive_ccache.c
> >   delete mode 100644 drivers/soc/sifive/sifive_l2_cache.c
> >   create mode 100644 include/soc/sifive/sifive_ccache.h
> >   delete mode 100644 include/soc/sifive/sifive_l2_cache.h
> >
> > diff --git a/drivers/soc/sifive/Kconfig b/drivers/soc/sifive/Kconfig
> > index 58cf8c40d08d..3d65d2771f9a 100644
> > --- a/drivers/soc/sifive/Kconfig
> > +++ b/drivers/soc/sifive/Kconfig
> > @@ -2,9 +2,10 @@
> >
> >   if SOC_SIFIVE
> >
> > -config SIFIVE_L2
> > -       bool "Sifive L2 Cache controller"
> > +config SIFIVE_CCACHE
> > +       bool "Sifive composable Cache controller"
> > +       default y
>
> Changing this to default on is not a rename of the file..
> This should be in a different patch.

Okay, let me separate it to another patch, but I guess we could remove
it, and enable it by user. What is your perspective on it?

>
> >          help
> > -         Support for the L2 cache controller on SiFive platforms.
> > +         Support for the composable cache controller on SiFive platforms.
> >
> >   endif
> > diff --git a/drivers/soc/sifive/Makefile b/drivers/soc/sifive/Makefile
> > index b5caff77938f..1f5dc339bf82 100644
> > --- a/drivers/soc/sifive/Makefile
> > +++ b/drivers/soc/sifive/Makefile
> > @@ -1,3 +1,3 @@
> >   # SPDX-License-Identifier: GPL-2.0
> >
> > -obj-$(CONFIG_SIFIVE_L2)        += sifive_l2_cache.o
> > +obj-$(CONFIG_SIFIVE_CCACHE)    += sifive_ccache.o
> > diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c
> > new file mode 100644
> > index 000000000000..46ce33db7d30
> > --- /dev/null
> > +++ b/drivers/soc/sifive/sifive_ccache.c
> > @@ -0,0 +1,221 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * SiFive composable cache controller Driver
> > + *
> > + * Copyright (C) 2018-2019 SiFive, Inc.
> > + *
> > + */
> > +#include <linux/debugfs.h>
> > +#include <linux/interrupt.h>
> > +#include <linux/of_irq.h>
> > +#include <linux/of_address.h>
> > +#include <linux/device.h>
> > +#include <asm/cacheinfo.h>
> > +#include <soc/sifive/sifive_ccache.h>
> > +
> > +#define SIFIVE_CCACHE_DIRECCFIX_LOW 0x100
> > +#define SIFIVE_CCACHE_DIRECCFIX_HIGH 0x104
> > +#define SIFIVE_CCACHE_DIRECCFIX_COUNT 0x108
> > +
> > +#define SIFIVE_CCACHE_DATECCFIX_LOW 0x140
> > +#define SIFIVE_CCACHE_DATECCFIX_HIGH 0x144
> > +#define SIFIVE_CCACHE_DATECCFIX_COUNT 0x148
> > +
> > +#define SIFIVE_CCACHE_DATECCFAIL_LOW 0x160
> > +#define SIFIVE_CCACHE_DATECCFAIL_HIGH 0x164
> > +#define SIFIVE_CCACHE_DATECCFAIL_COUNT 0x168
> > +
> > +#define SIFIVE_CCACHE_CONFIG 0x00
> > +#define SIFIVE_CCACHE_WAYENABLE 0x08
> > +#define SIFIVE_CCACHE_ECCINJECTERR 0x40
>
>  From what I can see, you've also changed these around too?
> Please generate the patch's diff so that the rename is detected & the
> diff shows only what changed in the file. The -M option is what you
> are looking for.
>
> I have a couple other comments to make about what's changed here other,
> thatn the rename but I will do so against a v2 where the diff is usable.
>

Let me sent the v2 patch, and separate the rename and diff part

> Thanks,
> Conor.
>
> > +
> > +#define SIFIVE_CCACHE_MAX_ECCINTR 3

Re: [PATCH 1/3] dt-bindings: sifive-ccache: rename SiFive L2 cache to composible cache

[Rob Herring]

On Mon, 29 Aug 2022 06:22:00 +0000, Zong Li wrote:
> Since composible cache may be L3 cache if private L2 cache exists, it
> should use its original name composible cache to prevent confusion.
> 
> Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
> Signed-off-by: Zong Li <zong.li@sifive.com>
> ---
>  .../riscv/{sifive-l2-cache.yaml => sifive-ccache.yaml}      | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)
>  rename Documentation/devicetree/bindings/riscv/{sifive-l2-cache.yaml => sifive-ccache.yaml} (92%)
> 

My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):

yamllint warnings/errors:

dtschema/dtc warnings/errors:
./Documentation/devicetree/bindings/riscv/sifive-ccache.yaml: $id: relative path/filename doesn't match actual path or filename
	expected: http://devicetree.org/schemas/riscv/sifive-ccache.yaml#

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/patch/

This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit.

Re: [PATCH 1/3] dt-bindings: sifive-ccache: rename SiFive L2 cache to composible cache

[Zong Li]

On Tue, Aug 30, 2022 at 2:42 AM Rob Herring <robh@kernel.org> wrote:
>
> On Mon, 29 Aug 2022 06:22:00 +0000, Zong Li wrote:
> > Since composible cache may be L3 cache if private L2 cache exists, it
> > should use its original name composible cache to prevent confusion.
> >
> > Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
> > Signed-off-by: Zong Li <zong.li@sifive.com>
> > ---
> >  .../riscv/{sifive-l2-cache.yaml => sifive-ccache.yaml}      | 6 ++++--
> >  1 file changed, 4 insertions(+), 2 deletions(-)
> >  rename Documentation/devicetree/bindings/riscv/{sifive-l2-cache.yaml => sifive-ccache.yaml} (92%)
> >
>
> My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
> on your patch (DT_CHECKER_FLAGS is new in v5.13):
>
> yamllint warnings/errors:
>
> dtschema/dtc warnings/errors:
> ./Documentation/devicetree/bindings/riscv/sifive-ccache.yaml: $id: relative path/filename doesn't match actual path or filename
>         expected: http://devicetree.org/schemas/riscv/sifive-ccache.yaml#
>
> doc reference errors (make refcheckdocs):
>
> See https://patchwork.ozlabs.org/patch/
>
> This check can fail if there are any dependencies. The base for a patch
> series is generally the most recent rc1.
>
> If you already ran 'make dt_binding_check' and didn't see the above
> error(s), then make sure 'yamllint' is installed and dt-schema is up to
> date:
>
> pip3 install dtschema --upgrade
>
> Please check and re-submit.
>

Thanks for the tips, I would upgrade my environment and try it again.

Re: [PATCH 0/3] Rename sifive L2 cache to sifive CCACHE

[Ben Dooks]

On 29/08/2022 07:21, Zong Li wrote:
> Since composible cache may be L3 cache if private L2 cache exists, we
> should use its original name "composible cache" to prevent confusion.
> 
> This patchset contains the modification which is related to ccache, such
> as DT binding and EDAC driver.
> 
> Greentime Hu (1):
>    soc: sifive: l2 cache: Rename SiFive L2 cache to composible cache.
> 
> Zong Li (2):
>    dt-bindings: sifive-ccache: rename SiFive L2 cache to composible cache
>    EDAC/sifive: use sifive_ccache instead of sifive_l2
> 
>   ...ifive-l2-cache.yaml => sifive-ccache.yaml} |   6 +-
>   drivers/edac/Kconfig                          |   2 +-
>   drivers/edac/sifive_edac.c                    |  12 +-
>   drivers/soc/sifive/Kconfig                    |   7 +-
>   drivers/soc/sifive/Makefile                   |   2 +-
>   drivers/soc/sifive/sifive_ccache.c            | 221 ++++++++++++++++
>   drivers/soc/sifive/sifive_l2_cache.c          | 237 ------------------
>   include/soc/sifive/sifive_ccache.h            |  16 ++
>   include/soc/sifive/sifive_l2_cache.h          |  16 --
>   9 files changed, 253 insertions(+), 266 deletions(-)
>   rename Documentation/devicetree/bindings/riscv/{sifive-l2-cache.yaml => sifive-ccache.yaml} (92%)
>   create mode 100644 drivers/soc/sifive/sifive_ccache.c
>   delete mode 100644 drivers/soc/sifive/sifive_l2_cache.c
>   create mode 100644 include/soc/sifive/sifive_ccache.h
>   delete mode 100644 include/soc/sifive/sifive_l2_cache.h

Is this series available on a git branch anywhere, I have at least
one other cleanup I was doing in a similar move to rename and make
it usable as the l3 cache.

I gave the series a quick review and did not find any issues so far.

-- 
Ben

Re: [PATCH 2/3] soc: sifive: l2 cache: Rename SiFive L2 cache to composible cache.

[Ben Dooks]

On 29/08/2022 07:22, Zong Li wrote:
> From: Greentime Hu <greentime.hu@sifive.com>
> 
> Since composible cache may be L3 cache if pL2 cache exists, we should use
> its original name composible cache to prevent confusion.

You probably should have noted in this that you also read the cache
level property to work out if this is an l2 or l3 cache.

> 
> Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
> Signed-off-by: Zong Li <zong.li@sifive.com>
> ---
>   drivers/soc/sifive/Kconfig           |   7 +-
>   drivers/soc/sifive/Makefile          |   2 +-
>   drivers/soc/sifive/sifive_ccache.c   | 221 +++++++++++++++++++++++++
>   drivers/soc/sifive/sifive_l2_cache.c | 237 ---------------------------
>   include/soc/sifive/sifive_ccache.h   |  16 ++
>   include/soc/sifive/sifive_l2_cache.h |  16 --
>   6 files changed, 242 insertions(+), 257 deletions(-)
>   create mode 100644 drivers/soc/sifive/sifive_ccache.c
>   delete mode 100644 drivers/soc/sifive/sifive_l2_cache.c
>   create mode 100644 include/soc/sifive/sifive_ccache.h
>   delete mode 100644 include/soc/sifive/sifive_l2_cache.h
> 
> diff --git a/drivers/soc/sifive/Kconfig b/drivers/soc/sifive/Kconfig
> index 58cf8c40d08d..3d65d2771f9a 100644
> --- a/drivers/soc/sifive/Kconfig
> +++ b/drivers/soc/sifive/Kconfig
> @@ -2,9 +2,10 @@
>   
>   if SOC_SIFIVE
>   
> -config SIFIVE_L2
> -	bool "Sifive L2 Cache controller"
> +config SIFIVE_CCACHE
> +	bool "Sifive composable Cache controller"
> +	default y
>   	help
> -	  Support for the L2 cache controller on SiFive platforms.
> +	  Support for the composable cache controller on SiFive platforms.
>   
>   endif
> diff --git a/drivers/soc/sifive/Makefile b/drivers/soc/sifive/Makefile
> index b5caff77938f..1f5dc339bf82 100644
> --- a/drivers/soc/sifive/Makefile
> +++ b/drivers/soc/sifive/Makefile
> @@ -1,3 +1,3 @@
>   # SPDX-License-Identifier: GPL-2.0
>   
> -obj-$(CONFIG_SIFIVE_L2)	+= sifive_l2_cache.o
> +obj-$(CONFIG_SIFIVE_CCACHE)	+= sifive_ccache.o
> diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c
> new file mode 100644
> index 000000000000..46ce33db7d30
> --- /dev/null
> +++ b/drivers/soc/sifive/sifive_ccache.c
> @@ -0,0 +1,221 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * SiFive composable cache controller Driver
> + *
> + * Copyright (C) 2018-2019 SiFive, Inc.
> + *
> + */
> +#include <linux/debugfs.h>
> +#include <linux/interrupt.h>
> +#include <linux/of_irq.h>
> +#include <linux/of_address.h>
> +#include <linux/device.h>
> +#include <asm/cacheinfo.h>
> +#include <soc/sifive/sifive_ccache.h>
> +
> +#define SIFIVE_CCACHE_DIRECCFIX_LOW 0x100
> +#define SIFIVE_CCACHE_DIRECCFIX_HIGH 0x104
> +#define SIFIVE_CCACHE_DIRECCFIX_COUNT 0x108
> +
> +#define SIFIVE_CCACHE_DATECCFIX_LOW 0x140
> +#define SIFIVE_CCACHE_DATECCFIX_HIGH 0x144
> +#define SIFIVE_CCACHE_DATECCFIX_COUNT 0x148
> +
> +#define SIFIVE_CCACHE_DATECCFAIL_LOW 0x160
> +#define SIFIVE_CCACHE_DATECCFAIL_HIGH 0x164
> +#define SIFIVE_CCACHE_DATECCFAIL_COUNT 0x168
> +
> +#define SIFIVE_CCACHE_CONFIG 0x00
> +#define SIFIVE_CCACHE_WAYENABLE 0x08
> +#define SIFIVE_CCACHE_ECCINJECTERR 0x40
> +
> +#define SIFIVE_CCACHE_MAX_ECCINTR 3
> +
> +static void __iomem *ccache_base;
> +static int level;
> +static int g_irq[SIFIVE_CCACHE_MAX_ECCINTR];
> +static struct riscv_cacheinfo_ops ccache_cache_ops;
> +
> +enum {
> +	DIR_CORR = 0,
> +	DATA_CORR,
> +	DATA_UNCORR,
> +};
> +
> +#ifdef CONFIG_DEBUG_FS
> +static struct dentry *sifive_test;
> +
> +static ssize_t ccache_write(struct file *file, const char __user *data,
> +			size_t count, loff_t *ppos)
> +{
> +	unsigned int val;
> +
> +	if (kstrtouint_from_user(data, count, 0, &val))
> +		return -EINVAL;
> +	if ((val < 0xFF) || (val >= 0x10000 && val < 0x100FF))
> +		writel(val, ccache_base + SIFIVE_CCACHE_ECCINJECTERR);
> +	else
> +		return -EINVAL;
> +	return count;
> +}
> +
> +static const struct file_operations ccache_fops = {
> +	.owner = THIS_MODULE,
> +	.open = simple_open,
> +	.write = ccache_write
> +};
> +
> +static void setup_sifive_debug(void)
> +{
> +	sifive_test = debugfs_create_dir("sifive_ccache_cache", NULL);
> +
> +	debugfs_create_file("sifive_debug_inject_error", 0200,
> +			    sifive_test, NULL, &ccache_fops);
> +}
> +#endif
> +
> +static void ccache_config_read(void)
> +{
> +	u32 regval, val;
> +
> +	regval = readl(ccache_base + SIFIVE_CCACHE_CONFIG);
> +	val = regval & 0xFF;
> +	pr_info("CCACHE: No. of Banks in the cache: %d\n", val);
> +	val = (regval & 0xFF00) >> 8;
> +	pr_info("CCACHE: No. of ways per bank: %d\n", val);
> +	val = (regval & 0xFF0000) >> 16;
> +	pr_info("CCACHE: Sets per bank: %llu\n", (uint64_t)1 << val);
> +	val = (regval & 0xFF000000) >> 24;
> +	pr_info("CCACHE: Bytes per cache block: %llu\n", (uint64_t)1 << val);
> +
> +	regval = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE);
> +	pr_info("CCACHE: Index of the largest way enabled: %d\n", regval);
> +}
> +
> +static const struct of_device_id sifive_ccache_ids[] = {
> +	{ .compatible = "sifive,fu540-c000-ccache" },
> +	{ .compatible = "sifive,ccache0" },
> +	{ /* end of table */ },
> +};
> +
> +static ATOMIC_NOTIFIER_HEAD(ccache_err_chain);
> +
> +int register_sifive_ccache_error_notifier(struct notifier_block *nb)
> +{
> +	return atomic_notifier_chain_register(&ccache_err_chain, nb);
> +}
> +EXPORT_SYMBOL_GPL(register_sifive_ccache_error_notifier);
> +
> +int unregister_sifive_ccache_error_notifier(struct notifier_block *nb)
> +{
> +	return atomic_notifier_chain_unregister(&ccache_err_chain, nb);
> +}
> +EXPORT_SYMBOL_GPL(unregister_sifive_ccache_error_notifier);
> +
> +static int ccache_largest_wayenabled(void)
> +{
> +	return readl(ccache_base + SIFIVE_CCACHE_WAYENABLE) & 0xFF;
> +}
> +
> +static ssize_t number_of_ways_enabled_show(struct device *dev,
> +					   struct device_attribute *attr,
> +					   char *buf)
> +{
> +	return sprintf(buf, "%u\n", ccache_largest_wayenabled());
> +}
> +
> +static DEVICE_ATTR_RO(number_of_ways_enabled);
> +
> +static struct attribute *priv_attrs[] = {
> +	&dev_attr_number_of_ways_enabled.attr,
> +	NULL,
> +};
> +
> +static const struct attribute_group priv_attr_group = {
> +	.attrs = priv_attrs,
> +};
> +
> +static const struct attribute_group *ccache_get_priv_group(struct cacheinfo *this_leaf)
> +{
> +	/* We want to use private group for composable cache only */
> +	if (this_leaf->level == level)
> +		return &priv_attr_group;
> +	else
> +		return NULL;
> +}
> +
> +static irqreturn_t ccache_int_handler(int irq, void *device)
> +{
> +	unsigned int add_h, add_l;
> +
> +	if (irq == g_irq[DIR_CORR]) {
> +		add_h = readl(ccache_base + SIFIVE_CCACHE_DIRECCFIX_HIGH);
> +		add_l = readl(ccache_base + SIFIVE_CCACHE_DIRECCFIX_LOW);
> +		pr_err("CCACHE: DirError @ 0x%08X.%08X\n", add_h, add_l);
> +		/* Reading this register clears the DirError interrupt sig */
> +		readl(ccache_base + SIFIVE_CCACHE_DIRECCFIX_COUNT);
> +		atomic_notifier_call_chain(&ccache_err_chain, SIFIVE_CCACHE_ERR_TYPE_CE,
> +					   "DirECCFix");
> +	}
> +	if (irq == g_irq[DATA_CORR]) {
> +		add_h = readl(ccache_base + SIFIVE_CCACHE_DATECCFIX_HIGH);
> +		add_l = readl(ccache_base + SIFIVE_CCACHE_DATECCFIX_LOW);
> +		pr_err("CCACHE: DataError @ 0x%08X.%08X\n", add_h, add_l);
> +		/* Reading this register clears the DataError interrupt sig */
> +		readl(ccache_base + SIFIVE_CCACHE_DATECCFIX_COUNT);
> +		atomic_notifier_call_chain(&ccache_err_chain, SIFIVE_CCACHE_ERR_TYPE_CE,
> +					   "DatECCFix");
> +	}
> +	if (irq == g_irq[DATA_UNCORR]) {
> +		add_h = readl(ccache_base + SIFIVE_CCACHE_DATECCFAIL_HIGH);
> +		add_l = readl(ccache_base + SIFIVE_CCACHE_DATECCFAIL_LOW);
> +		pr_err("CCACHE: DataFail @ 0x%08X.%08X\n", add_h, add_l);
> +		/* Reading this register clears the DataFail interrupt sig */
> +		readl(ccache_base + SIFIVE_CCACHE_DATECCFAIL_COUNT);
> +		atomic_notifier_call_chain(&ccache_err_chain, SIFIVE_CCACHE_ERR_TYPE_UE,
> +					   "DatECCFail");
> +	}
> +
> +	return IRQ_HANDLED;
> +}
> +
> +static int __init sifive_ccache_init(void)
> +{
> +	struct device_node *np;
> +	struct resource res;
> +	int i, rc;
> +
> +	np = of_find_matching_node(NULL, sifive_ccache_ids);
> +	if (!np)
> +		return -ENODEV;
> +
> +	if (of_address_to_resource(np, 0, &res))
> +		return -ENODEV;
> +
> +	if (of_property_read_u32(np, "cache-level", &level))
> +		return -ENODEV;
> +
> +	ccache_base = ioremap(res.start, resource_size(&res));
> +	if (!ccache_base)
> +		return -ENOMEM;
> +
> +	for (i = 0; i < SIFIVE_CCACHE_MAX_ECCINTR; i++) {
> +		g_irq[i] = irq_of_parse_and_map(np, i);
> +		rc = request_irq(g_irq[i], ccache_int_handler, 0, "ccache_ecc", NULL);
> +		if (rc) {
> +			pr_err("CCACHE: Could not request IRQ %d\n", g_irq[i]);
> +			return rc;
> +		}
> +	}
> +
> +	ccache_config_read();
> +
> +	ccache_cache_ops.get_priv_group = ccache_get_priv_group;
> +	riscv_set_cacheinfo_ops(&ccache_cache_ops);
> +
> +#ifdef CONFIG_DEBUG_FS
> +	setup_sifive_debug();
> +#endif
> +	return 0;
> +}
> +device_initcall(sifive_ccache_init);
> diff --git a/drivers/soc/sifive/sifive_l2_cache.c b/drivers/soc/sifive/sifive_l2_cache.c
> deleted file mode 100644
> index 59640a1d0b28..000000000000
> --- a/drivers/soc/sifive/sifive_l2_cache.c
> +++ /dev/null
> @@ -1,237 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0
> -/*
> - * SiFive L2 cache controller Driver
> - *
> - * Copyright (C) 2018-2019 SiFive, Inc.
> - *
> - */
> -#include <linux/debugfs.h>
> -#include <linux/interrupt.h>
> -#include <linux/of_irq.h>
> -#include <linux/of_address.h>
> -#include <linux/device.h>
> -#include <asm/cacheinfo.h>
> -#include <soc/sifive/sifive_l2_cache.h>
> -
> -#define SIFIVE_L2_DIRECCFIX_LOW 0x100
> -#define SIFIVE_L2_DIRECCFIX_HIGH 0x104
> -#define SIFIVE_L2_DIRECCFIX_COUNT 0x108
> -
> -#define SIFIVE_L2_DIRECCFAIL_LOW 0x120
> -#define SIFIVE_L2_DIRECCFAIL_HIGH 0x124
> -#define SIFIVE_L2_DIRECCFAIL_COUNT 0x128
> -
> -#define SIFIVE_L2_DATECCFIX_LOW 0x140
> -#define SIFIVE_L2_DATECCFIX_HIGH 0x144
> -#define SIFIVE_L2_DATECCFIX_COUNT 0x148
> -
> -#define SIFIVE_L2_DATECCFAIL_LOW 0x160
> -#define SIFIVE_L2_DATECCFAIL_HIGH 0x164
> -#define SIFIVE_L2_DATECCFAIL_COUNT 0x168
> -
> -#define SIFIVE_L2_CONFIG 0x00
> -#define SIFIVE_L2_WAYENABLE 0x08
> -#define SIFIVE_L2_ECCINJECTERR 0x40
> -
> -#define SIFIVE_L2_MAX_ECCINTR 4
> -
> -static void __iomem *l2_base;
> -static int g_irq[SIFIVE_L2_MAX_ECCINTR];
> -static struct riscv_cacheinfo_ops l2_cache_ops;
> -
> -enum {
> -	DIR_CORR = 0,
> -	DATA_CORR,
> -	DATA_UNCORR,
> -	DIR_UNCORR,
> -};
> -
> -#ifdef CONFIG_DEBUG_FS
> -static struct dentry *sifive_test;
> -
> -static ssize_t l2_write(struct file *file, const char __user *data,
> -			size_t count, loff_t *ppos)
> -{
> -	unsigned int val;
> -
> -	if (kstrtouint_from_user(data, count, 0, &val))
> -		return -EINVAL;
> -	if ((val < 0xFF) || (val >= 0x10000 && val < 0x100FF))
> -		writel(val, l2_base + SIFIVE_L2_ECCINJECTERR);
> -	else
> -		return -EINVAL;
> -	return count;
> -}
> -
> -static const struct file_operations l2_fops = {
> -	.owner = THIS_MODULE,
> -	.open = simple_open,
> -	.write = l2_write
> -};
> -
> -static void setup_sifive_debug(void)
> -{
> -	sifive_test = debugfs_create_dir("sifive_l2_cache", NULL);
> -
> -	debugfs_create_file("sifive_debug_inject_error", 0200,
> -			    sifive_test, NULL, &l2_fops);
> -}
> -#endif
> -
> -static void l2_config_read(void)
> -{
> -	u32 regval, val;
> -
> -	regval = readl(l2_base + SIFIVE_L2_CONFIG);
> -	val = regval & 0xFF;
> -	pr_info("L2CACHE: No. of Banks in the cache: %d\n", val);
> -	val = (regval & 0xFF00) >> 8;
> -	pr_info("L2CACHE: No. of ways per bank: %d\n", val);
> -	val = (regval & 0xFF0000) >> 16;
> -	pr_info("L2CACHE: Sets per bank: %llu\n", (uint64_t)1 << val);
> -	val = (regval & 0xFF000000) >> 24;
> -	pr_info("L2CACHE: Bytes per cache block: %llu\n", (uint64_t)1 << val);
> -
> -	regval = readl(l2_base + SIFIVE_L2_WAYENABLE);
> -	pr_info("L2CACHE: Index of the largest way enabled: %d\n", regval);
> -}
> -
> -static const struct of_device_id sifive_l2_ids[] = {
> -	{ .compatible = "sifive,fu540-c000-ccache" },
> -	{ .compatible = "sifive,fu740-c000-ccache" },
> -	{ /* end of table */ },
> -};
> -
> -static ATOMIC_NOTIFIER_HEAD(l2_err_chain);
> -
> -int register_sifive_l2_error_notifier(struct notifier_block *nb)
> -{
> -	return atomic_notifier_chain_register(&l2_err_chain, nb);
> -}
> -EXPORT_SYMBOL_GPL(register_sifive_l2_error_notifier);
> -
> -int unregister_sifive_l2_error_notifier(struct notifier_block *nb)
> -{
> -	return atomic_notifier_chain_unregister(&l2_err_chain, nb);
> -}
> -EXPORT_SYMBOL_GPL(unregister_sifive_l2_error_notifier);
> -
> -static int l2_largest_wayenabled(void)
> -{
> -	return readl(l2_base + SIFIVE_L2_WAYENABLE) & 0xFF;
> -}
> -
> -static ssize_t number_of_ways_enabled_show(struct device *dev,
> -					   struct device_attribute *attr,
> -					   char *buf)
> -{
> -	return sprintf(buf, "%u\n", l2_largest_wayenabled());
> -}
> -
> -static DEVICE_ATTR_RO(number_of_ways_enabled);
> -
> -static struct attribute *priv_attrs[] = {
> -	&dev_attr_number_of_ways_enabled.attr,
> -	NULL,
> -};
> -
> -static const struct attribute_group priv_attr_group = {
> -	.attrs = priv_attrs,
> -};
> -
> -static const struct attribute_group *l2_get_priv_group(struct cacheinfo *this_leaf)
> -{
> -	/* We want to use private group for L2 cache only */
> -	if (this_leaf->level == 2)
> -		return &priv_attr_group;
> -	else
> -		return NULL;
> -}
> -
> -static irqreturn_t l2_int_handler(int irq, void *device)
> -{
> -	unsigned int add_h, add_l;
> -
> -	if (irq == g_irq[DIR_CORR]) {
> -		add_h = readl(l2_base + SIFIVE_L2_DIRECCFIX_HIGH);
> -		add_l = readl(l2_base + SIFIVE_L2_DIRECCFIX_LOW);
> -		pr_err("L2CACHE: DirError @ 0x%08X.%08X\n", add_h, add_l);
> -		/* Reading this register clears the DirError interrupt sig */
> -		readl(l2_base + SIFIVE_L2_DIRECCFIX_COUNT);
> -		atomic_notifier_call_chain(&l2_err_chain, SIFIVE_L2_ERR_TYPE_CE,
> -					   "DirECCFix");
> -	}
> -	if (irq == g_irq[DIR_UNCORR]) {
> -		add_h = readl(l2_base + SIFIVE_L2_DIRECCFAIL_HIGH);
> -		add_l = readl(l2_base + SIFIVE_L2_DIRECCFAIL_LOW);
> -		/* Reading this register clears the DirFail interrupt sig */
> -		readl(l2_base + SIFIVE_L2_DIRECCFAIL_COUNT);
> -		atomic_notifier_call_chain(&l2_err_chain, SIFIVE_L2_ERR_TYPE_UE,
> -					   "DirECCFail");
> -		panic("L2CACHE: DirFail @ 0x%08X.%08X\n", add_h, add_l);
> -	}
> -	if (irq == g_irq[DATA_CORR]) {
> -		add_h = readl(l2_base + SIFIVE_L2_DATECCFIX_HIGH);
> -		add_l = readl(l2_base + SIFIVE_L2_DATECCFIX_LOW);
> -		pr_err("L2CACHE: DataError @ 0x%08X.%08X\n", add_h, add_l);
> -		/* Reading this register clears the DataError interrupt sig */
> -		readl(l2_base + SIFIVE_L2_DATECCFIX_COUNT);
> -		atomic_notifier_call_chain(&l2_err_chain, SIFIVE_L2_ERR_TYPE_CE,
> -					   "DatECCFix");
> -	}
> -	if (irq == g_irq[DATA_UNCORR]) {
> -		add_h = readl(l2_base + SIFIVE_L2_DATECCFAIL_HIGH);
> -		add_l = readl(l2_base + SIFIVE_L2_DATECCFAIL_LOW);
> -		pr_err("L2CACHE: DataFail @ 0x%08X.%08X\n", add_h, add_l);
> -		/* Reading this register clears the DataFail interrupt sig */
> -		readl(l2_base + SIFIVE_L2_DATECCFAIL_COUNT);
> -		atomic_notifier_call_chain(&l2_err_chain, SIFIVE_L2_ERR_TYPE_UE,
> -					   "DatECCFail");
> -	}
> -
> -	return IRQ_HANDLED;
> -}
> -
> -static int __init sifive_l2_init(void)
> -{
> -	struct device_node *np;
> -	struct resource res;
> -	int i, rc, intr_num;
> -
> -	np = of_find_matching_node(NULL, sifive_l2_ids);
> -	if (!np)
> -		return -ENODEV;
> -
> -	if (of_address_to_resource(np, 0, &res))
> -		return -ENODEV;
> -
> -	l2_base = ioremap(res.start, resource_size(&res));
> -	if (!l2_base)
> -		return -ENOMEM;
> -
> -	intr_num = of_property_count_u32_elems(np, "interrupts");
> -	if (!intr_num) {
> -		pr_err("L2CACHE: no interrupts property\n");
> -		return -ENODEV;
> -	}
> -
> -	for (i = 0; i < intr_num; i++) {
> -		g_irq[i] = irq_of_parse_and_map(np, i);
> -		rc = request_irq(g_irq[i], l2_int_handler, 0, "l2_ecc", NULL);
> -		if (rc) {
> -			pr_err("L2CACHE: Could not request IRQ %d\n", g_irq[i]);
> -			return rc;
> -		}
> -	}
> -
> -	l2_config_read();
> -
> -	l2_cache_ops.get_priv_group = l2_get_priv_group;
> -	riscv_set_cacheinfo_ops(&l2_cache_ops);
> -
> -#ifdef CONFIG_DEBUG_FS
> -	setup_sifive_debug();
> -#endif
> -	return 0;
> -}
> -device_initcall(sifive_l2_init);
> diff --git a/include/soc/sifive/sifive_ccache.h b/include/soc/sifive/sifive_ccache.h
> new file mode 100644
> index 000000000000..16576d678ea8
> --- /dev/null
> +++ b/include/soc/sifive/sifive_ccache.h
> @@ -0,0 +1,16 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * SiFive composable Cache Controller header file
> + *
> + */
> +
> +#ifndef __SOC_SIFIVE_CCACHE_H
> +#define __SOC_SIFIVE_CCACHE_H
> +
> +extern int register_sifive_ccache_error_notifier(struct notifier_block *nb);
> +extern int unregister_sifive_ccache_error_notifier(struct notifier_block *nb);
> +
> +#define SIFIVE_CCACHE_ERR_TYPE_CE 0
> +#define SIFIVE_CCACHE_ERR_TYPE_UE 1
> +
> +#endif /* __SOC_SIFIVE_CCACHE_H */
> diff --git a/include/soc/sifive/sifive_l2_cache.h b/include/soc/sifive/sifive_l2_cache.h
> deleted file mode 100644
> index 92ade10ed67e..000000000000
> --- a/include/soc/sifive/sifive_l2_cache.h
> +++ /dev/null
> @@ -1,16 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0 */
> -/*
> - * SiFive L2 Cache Controller header file
> - *
> - */
> -
> -#ifndef __SOC_SIFIVE_L2_CACHE_H
> -#define __SOC_SIFIVE_L2_CACHE_H
> -
> -extern int register_sifive_l2_error_notifier(struct notifier_block *nb);
> -extern int unregister_sifive_l2_error_notifier(struct notifier_block *nb);
> -
> -#define SIFIVE_L2_ERR_TYPE_CE 0
> -#define SIFIVE_L2_ERR_TYPE_UE 1
> -
> -#endif /* __SOC_SIFIVE_L2_CACHE_H */

-- 
Ben Dooks				http://www.codethink.co.uk/
Senior Engineer				Codethink - Providing Genius

https://www.codethink.co.uk/privacy.html

[PATCH] soc: sifive: ccache: reduce printing on init

[Ben Dooks]

The driver prints out 6 lines on startup, which can easily be redcued
to two lines without losing any information.

Note, to make the types work better, uint64_t has been replaced with
ULL to make the unsigned long long match the format in the print
statement.

Signed-off-by: Ben Dooks <ben.dooks@sifive.com>
---
 drivers/soc/sifive/sifive_ccache.c | 25 +++++++++++--------------
 1 file changed, 11 insertions(+), 14 deletions(-)

diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c
index 46ce33db7d30..65a10a6ee211 100644
--- a/drivers/soc/sifive/sifive_ccache.c
+++ b/drivers/soc/sifive/sifive_ccache.c
@@ -76,20 +76,17 @@ static void setup_sifive_debug(void)
 
 static void ccache_config_read(void)
 {
-	u32 regval, val;
-
-	regval = readl(ccache_base + SIFIVE_CCACHE_CONFIG);
-	val = regval & 0xFF;
-	pr_info("CCACHE: No. of Banks in the cache: %d\n", val);
-	val = (regval & 0xFF00) >> 8;
-	pr_info("CCACHE: No. of ways per bank: %d\n", val);
-	val = (regval & 0xFF0000) >> 16;
-	pr_info("CCACHE: Sets per bank: %llu\n", (uint64_t)1 << val);
-	val = (regval & 0xFF000000) >> 24;
-	pr_info("CCACHE: Bytes per cache block: %llu\n", (uint64_t)1 << val);
-
-	regval = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE);
-	pr_info("CCACHE: Index of the largest way enabled: %d\n", regval);
+	u32 cfg;
+
+	cfg = readl(ccache_base + SIFIVE_CCACHE_CONFIG);
+
+	pr_info("CCACHE: %u banks, %u ways, sets/bank=%llu, bytes/block=%llu\n",
+		(cfg & 0xff), (cfg >> 8) & 0xff,
+		1ULL << ((cfg >> 16) & 0xff),
+		1ULL << ((cfg >> 24) & 0xff));
+
+	cfg = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE);
+	pr_info("CCACHE: Index of the largest way enabled: %d\n", cfg);
 }
 
 static const struct of_device_id sifive_ccache_ids[] = {
-- 
2.35.1

[PATCH] dt-bindings: sifive-ccache: fix cache level for l3 cache

[Ben Dooks]

With newer cores such as the p550, the SiFive composable cache can be
a level 3 cache. Update the cache level to be one of 2 or 3.

Signed-off-by: Ben Dooks <ben.dooks@sifive.com>
---
 Documentation/devicetree/bindings/riscv/sifive-ccache.yaml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml b/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml
index 1a64a5384e36..6190deb65455 100644
--- a/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml
+++ b/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml
@@ -45,7 +45,7 @@ properties:
     const: 64
 
   cache-level:
-    const: 2
+    enum: [2, 3]
 
   cache-sets:
     enum: [1024, 2048]
-- 
2.35.1

Re: [PATCH 2/3] soc: sifive: l2 cache: Rename SiFive L2 cache to composible cache.

[Conor.Dooley]

On 29/08/2022 09:40, Zong Li wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> On Mon, Aug 29, 2022 at 3:05 PM <Conor.Dooley@microchip.com> wrote:
>>
>> Hey Zong,
>>
>> On 29/08/2022 07:22, Zong Li wrote:
>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>
>>> From: Greentime Hu <greentime.hu@sifive.com>
>>>
>>> Since composible cache may be L3 cache if pL2 cache exists, we should use
>>> its original name composible cache to prevent confusion.
>>>
>>> Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
>>> Signed-off-by: Zong Li <zong.li@sifive.com>

>>>
>>> diff --git a/drivers/soc/sifive/Kconfig b/drivers/soc/sifive/Kconfig
>>> index 58cf8c40d08d..3d65d2771f9a 100644
>>> --- a/drivers/soc/sifive/Kconfig
>>> +++ b/drivers/soc/sifive/Kconfig
>>> @@ -2,9 +2,10 @@
>>>
>>>    if SOC_SIFIVE
>>>
>>> -config SIFIVE_L2
>>> -       bool "Sifive L2 Cache controller"
>>> +config SIFIVE_CCACHE
>>> +       bool "Sifive composable Cache controller"
>>> +       default y
>>
>> Changing this to default on is not a rename of the file..
>> This should be in a different patch.
> 
> Okay, let me separate it to another patch, but I guess we could remove
> it, and enable it by user. What is your perspective on it?

Personally I would like to leave the default y out & leave it up
to the user - the driver is more informational than anything else
so I don't think making it default to on makes sense.



>>> +
>>> +#define SIFIVE_CCACHE_DIRECCFIX_LOW 0x100
>>> +#define SIFIVE_CCACHE_DIRECCFIX_HIGH 0x104
>>> +#define SIFIVE_CCACHE_DIRECCFIX_COUNT 0x108
>>> +
>>> +#define SIFIVE_CCACHE_DATECCFIX_LOW 0x140
>>> +#define SIFIVE_CCACHE_DATECCFIX_HIGH 0x144
>>> +#define SIFIVE_CCACHE_DATECCFIX_COUNT 0x148
>>> +
>>> +#define SIFIVE_CCACHE_DATECCFAIL_LOW 0x160
>>> +#define SIFIVE_CCACHE_DATECCFAIL_HIGH 0x164
>>> +#define SIFIVE_CCACHE_DATECCFAIL_COUNT 0x168
>>> +
>>> +#define SIFIVE_CCACHE_CONFIG 0x00
>>> +#define SIFIVE_CCACHE_WAYENABLE 0x08
>>> +#define SIFIVE_CCACHE_ECCINJECTERR 0x40
>>
>>   From what I can see, you've also changed these around too?
>> Please generate the patch's diff so that the rename is detected & the
>> diff shows only what changed in the file. The -M option is what you
>> are looking for.
>>
>> I have a couple other comments to make about what's changed here other,
>> thatn the rename but I will do so against a v2 where the diff is usable.
>>
> 
> Let me sent the v2 patch, and separate the rename and diff part

Great, thanks. I'll take another look at it then.

Conor.

Re: [PATCH] dt-bindings: sifive-ccache: fix cache level for l3 cache

[Rob Herring]

On Tue, Aug 30, 2022 at 3:36 AM Ben Dooks <ben.dooks@sifive.com> wrote:
>
> With newer cores such as the p550, the SiFive composable cache can be
> a level 3 cache. Update the cache level to be one of 2 or 3.
>
> Signed-off-by: Ben Dooks <ben.dooks@sifive.com>
> ---
>  Documentation/devicetree/bindings/riscv/sifive-ccache.yaml | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

Please send DT patches to the DT list. Resend so checks run.

Rob

[RESEND PATCH] dt-bindings: sifive-ccache: fix cache level for l3 cache

[Ben Dooks]

With newer cores such as the p550, the SiFive composable cache can be
a level 3 cache. Update the cache level to be one of 2 or 3.

Signed-off-by: Ben Dooks <ben.dooks@sifive.com>
---
 Documentation/devicetree/bindings/riscv/sifive-ccache.yaml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml b/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml
index 1a64a5384e36..6190deb65455 100644
--- a/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml
+++ b/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml
@@ -45,7 +45,7 @@ properties:
     const: 64
 
   cache-level:
-    const: 2
+    enum: [2, 3]
 
   cache-sets:
     enum: [1024, 2048]
-- 
2.35.1

Re: [RESEND PATCH] dt-bindings: sifive-ccache: fix cache level for l3 cache

[Conor.Dooley]

On 30/08/2022 13:51, Ben Dooks wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> With newer cores such as the p550, the SiFive composable cache can be
> a level 3 cache. Update the cache level to be one of 2 or 3.
> 
> Signed-off-by: Ben Dooks <ben.dooks@sifive.com>
> ---
>   Documentation/devicetree/bindings/riscv/sifive-ccache.yaml | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml b/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml
> index 1a64a5384e36..6190deb65455 100644
> --- a/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml
> +++ b/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml
> @@ -45,7 +45,7 @@ properties:
>       const: 64
> 
>     cache-level:
> -    const: 2
> +    enum: [2, 3]

Do we want to enforce the cache level like we currently do for
interrupts and cache-sets?

Re: [RESEND PATCH] dt-bindings: sifive-ccache: fix cache level for l3 cache

[Ben Dooks]

On 30/08/2022 13:56, Conor.Dooley@microchip.com wrote:
> On 30/08/2022 13:51, Ben Dooks wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>
>> With newer cores such as the p550, the SiFive composable cache can be
>> a level 3 cache. Update the cache level to be one of 2 or 3.
>>
>> Signed-off-by: Ben Dooks <ben.dooks@sifive.com>
>> ---
>>    Documentation/devicetree/bindings/riscv/sifive-ccache.yaml | 2 +-
>>    1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml b/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml
>> index 1a64a5384e36..6190deb65455 100644
>> --- a/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml
>> +++ b/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml
>> @@ -45,7 +45,7 @@ properties:
>>        const: 64
>>
>>      cache-level:
>> -    const: 2
>> +    enum: [2, 3]
> 
> Do we want to enforce the cache level like we currently do for
> interrupts and cache-sets?

Not sure on that, for the P550 cores the ccache is going to be level3
and my colleague has said it does confuse some tooling if the level is
not set correctly.

-- 
Ben

Re: [RESEND PATCH] dt-bindings: sifive-ccache: fix cache level for l3 cache

[Conor.Dooley]

On 30/08/2022 13:58, Ben Dooks wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> On 30/08/2022 13:56, Conor.Dooley@microchip.com wrote:
>> On 30/08/2022 13:51, Ben Dooks wrote:
>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>
>>> With newer cores such as the p550, the SiFive composable cache can be
>>> a level 3 cache. Update the cache level to be one of 2 or 3.
>>>
>>> Signed-off-by: Ben Dooks <ben.dooks@sifive.com>
>>> ---
>>>    Documentation/devicetree/bindings/riscv/sifive-ccache.yaml | 2 +-
>>>    1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml b/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml
>>> index 1a64a5384e36..6190deb65455 100644
>>> --- a/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml
>>> +++ b/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml
>>> @@ -45,7 +45,7 @@ properties:
>>>        const: 64
>>>
>>>      cache-level:
>>> -    const: 2
>>> +    enum: [2, 3]
>>
>> Do we want to enforce the cache level like we currently do for
>> interrupts and cache-sets?
> 
> Not sure on that, for the P550 cores the ccache is going to be level3
> and my colleague has said it does confuse some tooling if the level is
> not set correctly.

What I meant was:
Currently we enforce the correct cache-sets & interrupts based on the
compatible string. Adding enum: [2, 3] relaxes the enforcement of the
cache-level for existing compatibles and does not prevent someone from
setting an incorrect cache level for p550 cores.

I think that on top of adding the enum, we should add some enforcement
so that the cache is not incorrectly configured for both existing l2
caches and for the new l3 versions.

@Zong, could you please incorporate Ben's patches into your V2? it
would make it a lot easier to review what's going on here. It may
also make sense to add the compatible for the p550 cache while we are
at it...

FYI, there is also this patch here outstanding against the l2:
https://lore.kernel.org/linux-riscv/20220825180417.1259360-2-mail@conchuod.ie/

I intend taking this into 6.0-rc5 or so as a fix, so if you could
rebase the series on that so it is not lost in the dt-binding rename
that would be great.

Thanks,
Conor.

Re: [PATCH] soc: sifive: ccache: reduce printing on init

[Conor.Dooley]

On 30/08/2022 09:26, Ben Dooks wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> The driver prints out 6 lines on startup, which can easily be redcued
> to two lines without losing any information.
> 
> Note, to make the types work better, uint64_t has been replaced with
> ULL to make the unsigned long long match the format in the print
> statement.
> 
> Signed-off-by: Ben Dooks <ben.dooks@sifive.com>
> ---
>  drivers/soc/sifive/sifive_ccache.c | 25 +++++++++++--------------
>  1 file changed, 11 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c
> index 46ce33db7d30..65a10a6ee211 100644
> --- a/drivers/soc/sifive/sifive_ccache.c
> +++ b/drivers/soc/sifive/sifive_ccache.c
> @@ -76,20 +76,17 @@ static void setup_sifive_debug(void)
> 
>  static void ccache_config_read(void)
>  {
> -       u32 regval, val;
> -
> -       regval = readl(ccache_base + SIFIVE_CCACHE_CONFIG);
> -       val = regval & 0xFF;
> -       pr_info("CCACHE: No. of Banks in the cache: %d\n", val);
> -       val = (regval & 0xFF00) >> 8;
> -       pr_info("CCACHE: No. of ways per bank: %d\n", val);
> -       val = (regval & 0xFF0000) >> 16;
> -       pr_info("CCACHE: Sets per bank: %llu\n", (uint64_t)1 << val);
> -       val = (regval & 0xFF000000) >> 24;
> -       pr_info("CCACHE: Bytes per cache block: %llu\n", (uint64_t)1 << val);
> -
> -       regval = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE);
> -       pr_info("CCACHE: Index of the largest way enabled: %d\n", regval);
> +       u32 cfg;
> +
> +       cfg = readl(ccache_base + SIFIVE_CCACHE_CONFIG);
> +
> +       pr_info("CCACHE: %u banks, %u ways, sets/bank=%llu, bytes/block=%llu\n",
> +               (cfg & 0xff), (cfg >> 8) & 0xff,
> +               1ULL << ((cfg >> 16) & 0xff),

This is just BIT_ULL((cfg >> 16) & 0xff), no?
Would be nice too if these were defined, so you'd have something
like BIT_ULL((cfg >> SETS_PER_BANK_SHIFT) & 0xff)

I do like the cleanup of the uint64_t & cutting down on the prints
though :) Again, it'd be nice if you and Zong could collaborate on
a combined v2.

Thanks,
Conor.

> +               1ULL << ((cfg >> 24) & 0xff));
> +
> +       cfg = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE);
> +       pr_info("CCACHE: Index of the largest way enabled: %d\n", cfg);
>  }
> 
>  static const struct of_device_id sifive_ccache_ids[] = {
> --
> 2.35.1
> 

Re: [RESEND PATCH] dt-bindings: sifive-ccache: fix cache level for l3 cache

[Ben Dooks]

On 30/08/2022 14:49, Conor.Dooley@microchip.com wrote:
> On 30/08/2022 13:58, Ben Dooks wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>
>> On 30/08/2022 13:56, Conor.Dooley@microchip.com wrote:
>>> On 30/08/2022 13:51, Ben Dooks wrote:
>>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>>
>>>> With newer cores such as the p550, the SiFive composable cache can be
>>>> a level 3 cache. Update the cache level to be one of 2 or 3.
>>>>
>>>> Signed-off-by: Ben Dooks <ben.dooks@sifive.com>
>>>> ---
>>>>     Documentation/devicetree/bindings/riscv/sifive-ccache.yaml | 2 +-
>>>>     1 file changed, 1 insertion(+), 1 deletion(-)
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml b/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml
>>>> index 1a64a5384e36..6190deb65455 100644
>>>> --- a/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml
>>>> +++ b/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml
>>>> @@ -45,7 +45,7 @@ properties:
>>>>         const: 64
>>>>
>>>>       cache-level:
>>>> -    const: 2
>>>> +    enum: [2, 3]
>>>
>>> Do we want to enforce the cache level like we currently do for
>>> interrupts and cache-sets?
>>
>> Not sure on that, for the P550 cores the ccache is going to be level3
>> and my colleague has said it does confuse some tooling if the level is
>> not set correctly.
> 
> What I meant was:
> Currently we enforce the correct cache-sets & interrupts based on the
> compatible string. Adding enum: [2, 3] relaxes the enforcement of the
> cache-level for existing compatibles and does not prevent someone from
> setting an incorrect cache level for p550 cores.
> 
> I think that on top of adding the enum, we should add some enforcement
> so that the cache is not incorrectly configured for both existing l2
> caches and for the new l3 versions.

Ok, we can add some enforcement once we add the new bindings, but I'm
not ready for that today and I'd rather get the current queue sorted
out first before we come in with newer silicon which hasn't hit the
market uet.

> @Zong, could you please incorporate Ben's patches into your V2? it
> would make it a lot easier to review what's going on here. It may
> also make sense to add the compatible for the p550 cache while we are
> at it...
> 
> FYI, there is also this patch here outstanding against the l2:
> https://lore.kernel.org/linux-riscv/20220825180417.1259360-2-mail@conchuod.ie/
> 
> I intend taking this into 6.0-rc5 or so as a fix, so if you could
> rebase the series on that so it is not lost in the dt-binding rename
> that would be great.

Do we need someone to take charge of this series?

-- 
Ben Dooks				http://www.codethink.co.uk/
Senior Engineer				Codethink - Providing Genius

https://www.codethink.co.uk/privacy.html

Re: [PATCH] soc: sifive: ccache: reduce printing on init

[Ben Dooks]

On 30/08/2022 17:30, Conor.Dooley@microchip.com wrote:
> On 30/08/2022 09:26, Ben Dooks wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>
>> The driver prints out 6 lines on startup, which can easily be redcued
>> to two lines without losing any information.
>>
>> Note, to make the types work better, uint64_t has been replaced with
>> ULL to make the unsigned long long match the format in the print
>> statement.
>>
>> Signed-off-by: Ben Dooks <ben.dooks@sifive.com>
>> ---
>>   drivers/soc/sifive/sifive_ccache.c | 25 +++++++++++--------------
>>   1 file changed, 11 insertions(+), 14 deletions(-)
>>
>> diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c
>> index 46ce33db7d30..65a10a6ee211 100644
>> --- a/drivers/soc/sifive/sifive_ccache.c
>> +++ b/drivers/soc/sifive/sifive_ccache.c
>> @@ -76,20 +76,17 @@ static void setup_sifive_debug(void)
>>
>>   static void ccache_config_read(void)
>>   {
>> -       u32 regval, val;
>> -
>> -       regval = readl(ccache_base + SIFIVE_CCACHE_CONFIG);
>> -       val = regval & 0xFF;
>> -       pr_info("CCACHE: No. of Banks in the cache: %d\n", val);
>> -       val = (regval & 0xFF00) >> 8;
>> -       pr_info("CCACHE: No. of ways per bank: %d\n", val);
>> -       val = (regval & 0xFF0000) >> 16;
>> -       pr_info("CCACHE: Sets per bank: %llu\n", (uint64_t)1 << val);
>> -       val = (regval & 0xFF000000) >> 24;
>> -       pr_info("CCACHE: Bytes per cache block: %llu\n", (uint64_t)1 << val);
>> -
>> -       regval = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE);
>> -       pr_info("CCACHE: Index of the largest way enabled: %d\n", regval);
>> +       u32 cfg;
>> +
>> +       cfg = readl(ccache_base + SIFIVE_CCACHE_CONFIG);
>> +
>> +       pr_info("CCACHE: %u banks, %u ways, sets/bank=%llu, bytes/block=%llu\n",
>> +               (cfg & 0xff), (cfg >> 8) & 0xff,
>> +               1ULL << ((cfg >> 16) & 0xff),
> 
> This is just BIT_ULL((cfg >> 16) & 0xff), no?
> Would be nice too if these were defined, so you'd have something
> like BIT_ULL((cfg >> SETS_PER_BANK_SHIFT) & 0xff)
> 
> I do like the cleanup of the uint64_t & cutting down on the prints
> though :) Again, it'd be nice if you and Zong could collaborate on
> a combined v2.

I think even BIT_UL() would do here, if someone is going to make a
cache bigger than 2GiB we'll probably be quite old by then, so v2
might have the last two values down as %lu.

> Thanks,
> Conor.
> 
>> +               1ULL << ((cfg >> 24) & 0xff));
>> +
>> +       cfg = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE);
>> +       pr_info("CCACHE: Index of the largest way enabled: %d\n", cfg);
>>   }
>>
>>   static const struct of_device_id sifive_ccache_ids[] = {
>> --
>> 2.35.1
>>
> 
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
> 

-- 
Ben Dooks				http://www.codethink.co.uk/
Senior Engineer				Codethink - Providing Genius

https://www.codethink.co.uk/privacy.html

Re: [RESEND PATCH] dt-bindings: sifive-ccache: fix cache level for l3 cache

[Conor.Dooley]

On 30/08/2022 17:49, Ben Dooks wrote:
> On 30/08/2022 14:49, Conor.Dooley@microchip.com wrote:
>> On 30/08/2022 13:58, Ben Dooks wrote:
>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>
>>> On 30/08/2022 13:56, Conor.Dooley@microchip.com wrote:
>>>> On 30/08/2022 13:51, Ben Dooks wrote:
>>>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>>>
>>>>> With newer cores such as the p550, the SiFive composable cache can be
>>>>> a level 3 cache. Update the cache level to be one of 2 or 3.
>>>>>
>>>>> Signed-off-by: Ben Dooks <ben.dooks@sifive.com>
>>>>> ---
>>>>>     Documentation/devicetree/bindings/riscv/sifive-ccache.yaml | 2 +-
>>>>>     1 file changed, 1 insertion(+), 1 deletion(-)
>>>>>
>>>>> diff --git a/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml b/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml
>>>>> index 1a64a5384e36..6190deb65455 100644
>>>>> --- a/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml
>>>>> +++ b/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml
>>>>> @@ -45,7 +45,7 @@ properties:
>>>>>         const: 64
>>>>>
>>>>>       cache-level:
>>>>> -    const: 2
>>>>> +    enum: [2, 3]
>>>>
>>>> Do we want to enforce the cache level like we currently do for
>>>> interrupts and cache-sets?
>>>
>>> Not sure on that, for the P550 cores the ccache is going to be level3
>>> and my colleague has said it does confuse some tooling if the level is
>>> not set correctly.
>>
>> What I meant was:
>> Currently we enforce the correct cache-sets & interrupts based on the
>> compatible string. Adding enum: [2, 3] relaxes the enforcement of the
>> cache-level for existing compatibles and does not prevent someone from
>> setting an incorrect cache level for p550 cores.
>>
>> I think that on top of adding the enum, we should add some enforcement
>> so that the cache is not incorrectly configured for both existing l2
>> caches and for the new l3 versions.
> 
> Ok, we can add some enforcement once we add the new bindings, but I'm
> not ready for that today and I'd rather get the current queue sorted
> out first before we come in with newer silicon which hasn't hit the
> market uet.

SGTM. Maybe this particular patch could come at the start of the
series. And then we could add something so that the end result looks
like the following (white space damaged) diff:

diff --git a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
index ca3b9be58058..994e4b143485 100644
--- a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
+++ b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
@@ -33,6 +33,7 @@ properties:
     oneOf:
       - items:
           - enum:
+              - sifive,ccache0
               - sifive,fu540-c000-ccache
               - sifive,fu740-c000-ccache
           - const: cache
@@ -45,7 +46,7 @@ properties:
     const: 64
 
   cache-level:
-    const: 2
+    enum: [2, 3]
 
   cache-sets:
     enum: [1024, 2048]
@@ -115,6 +116,23 @@ allOf:
         cache-sets:
           const: 1024
 
+  - if:
+      properties:
+        compatible:
+          contains:
+            const:
+              sifive,ccache0
+
+    then:
+      properties:
+        cache-level:
+         enum: [2, 3]
+
+    else:
+      properties:
+        cache-level:
+          const: 2
+
 additionalProperties: false
 
 required:


That would keep the enforcement for existing caches and allow you
the freedome to do w/e you want for the ccache0 compatible.

> 
>> @Zong, could you please incorporate Ben's patches into your V2? it
>> would make it a lot easier to review what's going on here. It may
>> also make sense to add the compatible for the p550 cache while we are
>> at it...
>>
>> FYI, there is also this patch here outstanding against the l2:
>> https://lore.kernel.org/linux-riscv/20220825180417.1259360-2-mail@conchuod.ie/
>>
>> I intend taking this into 6.0-rc5 or so as a fix, so if you could
>> rebase the series on that so it is not lost in the dt-binding rename
>> that would be great.
> 
> Do we need someone to take charge of this series?
> 

Can I volunteer Zong? (since all but two of the patches are theirs)

Thanks,
Conor.

Re: [RESEND PATCH] dt-bindings: sifive-ccache: fix cache level for l3 cache

[Zong Li]

<Conor.Dooley@microchip.com> 於 2022年8月31日 週三 凌晨1:09寫道：
>
> On 30/08/2022 17:49, Ben Dooks wrote:
> > On 30/08/2022 14:49, Conor.Dooley@microchip.com wrote:
> >> On 30/08/2022 13:58, Ben Dooks wrote:
> >>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >>>
> >>> On 30/08/2022 13:56, Conor.Dooley@microchip.com wrote:
> >>>> On 30/08/2022 13:51, Ben Dooks wrote:
> >>>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >>>>>
> >>>>> With newer cores such as the p550, the SiFive composable cache can be
> >>>>> a level 3 cache. Update the cache level to be one of 2 or 3.
> >>>>>
> >>>>> Signed-off-by: Ben Dooks <ben.dooks@sifive.com>
> >>>>> ---
> >>>>>     Documentation/devicetree/bindings/riscv/sifive-ccache.yaml | 2 +-
> >>>>>     1 file changed, 1 insertion(+), 1 deletion(-)
> >>>>>
> >>>>> diff --git a/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml b/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml
> >>>>> index 1a64a5384e36..6190deb65455 100644
> >>>>> --- a/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml
> >>>>> +++ b/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml
> >>>>> @@ -45,7 +45,7 @@ properties:
> >>>>>         const: 64
> >>>>>
> >>>>>       cache-level:
> >>>>> -    const: 2
> >>>>> +    enum: [2, 3]
> >>>>
> >>>> Do we want to enforce the cache level like we currently do for
> >>>> interrupts and cache-sets?
> >>>
> >>> Not sure on that, for the P550 cores the ccache is going to be level3
> >>> and my colleague has said it does confuse some tooling if the level is
> >>> not set correctly.
> >>
> >> What I meant was:
> >> Currently we enforce the correct cache-sets & interrupts based on the
> >> compatible string. Adding enum: [2, 3] relaxes the enforcement of the
> >> cache-level for existing compatibles and does not prevent someone from
> >> setting an incorrect cache level for p550 cores.
> >>
> >> I think that on top of adding the enum, we should add some enforcement
> >> so that the cache is not incorrectly configured for both existing l2
> >> caches and for the new l3 versions.
> >
> > Ok, we can add some enforcement once we add the new bindings, but I'm
> > not ready for that today and I'd rather get the current queue sorted
> > out first before we come in with newer silicon which hasn't hit the
> > market uet.
>
> SGTM. Maybe this particular patch could come at the start of the
> series. And then we could add something so that the end result looks
> like the following (white space damaged) diff:
>
> diff --git a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
> index ca3b9be58058..994e4b143485 100644
> --- a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
> +++ b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
> @@ -33,6 +33,7 @@ properties:
>      oneOf:
>        - items:
>            - enum:
> +              - sifive,ccache0
>                - sifive,fu540-c000-ccache
>                - sifive,fu740-c000-ccache
>            - const: cache
> @@ -45,7 +46,7 @@ properties:
>      const: 64
>
>    cache-level:
> -    const: 2
> +    enum: [2, 3]
>
>    cache-sets:
>      enum: [1024, 2048]
> @@ -115,6 +116,23 @@ allOf:
>          cache-sets:
>            const: 1024
>
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            const:
> +              sifive,ccache0
> +
> +    then:
> +      properties:
> +        cache-level:
> +         enum: [2, 3]
> +
> +    else:
> +      properties:
> +        cache-level:
> +          const: 2
> +
>  additionalProperties: false
>
>  required:
>
>
> That would keep the enforcement for existing caches and allow you
> the freedome to do w/e you want for the ccache0 compatible.

Thanks you all for bring me here,  we actually have some core series
with 4096 cache set in ccache, should we need to extend the cache set
as follow? or we only need to focus on the DTS which is already in
mainline.

cache-sets:
-    enum: [1024, 2048]
+   enum: [1024, 2048, 4096]

>
> >
> >> @Zong, could you please incorporate Ben's patches into your V2? it
> >> would make it a lot easier to review what's going on here. It may
> >> also make sense to add the compatible for the p550 cache while we are
> >> at it...
> >>
> >> FYI, there is also this patch here outstanding against the l2:
> >> https://lore.kernel.org/linux-riscv/20220825180417.1259360-2-mail@conchuod.ie/
> >>
> >> I intend taking this into 6.0-rc5 or so as a fix, so if you could
> >> rebase the series on that so it is not lost in the dt-binding rename
> >> that would be great.
> >
> > Do we need someone to take charge of this series?
> >
>
> Can I volunteer Zong? (since all but two of the patches are theirs)
>

It is ok to me, but I'm still refining the patchset for V2, and I'm
not sure if we will need the V3. Do you prefer to take V2 patch set
first and replace the dt-binding patch?

> Thanks,
> Conor.
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv

Re: [PATCH] soc: sifive: ccache: reduce printing on init

[Zong Li]

Ben Dooks <ben.dooks@codethink.co.uk> 於 2022年8月31日 週三 凌晨1:04寫道：
>
> On 30/08/2022 17:30, Conor.Dooley@microchip.com wrote:
> > On 30/08/2022 09:26, Ben Dooks wrote:
> >> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >>
> >> The driver prints out 6 lines on startup, which can easily be redcued
> >> to two lines without losing any information.
> >>
> >> Note, to make the types work better, uint64_t has been replaced with
> >> ULL to make the unsigned long long match the format in the print
> >> statement.
> >>
> >> Signed-off-by: Ben Dooks <ben.dooks@sifive.com>
> >> ---
> >>   drivers/soc/sifive/sifive_ccache.c | 25 +++++++++++--------------
> >>   1 file changed, 11 insertions(+), 14 deletions(-)
> >>
> >> diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c
> >> index 46ce33db7d30..65a10a6ee211 100644
> >> --- a/drivers/soc/sifive/sifive_ccache.c
> >> +++ b/drivers/soc/sifive/sifive_ccache.c
> >> @@ -76,20 +76,17 @@ static void setup_sifive_debug(void)
> >>
> >>   static void ccache_config_read(void)
> >>   {
> >> -       u32 regval, val;
> >> -
> >> -       regval = readl(ccache_base + SIFIVE_CCACHE_CONFIG);
> >> -       val = regval & 0xFF;
> >> -       pr_info("CCACHE: No. of Banks in the cache: %d\n", val);
> >> -       val = (regval & 0xFF00) >> 8;
> >> -       pr_info("CCACHE: No. of ways per bank: %d\n", val);
> >> -       val = (regval & 0xFF0000) >> 16;
> >> -       pr_info("CCACHE: Sets per bank: %llu\n", (uint64_t)1 << val);
> >> -       val = (regval & 0xFF000000) >> 24;
> >> -       pr_info("CCACHE: Bytes per cache block: %llu\n", (uint64_t)1 << val);
> >> -
> >> -       regval = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE);
> >> -       pr_info("CCACHE: Index of the largest way enabled: %d\n", regval);
> >> +       u32 cfg;
> >> +
> >> +       cfg = readl(ccache_base + SIFIVE_CCACHE_CONFIG);
> >> +
> >> +       pr_info("CCACHE: %u banks, %u ways, sets/bank=%llu, bytes/block=%llu\n",
> >> +               (cfg & 0xff), (cfg >> 8) & 0xff,
> >> +               1ULL << ((cfg >> 16) & 0xff),
> >
> > This is just BIT_ULL((cfg >> 16) & 0xff), no?
> > Would be nice too if these were defined, so you'd have something
> > like BIT_ULL((cfg >> SETS_PER_BANK_SHIFT) & 0xff)
> >
> > I do like the cleanup of the uint64_t & cutting down on the prints
> > though :) Again, it'd be nice if you and Zong could collaborate on
> > a combined v2.
>
> I think even BIT_UL() would do here, if someone is going to make a
> cache bigger than 2GiB we'll probably be quite old by then, so v2
> might have the last two values down as %lu.
>

Hi Ben,
Thanks for your suggestion, If you don't mind, I will take this into
my V2 patchset.

> > Thanks,
> > Conor.
> >
> >> +               1ULL << ((cfg >> 24) & 0xff));
> >> +
> >> +       cfg = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE);
> >> +       pr_info("CCACHE: Index of the largest way enabled: %d\n", cfg);
> >>   }
> >>
> >>   static const struct of_device_id sifive_ccache_ids[] = {
> >> --
> >> 2.35.1
> >>
> >
> > _______________________________________________
> > linux-riscv mailing list
> > linux-riscv@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-riscv
> >
>
> --
> Ben Dooks                               http://www.codethink.co.uk/
> Senior Engineer                         Codethink - Providing Genius
>
> https://www.codethink.co.uk/privacy.html
>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv

Re: [PATCH 2/3] soc: sifive: l2 cache: Rename SiFive L2 cache to composible cache.

[Zong Li]

<Conor.Dooley@microchip.com> 於 2022年8月30日 週二 下午4:42寫道：
>
> On 29/08/2022 09:40, Zong Li wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >
> > On Mon, Aug 29, 2022 at 3:05 PM <Conor.Dooley@microchip.com> wrote:
> >>
> >> Hey Zong,
> >>
> >> On 29/08/2022 07:22, Zong Li wrote:
> >>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >>>
> >>> From: Greentime Hu <greentime.hu@sifive.com>
> >>>
> >>> Since composible cache may be L3 cache if pL2 cache exists, we should use
> >>> its original name composible cache to prevent confusion.
> >>>
> >>> Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
> >>> Signed-off-by: Zong Li <zong.li@sifive.com>
>
> >>>
> >>> diff --git a/drivers/soc/sifive/Kconfig b/drivers/soc/sifive/Kconfig
> >>> index 58cf8c40d08d..3d65d2771f9a 100644
> >>> --- a/drivers/soc/sifive/Kconfig
> >>> +++ b/drivers/soc/sifive/Kconfig
> >>> @@ -2,9 +2,10 @@
> >>>
> >>>    if SOC_SIFIVE
> >>>
> >>> -config SIFIVE_L2
> >>> -       bool "Sifive L2 Cache controller"
> >>> +config SIFIVE_CCACHE
> >>> +       bool "Sifive composable Cache controller"
> >>> +       default y
> >>
> >> Changing this to default on is not a rename of the file..
> >> This should be in a different patch.
> >
> > Okay, let me separate it to another patch, but I guess we could remove
> > it, and enable it by user. What is your perspective on it?
>
> Personally I would like to leave the default y out & leave it up
> to the user - the driver is more informational than anything else
> so I don't think making it default to on makes sense.
>

Agree, let me remove it in the next version. Thanks

>
>
> >>> +
> >>> +#define SIFIVE_CCACHE_DIRECCFIX_LOW 0x100
> >>> +#define SIFIVE_CCACHE_DIRECCFIX_HIGH 0x104
> >>> +#define SIFIVE_CCACHE_DIRECCFIX_COUNT 0x108
> >>> +
> >>> +#define SIFIVE_CCACHE_DATECCFIX_LOW 0x140
> >>> +#define SIFIVE_CCACHE_DATECCFIX_HIGH 0x144
> >>> +#define SIFIVE_CCACHE_DATECCFIX_COUNT 0x148
> >>> +
> >>> +#define SIFIVE_CCACHE_DATECCFAIL_LOW 0x160
> >>> +#define SIFIVE_CCACHE_DATECCFAIL_HIGH 0x164
> >>> +#define SIFIVE_CCACHE_DATECCFAIL_COUNT 0x168
> >>> +
> >>> +#define SIFIVE_CCACHE_CONFIG 0x00
> >>> +#define SIFIVE_CCACHE_WAYENABLE 0x08
> >>> +#define SIFIVE_CCACHE_ECCINJECTERR 0x40
> >>
> >>   From what I can see, you've also changed these around too?
> >> Please generate the patch's diff so that the rename is detected & the
> >> diff shows only what changed in the file. The -M option is what you
> >> are looking for.
> >>
> >> I have a couple other comments to make about what's changed here other,
> >> thatn the rename but I will do so against a v2 where the diff is usable.
> >>
> >
> > Let me sent the v2 patch, and separate the rename and diff part
>
> Great, thanks. I'll take another look at it then.
>
> Conor.
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv

Re: [RESEND PATCH] dt-bindings: sifive-ccache: fix cache level for l3 cache

[Conor.Dooley]

On 31/08/2022 06:17, Zong Li wrote:
> [Some people who received this message don't often get email from zongbox@gmail.com. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
> 
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> <Conor.Dooley@microchip.com> 於 2022年8月31日 週三 凌晨1:09寫道：
>> That would keep the enforcement for existing caches and allow you
>> the freedome to do w/e you want for the ccache0 compatible.
> 
> Thanks you all for bring me here,  we actually have some core series
> with 4096 cache set in ccache, should we need to extend the cache set
> as follow? or we only need to focus on the DTS which is already in
> mainline.
> 
> cache-sets:
> -    enum: [1024, 2048]
> +   enum: [1024, 2048, 4096]

Until a user shows up, I think we are better off not adding 4096.

>>> Do we need someone to take charge of this series?
>>>
>>
>> Can I volunteer Zong? (since all but two of the patches are theirs)
>>
> 
> It is ok to me, but I'm still refining the patchset for V2, and I'm
> not sure if we will need the V3. Do you prefer to take V2 patch set
> first and replace the dt-binding patch?

If you could incorporate it for v2 it would make reviewing easier
I think.

Thanks,
Conor.

Re: [PATCH 0/3] Rename sifive L2 cache to sifive CCACHE

[Zong Li]

On Tue, Aug 30, 2022 at 3:59 PM Ben Dooks <ben.dooks@sifive.com> wrote:
>
> On 29/08/2022 07:21, Zong Li wrote:
> > Since composible cache may be L3 cache if private L2 cache exists, we
> > should use its original name "composible cache" to prevent confusion.
> >
> > This patchset contains the modification which is related to ccache, such
> > as DT binding and EDAC driver.
> >
> > Greentime Hu (1):
> >    soc: sifive: l2 cache: Rename SiFive L2 cache to composible cache.
> >
> > Zong Li (2):
> >    dt-bindings: sifive-ccache: rename SiFive L2 cache to composible cache
> >    EDAC/sifive: use sifive_ccache instead of sifive_l2
> >
> >   ...ifive-l2-cache.yaml => sifive-ccache.yaml} |   6 +-
> >   drivers/edac/Kconfig                          |   2 +-
> >   drivers/edac/sifive_edac.c                    |  12 +-
> >   drivers/soc/sifive/Kconfig                    |   7 +-
> >   drivers/soc/sifive/Makefile                   |   2 +-
> >   drivers/soc/sifive/sifive_ccache.c            | 221 ++++++++++++++++
> >   drivers/soc/sifive/sifive_l2_cache.c          | 237 ------------------
> >   include/soc/sifive/sifive_ccache.h            |  16 ++
> >   include/soc/sifive/sifive_l2_cache.h          |  16 --
> >   9 files changed, 253 insertions(+), 266 deletions(-)
> >   rename Documentation/devicetree/bindings/riscv/{sifive-l2-cache.yaml => sifive-ccache.yaml} (92%)
> >   create mode 100644 drivers/soc/sifive/sifive_ccache.c
> >   delete mode 100644 drivers/soc/sifive/sifive_l2_cache.c
> >   create mode 100644 include/soc/sifive/sifive_ccache.h
> >   delete mode 100644 include/soc/sifive/sifive_l2_cache.h
>
> Is this series available on a git branch anywhere, I have at least
> one other cleanup I was doing in a similar move to rename and make
> it usable as the l3 cache.
>
> I gave the series a quick review and did not find any issues so far.
>

Thanks for your review, I don't push the series to a public
repository, if you needed, I can push it to somewhere.

> --
> Ben
>
>

Re: [PATCH] soc: sifive: ccache: reduce printing on init

[Ben Dooks]

On 31/08/2022 06:22, Zong Li wrote:
> Ben Dooks <ben.dooks@codethink.co.uk> 於 2022年8月31日 週三 凌晨1:04寫道：
>>
>> On 30/08/2022 17:30, Conor.Dooley@microchip.com wrote:
>>> On 30/08/2022 09:26, Ben Dooks wrote:
>>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>>
>>>> The driver prints out 6 lines on startup, which can easily be redcued
>>>> to two lines without losing any information.
>>>>
>>>> Note, to make the types work better, uint64_t has been replaced with
>>>> ULL to make the unsigned long long match the format in the print
>>>> statement.
>>>>
>>>> Signed-off-by: Ben Dooks <ben.dooks@sifive.com>
>>>> ---
>>>>    drivers/soc/sifive/sifive_ccache.c | 25 +++++++++++--------------
>>>>    1 file changed, 11 insertions(+), 14 deletions(-)
>>>>
>>>> diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c
>>>> index 46ce33db7d30..65a10a6ee211 100644
>>>> --- a/drivers/soc/sifive/sifive_ccache.c
>>>> +++ b/drivers/soc/sifive/sifive_ccache.c
>>>> @@ -76,20 +76,17 @@ static void setup_sifive_debug(void)
>>>>
>>>>    static void ccache_config_read(void)
>>>>    {
>>>> -       u32 regval, val;
>>>> -
>>>> -       regval = readl(ccache_base + SIFIVE_CCACHE_CONFIG);
>>>> -       val = regval & 0xFF;
>>>> -       pr_info("CCACHE: No. of Banks in the cache: %d\n", val);
>>>> -       val = (regval & 0xFF00) >> 8;
>>>> -       pr_info("CCACHE: No. of ways per bank: %d\n", val);
>>>> -       val = (regval & 0xFF0000) >> 16;
>>>> -       pr_info("CCACHE: Sets per bank: %llu\n", (uint64_t)1 << val);
>>>> -       val = (regval & 0xFF000000) >> 24;
>>>> -       pr_info("CCACHE: Bytes per cache block: %llu\n", (uint64_t)1 << val);
>>>> -
>>>> -       regval = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE);
>>>> -       pr_info("CCACHE: Index of the largest way enabled: %d\n", regval);
>>>> +       u32 cfg;
>>>> +
>>>> +       cfg = readl(ccache_base + SIFIVE_CCACHE_CONFIG);
>>>> +
>>>> +       pr_info("CCACHE: %u banks, %u ways, sets/bank=%llu, bytes/block=%llu\n",
>>>> +               (cfg & 0xff), (cfg >> 8) & 0xff,
>>>> +               1ULL << ((cfg >> 16) & 0xff),
>>>
>>> This is just BIT_ULL((cfg >> 16) & 0xff), no?
>>> Would be nice too if these were defined, so you'd have something
>>> like BIT_ULL((cfg >> SETS_PER_BANK_SHIFT) & 0xff)
>>>
>>> I do like the cleanup of the uint64_t & cutting down on the prints
>>> though :) Again, it'd be nice if you and Zong could collaborate on
>>> a combined v2.
>>
>> I think even BIT_UL() would do here, if someone is going to make a
>> cache bigger than 2GiB we'll probably be quite old by then, so v2
>> might have the last two values down as %lu.
>>
> 
> Hi Ben,
> Thanks for your suggestion, If you don't mind, I will take this into
> my V2 patchset.

Thanks.

I may well post v2 of this tomorrow with the BIT_ULL() suggestions
from Conor, or even down to BIT_UL() and use %lu as noted.

> 
>>> Thanks,
>>> Conor.
>>>
>>>> +               1ULL << ((cfg >> 24) & 0xff));
>>>> +
>>>> +       cfg = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE);
>>>> +       pr_info("CCACHE: Index of the largest way enabled: %d\n", cfg);
>>>>    }
>>>>
>>>>    static const struct of_device_id sifive_ccache_ids[] = {
>>>> --
>>>> 2.35.1
>>>>
>>>
>>> _______________________________________________
>>> linux-riscv mailing list
>>> linux-riscv@lists.infradead.org
>>> http://lists.infradead.org/mailman/listinfo/linux-riscv
>>>
>>
>> --
>> Ben Dooks                               http://www.codethink.co.uk/
>> Senior Engineer                         Codethink - Providing Genius
>>
>> https://www.codethink.co.uk/privacy.html
>>
>>
>> _______________________________________________
>> linux-riscv mailing list
>> linux-riscv@lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-riscv

Re: [PATCH] soc: sifive: ccache: reduce printing on init

[Zong Li]

On Wed, Aug 31, 2022 at 11:55 PM Ben Dooks <ben.dooks@sifive.com> wrote:
>
> On 31/08/2022 06:22, Zong Li wrote:
> > Ben Dooks <ben.dooks@codethink.co.uk> 於 2022年8月31日 週三 凌晨1:04寫道：
> >>
> >> On 30/08/2022 17:30, Conor.Dooley@microchip.com wrote:
> >>> On 30/08/2022 09:26, Ben Dooks wrote:
> >>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >>>>
> >>>> The driver prints out 6 lines on startup, which can easily be redcued
> >>>> to two lines without losing any information.
> >>>>
> >>>> Note, to make the types work better, uint64_t has been replaced with
> >>>> ULL to make the unsigned long long match the format in the print
> >>>> statement.
> >>>>
> >>>> Signed-off-by: Ben Dooks <ben.dooks@sifive.com>
> >>>> ---
> >>>>    drivers/soc/sifive/sifive_ccache.c | 25 +++++++++++--------------
> >>>>    1 file changed, 11 insertions(+), 14 deletions(-)
> >>>>
> >>>> diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c
> >>>> index 46ce33db7d30..65a10a6ee211 100644
> >>>> --- a/drivers/soc/sifive/sifive_ccache.c
> >>>> +++ b/drivers/soc/sifive/sifive_ccache.c
> >>>> @@ -76,20 +76,17 @@ static void setup_sifive_debug(void)
> >>>>
> >>>>    static void ccache_config_read(void)
> >>>>    {
> >>>> -       u32 regval, val;
> >>>> -
> >>>> -       regval = readl(ccache_base + SIFIVE_CCACHE_CONFIG);
> >>>> -       val = regval & 0xFF;
> >>>> -       pr_info("CCACHE: No. of Banks in the cache: %d\n", val);
> >>>> -       val = (regval & 0xFF00) >> 8;
> >>>> -       pr_info("CCACHE: No. of ways per bank: %d\n", val);
> >>>> -       val = (regval & 0xFF0000) >> 16;
> >>>> -       pr_info("CCACHE: Sets per bank: %llu\n", (uint64_t)1 << val);
> >>>> -       val = (regval & 0xFF000000) >> 24;
> >>>> -       pr_info("CCACHE: Bytes per cache block: %llu\n", (uint64_t)1 << val);
> >>>> -
> >>>> -       regval = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE);
> >>>> -       pr_info("CCACHE: Index of the largest way enabled: %d\n", regval);
> >>>> +       u32 cfg;
> >>>> +
> >>>> +       cfg = readl(ccache_base + SIFIVE_CCACHE_CONFIG);
> >>>> +
> >>>> +       pr_info("CCACHE: %u banks, %u ways, sets/bank=%llu, bytes/block=%llu\n",
> >>>> +               (cfg & 0xff), (cfg >> 8) & 0xff,
> >>>> +               1ULL << ((cfg >> 16) & 0xff),
> >>>
> >>> This is just BIT_ULL((cfg >> 16) & 0xff), no?
> >>> Would be nice too if these were defined, so you'd have something
> >>> like BIT_ULL((cfg >> SETS_PER_BANK_SHIFT) & 0xff)
> >>>
> >>> I do like the cleanup of the uint64_t & cutting down on the prints
> >>> though :) Again, it'd be nice if you and Zong could collaborate on
> >>> a combined v2.
> >>
> >> I think even BIT_UL() would do here, if someone is going to make a
> >> cache bigger than 2GiB we'll probably be quite old by then, so v2
> >> might have the last two values down as %lu.
> >>
> >
> > Hi Ben,
> > Thanks for your suggestion, If you don't mind, I will take this into
> > my V2 patchset.
>
> Thanks.
>
> I may well post v2 of this tomorrow with the BIT_ULL() suggestions
> from Conor, or even down to BIT_UL() and use %lu as noted.
>

No problem Ben. Could you please also add me in the thread of your v2,
then I can take it and send out my v2 patchset. Thanks.

> >
> >>> Thanks,
> >>> Conor.
> >>>
> >>>> +               1ULL << ((cfg >> 24) & 0xff));
> >>>> +
> >>>> +       cfg = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE);
> >>>> +       pr_info("CCACHE: Index of the largest way enabled: %d\n", cfg);
> >>>>    }
> >>>>
> >>>>    static const struct of_device_id sifive_ccache_ids[] = {
> >>>> --
> >>>> 2.35.1
> >>>>
> >>>
> >>> _______________________________________________
> >>> linux-riscv mailing list
> >>> linux-riscv@lists.infradead.org
> >>> http://lists.infradead.org/mailman/listinfo/linux-riscv
> >>>
> >>
> >> --
> >> Ben Dooks                               http://www.codethink.co.uk/
> >> Senior Engineer                         Codethink - Providing Genius
> >>
> >> https://www.codethink.co.uk/privacy.html
> >>
> >>
> >> _______________________________________________
> >> linux-riscv mailing list
> >> linux-riscv@lists.infradead.org
> >> http://lists.infradead.org/mailman/listinfo/linux-riscv
>

Re: [RESEND PATCH] dt-bindings: sifive-ccache: fix cache level for l3 cache

[Rob Herring]

On Tue, 30 Aug 2022 13:51:33 +0100, Ben Dooks wrote:
> With newer cores such as the p550, the SiFive composable cache can be
> a level 3 cache. Update the cache level to be one of 2 or 3.
> 
> Signed-off-by: Ben Dooks <ben.dooks@sifive.com>
> ---
>  Documentation/devicetree/bindings/riscv/sifive-ccache.yaml | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 

Acked-by: Rob Herring <robh@kernel.org>

Re: [PATCH 1/3] dt-bindings: sifive-ccache: rename SiFive L2 cache to composible cache

[Palmer Dabbelt]

On Sun, 28 Aug 2022 23:22:00 PDT (-0700), zong.li@sifive.com wrote:
> Since composible cache may be L3 cache if private L2 cache exists, it
> should use its original name composible cache to prevent confusion.
>
> Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
> Signed-off-by: Zong Li <zong.li@sifive.com>
> ---
>  .../riscv/{sifive-l2-cache.yaml => sifive-ccache.yaml}      | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)
>  rename Documentation/devicetree/bindings/riscv/{sifive-l2-cache.yaml => sifive-ccache.yaml} (92%)
>
> diff --git a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml b/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml
> similarity index 92%
> rename from Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
> rename to Documentation/devicetree/bindings/riscv/sifive-ccache.yaml
> index 69cdab18d629..1a64a5384e36 100644
> --- a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
> +++ b/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml
> @@ -12,8 +12,8 @@ maintainers:
>    - Paul Walmsley  <paul.walmsley@sifive.com>
>
>  description:
> -  The SiFive Level 2 Cache Controller is used to provide access to fast copies
> -  of memory for masters in a Core Complex. The Level 2 Cache Controller also
> +  The SiFive Composable Cache Controller is used to provide access to fast copies
> +  of memory for masters in a Core Complex. The Composable Cache Controller also
>    acts as directory-based coherency manager.
>    All the properties in ePAPR/DeviceTree specification applies for this platform.
>
> @@ -27,6 +27,7 @@ select:
>          enum:
>            - sifive,fu540-c000-ccache
>            - sifive,fu740-c000-ccache
> +          - sifive,ccache0

Looks like Rob's bot had comments and I don't see a v2.  Sorry if I'm 
missing something.

Also: I'd guess that we only had the SOC-specific mappings on purpose.  
It's kind of a grey area and I'm OK either way, but I'd definately 
prefer the DT folks to get a chance to review these.  My guess is that 
they're not looking due to the bot comments, but sorry again if I've 
missed it.

>    required:
>      - compatible
> @@ -37,6 +38,7 @@ properties:
>        - enum:
>            - sifive,fu540-c000-ccache
>            - sifive,fu740-c000-ccache
> +          - sifive,ccache0
>        - const: cache
>
>    cache-block-size:

Re: [PATCH 3/3] EDAC/sifive: use sifive_ccache instead of sifive_l2

[Palmer Dabbelt]

On Sun, 28 Aug 2022 23:22:02 PDT (-0700), zong.li@sifive.com wrote:
> The sifive L2 has been renamed to sifive CCACHE, EDAC driver needs to
> apply the change as well

That means the build would be broken before this patch, which we 
generally try to avoid as it breaks things like bisecting.

>
> Signed-off-by: Zong Li <zong.li@sifive.com>
> ---
>  drivers/edac/Kconfig       |  2 +-
>  drivers/edac/sifive_edac.c | 12 ++++++------
>  2 files changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
> index 17562cf1fe97..456602d373b7 100644
> --- a/drivers/edac/Kconfig
> +++ b/drivers/edac/Kconfig
> @@ -473,7 +473,7 @@ config EDAC_ALTERA_SDMMC
>
>  config EDAC_SIFIVE
>  	bool "Sifive platform EDAC driver"
> -	depends on EDAC=y && SIFIVE_L2
> +	depends on EDAC=y && SIFIVE_CCACHE
>  	help
>  	  Support for error detection and correction on the SiFive SoCs.
>
> diff --git a/drivers/edac/sifive_edac.c b/drivers/edac/sifive_edac.c
> index ee800aec7d47..b844e2626fd5 100644
> --- a/drivers/edac/sifive_edac.c
> +++ b/drivers/edac/sifive_edac.c
> @@ -2,7 +2,7 @@
>  /*
>   * SiFive Platform EDAC Driver
>   *
> - * Copyright (C) 2018-2019 SiFive, Inc.
> + * Copyright (C) 2018-2022 SiFive, Inc.
>   *
>   * This driver is partially based on octeon_edac-pc.c
>   *
> @@ -10,7 +10,7 @@
>  #include <linux/edac.h>
>  #include <linux/platform_device.h>
>  #include "edac_module.h"
> -#include <soc/sifive/sifive_l2_cache.h>
> +#include <soc/sifive/sifive_ccache.h>
>
>  #define DRVNAME "sifive_edac"
>
> @@ -32,9 +32,9 @@ int ecc_err_event(struct notifier_block *this, unsigned long event, void *ptr)
>
>  	p = container_of(this, struct sifive_edac_priv, notifier);
>
> -	if (event == SIFIVE_L2_ERR_TYPE_UE)
> +	if (event == SIFIVE_CCACHE_ERR_TYPE_UE)
>  		edac_device_handle_ue(p->dci, 0, 0, msg);
> -	else if (event == SIFIVE_L2_ERR_TYPE_CE)
> +	else if (event == SIFIVE_CCACHE_ERR_TYPE_CE)
>  		edac_device_handle_ce(p->dci, 0, 0, msg);
>
>  	return NOTIFY_OK;
> @@ -67,7 +67,7 @@ static int ecc_register(struct platform_device *pdev)
>  		goto err;
>  	}
>
> -	register_sifive_l2_error_notifier(&p->notifier);
> +	register_sifive_ccache_error_notifier(&p->notifier);
>
>  	return 0;
>
> @@ -81,7 +81,7 @@ static int ecc_unregister(struct platform_device *pdev)
>  {
>  	struct sifive_edac_priv *p = platform_get_drvdata(pdev);
>
> -	unregister_sifive_l2_error_notifier(&p->notifier);
> +	unregister_sifive_ccache_error_notifier(&p->notifier);
>  	edac_device_del_device(&pdev->dev);
>  	edac_device_free_ctl_info(p->dci);

Re: [PATCH 1/3] dt-bindings: sifive-ccache: rename SiFive L2 cache to composible cache

[Zong Li]

On Fri, Oct 7, 2022 at 10:58 AM Palmer Dabbelt <palmer@dabbelt.com> wrote:
>
> On Sun, 28 Aug 2022 23:22:00 PDT (-0700), zong.li@sifive.com wrote:
> > Since composible cache may be L3 cache if private L2 cache exists, it
> > should use its original name composible cache to prevent confusion.
> >
> > Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
> > Signed-off-by: Zong Li <zong.li@sifive.com>
> > ---
> >  .../riscv/{sifive-l2-cache.yaml => sifive-ccache.yaml}      | 6 ++++--
> >  1 file changed, 4 insertions(+), 2 deletions(-)
> >  rename Documentation/devicetree/bindings/riscv/{sifive-l2-cache.yaml => sifive-ccache.yaml} (92%)
> >
> > diff --git a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml b/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml
> > similarity index 92%
> > rename from Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
> > rename to Documentation/devicetree/bindings/riscv/sifive-ccache.yaml
> > index 69cdab18d629..1a64a5384e36 100644
> > --- a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
> > +++ b/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml
> > @@ -12,8 +12,8 @@ maintainers:
> >    - Paul Walmsley  <paul.walmsley@sifive.com>
> >
> >  description:
> > -  The SiFive Level 2 Cache Controller is used to provide access to fast copies
> > -  of memory for masters in a Core Complex. The Level 2 Cache Controller also
> > +  The SiFive Composable Cache Controller is used to provide access to fast copies
> > +  of memory for masters in a Core Complex. The Composable Cache Controller also
> >    acts as directory-based coherency manager.
> >    All the properties in ePAPR/DeviceTree specification applies for this platform.
> >
> > @@ -27,6 +27,7 @@ select:
> >          enum:
> >            - sifive,fu540-c000-ccache
> >            - sifive,fu740-c000-ccache
> > +          - sifive,ccache0
>
> Looks like Rob's bot had comments and I don't see a v2.  Sorry if I'm
> missing something.

Hi Palmer,
We moved this series to the following patch set:
http://lists.infradead.org/pipermail/linux-riscv/2022-October/020196.html

Sorry for the confusion. Many thanks for considering this series.

>
> Also: I'd guess that we only had the SOC-specific mappings on purpose.
> It's kind of a grey area and I'm OK either way, but I'd definately
> prefer the DT folks to get a chance to review these.  My guess is that
> they're not looking due to the bot comments, but sorry again if I've
> missed it.
>
> >    required:
> >      - compatible
> > @@ -37,6 +38,7 @@ properties:
> >        - enum:
> >            - sifive,fu540-c000-ccache
> >            - sifive,fu740-c000-ccache
> > +          - sifive,ccache0
> >        - const: cache
> >
> >    cache-block-size: