From: Alan Tull <atull@kernel.org>
To: Wu Hao <hao.wu@intel.com>
Cc: Moritz Fischer <mdf@kernel.org>,
linux-fpga@vger.kernel.org,
linux-kernel <linux-kernel@vger.kernel.org>,
linux-api@vger.kernel.org, Luwei Kang <luwei.kang@intel.com>,
Xu Yilun <yilun.xu@intel.com>
Subject: Re: [PATCH 13/17] fpga: dfl: fme: add capability sysfs interfaces
Date: Tue, 9 Apr 2019 16:05:09 -0500 [thread overview]
Message-ID: <CANk1AXQvsUYHmyZ7XF2LD+eNQ2FV33HageL0Mgbt7-9YVaagdw@mail.gmail.com> (raw)
In-Reply-To: <1553483264-5379-14-git-send-email-hao.wu@intel.com>
On Sun, Mar 24, 2019 at 10:24 PM Wu Hao <hao.wu@intel.com> wrote:
Hi Hao,
Looks good...
>
> This patch adds 3 read-only sysfs interfaces for FPGA Management Engine
> (FME) block for capabilities including cache_size, fabric_version and
> socket_id.
>
> Signed-off-by: Luwei Kang <luwei.kang@intel.com>
> Signed-off-by: Xu Yilun <yilun.xu@intel.com>
> Signed-off-by: Wu Hao <hao.wu@intel.com>
Acked-by: Alan Tull <atull@kernel.org>
Thanks,
Alan
> ---
> Documentation/ABI/testing/sysfs-platform-dfl-fme | 23 ++++++++++++
> drivers/fpga/dfl-fme-main.c | 48 ++++++++++++++++++++++++
> 2 files changed, 71 insertions(+)
>
> diff --git a/Documentation/ABI/testing/sysfs-platform-dfl-fme b/Documentation/ABI/testing/sysfs-platform-dfl-fme
> index 8fa4feb..b8327e9 100644
> --- a/Documentation/ABI/testing/sysfs-platform-dfl-fme
> +++ b/Documentation/ABI/testing/sysfs-platform-dfl-fme
> @@ -21,3 +21,26 @@ Contact: Wu Hao <hao.wu@intel.com>
> Description: Read-only. It returns Bitstream (static FPGA region) meta
> data, which includes the synthesis date, seed and other
> information of this static FPGA region.
> +
> +What: /sys/bus/platform/devices/dfl-fme.0/cache_size
> +Date: March 2019
> +KernelVersion: 5.2
> +Contact: Wu Hao <hao.wu@intel.com>
> +Description: Read-only. It returns cache size of this FPGA device.
> +
> +What: /sys/bus/platform/devices/dfl-fme.0/fabric_version
> +Date: March 2019
> +KernelVersion: 5.2
> +Contact: Wu Hao <hao.wu@intel.com>
> +Description: Read-only. It returns fabric version of this FPGA device.
> + Userspace applications need this information to select
> + best data channels per different fabric design.
> +
> +What: /sys/bus/platform/devices/dfl-fme.0/socket_id
> +Date: March 2019
> +KernelVersion: 5.2
> +Contact: Wu Hao <hao.wu@intel.com>
> +Description: Read-only. It returns socket_id to indicate which socket
> + this FPGA belongs to, only valid for integrated solution.
> + User only needs this information, in case standard numa node
> + can't provide correct information.
> diff --git a/drivers/fpga/dfl-fme-main.c b/drivers/fpga/dfl-fme-main.c
> index 38c6342..8339ee8 100644
> --- a/drivers/fpga/dfl-fme-main.c
> +++ b/drivers/fpga/dfl-fme-main.c
> @@ -75,10 +75,58 @@ static ssize_t bitstream_metadata_show(struct device *dev,
> }
> static DEVICE_ATTR_RO(bitstream_metadata);
>
> +static ssize_t cache_size_show(struct device *dev,
> + struct device_attribute *attr, char *buf)
> +{
> + void __iomem *base;
> + u64 v;
> +
> + base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_HEADER);
> +
> + v = readq(base + FME_HDR_CAP);
> +
> + return scnprintf(buf, PAGE_SIZE, "%u\n",
> + (unsigned int)FIELD_GET(FME_CAP_CACHE_SIZE, v));
> +}
> +static DEVICE_ATTR_RO(cache_size);
> +
> +static ssize_t fabric_version_show(struct device *dev,
> + struct device_attribute *attr, char *buf)
> +{
> + void __iomem *base;
> + u64 v;
> +
> + base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_HEADER);
> +
> + v = readq(base + FME_HDR_CAP);
> +
> + return scnprintf(buf, PAGE_SIZE, "%u\n",
> + (unsigned int)FIELD_GET(FME_CAP_FABRIC_VERID, v));
> +}
> +static DEVICE_ATTR_RO(fabric_version);
> +
> +static ssize_t socket_id_show(struct device *dev,
> + struct device_attribute *attr, char *buf)
> +{
> + void __iomem *base;
> + u64 v;
> +
> + base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_HEADER);
> +
> + v = readq(base + FME_HDR_CAP);
> +
> + return scnprintf(buf, PAGE_SIZE, "%u\n",
> + (unsigned int)FIELD_GET(FME_CAP_SOCKET_ID, v));
> +}
> +static DEVICE_ATTR_RO(socket_id);
> +
> static const struct attribute *fme_hdr_attrs[] = {
> &dev_attr_ports_num.attr,
> &dev_attr_bitstream_id.attr,
> &dev_attr_bitstream_metadata.attr,
> + &dev_attr_cache_size.attr,
> + &dev_attr_fabric_version.attr,
> + &dev_attr_socket_id.attr,
> NULL,
> };
>
> --
> 2.7.4
>
next prev parent reply other threads:[~2019-04-09 21:05 UTC|newest]
Thread overview: 62+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-25 3:07 [PATCH 00/17] add new features for FPGA DFL drivers Wu Hao
2019-03-25 3:07 ` [PATCH 01/17] fpga: dfl-fme-mgr: fix FME_PR_INTFC_ID register address Wu Hao
2019-03-25 17:28 ` Alan Tull
2019-04-01 19:54 ` Moritz Fischer
2019-04-02 4:38 ` Wu Hao
2019-04-02 13:33 ` Moritz Fischer
2019-03-25 3:07 ` [PATCH 02/17] fpga: dfl: fme: align PR buffer size per PR datawidth Wu Hao
2019-03-25 17:50 ` Alan Tull
2019-03-26 0:28 ` Wu Hao
2019-03-28 18:50 ` Alan Tull
2019-03-25 3:07 ` [PATCH 03/17] fpga: dfl: fme: support 512bit data width PR Wu Hao
2019-03-25 18:48 ` Alan Tull
2019-03-25 22:53 ` Scott Wood
2019-03-25 22:58 ` Scott Wood
2019-03-26 19:33 ` Alan Tull
2019-03-26 21:22 ` Scott Wood
2019-03-27 4:37 ` Wu Hao
2019-03-27 6:10 ` Scott Wood
2019-03-27 6:03 ` Wu Hao
2019-03-27 5:10 ` Wu Hao
2019-03-27 6:19 ` Scott Wood
2019-03-27 7:10 ` Wu Hao
2019-03-27 5:46 ` Wu Hao
2019-03-25 3:07 ` [PATCH 04/17] Documentation: fpga: dfl: add descriptions for virtualization and new interfaces Wu Hao
2019-03-25 3:07 ` [PATCH 05/17] fpga: dfl: fme: add DFL_FPGA_FME_PORT_RELEASE/ASSIGN ioctl support Wu Hao
2019-03-28 22:03 ` Alan Tull
2019-03-25 3:07 ` [PATCH 06/17] fpga: dfl: pci: enable SRIOV support Wu Hao
2019-03-28 22:03 ` Alan Tull
2019-03-25 3:07 ` [PATCH 07/17] fpga: dfl: afu: add AFU state related sysfs interfaces Wu Hao
2019-03-28 17:13 ` Alan Tull
2019-03-25 3:07 ` [PATCH 08/17] fpga: dfl: afu: add userclock " Wu Hao
2019-04-01 21:41 ` Alan Tull
2019-03-25 3:07 ` [PATCH 09/17] fpga: dfl: add id_table for dfl private feature driver Wu Hao
2019-04-02 15:09 ` Moritz Fischer
2019-04-11 20:55 ` Alan Tull
2019-03-25 3:07 ` [PATCH 10/17] fpga: dfl: afu: export __port_enable/disable function Wu Hao
2019-04-02 15:50 ` Moritz Fischer
2019-04-11 20:45 ` Alan Tull
2019-03-25 3:07 ` [PATCH 11/17] fpga: dfl: afu: add error reporting support Wu Hao
2019-04-09 20:57 ` Alan Tull
2019-04-10 1:43 ` Wu Hao
2019-03-25 3:07 ` [PATCH 12/17] fpga: dfl: afu: add STP (SignalTap) support Wu Hao
2019-04-02 15:07 ` Moritz Fischer
2019-04-11 20:41 ` Alan Tull
2019-03-25 3:07 ` [PATCH 13/17] fpga: dfl: fme: add capability sysfs interfaces Wu Hao
2019-04-09 21:05 ` Alan Tull [this message]
2019-03-25 3:07 ` [PATCH 14/17] fpga: dfl: fme: add thermal management support Wu Hao
2019-04-02 14:59 ` Moritz Fischer
2019-04-03 16:31 ` Wu Hao
2019-04-03 18:09 ` Moritz Fischer
2019-04-03 23:43 ` Wu Hao
2019-03-25 3:07 ` [PATCH 15/17] fpga: dfl: fme: add power " Wu Hao
2019-04-11 20:07 ` Alan Tull
2019-04-12 2:50 ` Wu Hao
2019-04-15 21:17 ` Alan Tull
2019-04-17 7:36 ` Wu Hao
2019-04-12 21:05 ` Moritz Fischer
2019-04-17 7:31 ` Wu Hao
2019-03-25 3:07 ` [PATCH 16/17] fpga: dfl: fme: add global error reporting support Wu Hao
2019-04-09 21:35 ` Alan Tull
2019-04-10 1:34 ` Wu Hao
2019-03-25 3:07 ` [PATCH 17/17] fpga: dfl: fme: add performance " Wu Hao
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=CANk1AXQvsUYHmyZ7XF2LD+eNQ2FV33HageL0Mgbt7-9YVaagdw@mail.gmail.com \
--to=atull@kernel.org \
--cc=hao.wu@intel.com \
--cc=linux-api@vger.kernel.org \
--cc=linux-fpga@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=luwei.kang@intel.com \
--cc=mdf@kernel.org \
--cc=yilun.xu@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).