From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752020AbdLDTrn (ORCPT ); Mon, 4 Dec 2017 14:47:43 -0500 Received: from mail.kernel.org ([198.145.29.99]:46816 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751428AbdLDTrl (ORCPT ); Mon, 4 Dec 2017 14:47:41 -0500 DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 5A41D218C9 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=atull@kernel.org X-Google-Smtp-Source: AGs4zMbUMquXvAIbWyHEOxdVE91KB87g/YA2TDNhPHbfVuoVIASGwY0FgRO1UHdRNI/w1EOPJXgFeZ8oWS86/HwGRVA= MIME-Version: 1.0 In-Reply-To: <20171128031519.GA25705@hao-dev> References: <1511764948-20972-1-git-send-email-hao.wu@intel.com> <1511764948-20972-9-git-send-email-hao.wu@intel.com> <20171128031519.GA25705@hao-dev> From: Alan Tull Date: Mon, 4 Dec 2017 13:46:59 -0600 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v3 08/21] fpga: add Intel FPGA DFL PCIe device To: Wu Hao Cc: David Laight , "mdf@kernel.org" , "linux-fpga@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-api@vger.kernel.org" , "luwei.kang@intel.com" , "yi.z.zhang@intel.com" , Tim Whisonant , Enno Luebbers , Shiva Rao , Christopher Rauer , Xiao Guangrong Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Nov 27, 2017 at 9:15 PM, Wu Hao wrote: > On Mon, Nov 27, 2017 at 10:28:04AM +0000, David Laight wrote: >> From: Wu Hao >> > Sent: 27 November 2017 06:42 >> > From: Zhang Yi >> > >> > The Intel FPGA device appears as a PCIe device on the system. This patch >> > implements the basic framework of the driver for Intel PCIe device which >> > is located between CPU and Accelerated Function Units (AFUs), and has >> > the Device Feature List (DFL) implemented in its MMIO space. >> >> This ought to have a better name than 'Intel FPGA'. >> An fpga can be used for all sorts of things, this looks like >> a very specific architecture using a common VHDL environment to >> allow certain types of user VHDL be accessed over PCIe. > > Hi David > > This patch adds a pcie device driver for Intel FPGA devices which implements > the DFL, e.g Intel Server Platform with In-package FPGA and Intel FPGA PCIe > Acceleration Cards. They are pcie devices, and all have DFL implemented in > the MMIO space, so we would like to use one kernel driver to handle them. > > With this full patchset, it just provides user the interfaces to configure > and access the FPGA accelerators on Intel DFL based FPGA devices. For sure, > users can develop and build their own logics via tools provided by Intel, > program them to accelerators on these Intel FPGA devices, and access them > for their workloads. I don't see anything Intel specific here. This could all be named dfl-* Alan > > Thanks > Hao