From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752137AbdLFPaT (ORCPT ); Wed, 6 Dec 2017 10:30:19 -0500 Received: from mail.kernel.org ([198.145.29.99]:37962 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751453AbdLFPaR (ORCPT ); Wed, 6 Dec 2017 10:30:17 -0500 DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 73F4221985 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=atull@kernel.org X-Google-Smtp-Source: AGs4zMaNMYucb6IydbMZeTXH3vlhfcdepEZP3xKZpVx5x34PF6SH4uiuaTulD7+D6irUXXPPcuEXSZohwhLJg/cOwhk= MIME-Version: 1.0 In-Reply-To: References: <1511764948-20972-1-git-send-email-hao.wu@intel.com> <1511764948-20972-9-git-send-email-hao.wu@intel.com> <20171128031519.GA25705@hao-dev> <20171205033330.GA19730@hao-dev> <20171206053015.GA19023@hao-dev> From: Alan Tull Date: Wed, 6 Dec 2017 09:29:34 -0600 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v3 08/21] fpga: add Intel FPGA DFL PCIe device To: David Laight Cc: Wu Hao , "mdf@kernel.org" , "linux-fpga@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-api@vger.kernel.org" , "luwei.kang@intel.com" , "yi.z.zhang@intel.com" , Tim Whisonant , Enno Luebbers , Shiva Rao , Christopher Rauer , Xiao Guangrong Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Dec 6, 2017 at 3:44 AM, David Laight wrote: > From: Wu Hao >> Sent: 06 December 2017 05:30 > ... >> > Regarding file names, it seems like the files added to drivers/fpga >> > could be uniformly named dfl-*.[ch]. Some are fpga-dfl-*.[ch] while >> > other are currently dfl-*.[ch] currently. > > They don't even want to do into a drivers/fgpa directory. > Maybe drivers/dfl or drivers/dfl/intel It's plugged into the fpga framework in drivers/fpga. This patchset also handles reprogramming the fpga, not just the dfl style enumeration. But your points about this being not just for FPGA are interesting to me. Do you have a use for this that isn't FPGA-centric? Alan > > David >