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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=XrncbmxfYlp9PSdBmkEvXZfFiQoM7LAT+7nJ0SOKuE0=; b=TcBHKpPweuSfifNOxbidI6GPyyx8eHOR9HmY7IYjbiUh3sRPEGxTygro1kdKoTiCPO cIy+gDif0BQFs2jrLHI2aW/zuDLmJ3+ththvR9Jginf4yIfjwXYUf3qJJcJGe5+9uZpw 0+7WEkDHfpkmCJNUCpWqCzaFgTkb6yq6JRuIBidr4srQaxn6BHhjUu3fqVVs6rR2jcED W15P/8QQb5+uIqeXoCycpcgIfgXp5k8+hr9PF+5rBPyeeXNNLntezLXAOtc52VOk0aJ2 Ex7FMv1Q4E5o/0DYOh0oUGho6P7VLoCO9pDwgHyQXPdVzTOsSMgISU63J9DsR1XytAcF RWOQ== X-Gm-Message-State: APt69E2uQAnW/PruHNEoO6GJ5Wopx6rNfHyqvitQMv2r18CNd8UNcGjP 7/UV/j5ofbnlxVUpk2XhWO9e9grOzwv1V8AAhYQ= X-Google-Smtp-Source: ADUXVKKQvrbysRkJnO3kGuHK2ANJFdQWEtLUusx4Z8BDUY1GiJcoghVFiClm+B+jkXQNtMyyki39Srtry5nYjxrm+XU= X-Received: by 2002:a9d:56e8:: with SMTP id b37-v6mr6365157otj.175.1529294442241; Sun, 17 Jun 2018 21:00:42 -0700 (PDT) MIME-Version: 1.0 Received: by 2002:a9d:1049:0:0:0:0:0 with HTTP; Sun, 17 Jun 2018 21:00:41 -0700 (PDT) In-Reply-To: <20180226134741.neqkpge33zo3pfzt@earth.universe> References: <20180212123945.15732-1-sebastian.reichel@collabora.co.uk> <20180212123945.15732-2-sebastian.reichel@collabora.co.uk> <20180224074543.GF3217@dragon> <20180226134741.neqkpge33zo3pfzt@earth.universe> From: Fabio Estevam Date: Mon, 18 Jun 2018 01:00:41 -0300 Message-ID: Subject: Re: [PATCHv4 1/2] ARM: imx53: add secure-reg-access support for PMU To: Sebastian Reichel , Martin Fuzzey Cc: Shawn Guo , Mark Rutland , Will Deacon , Russell King , linux-kernel , Ian Ray , Sascha Hauer , Nandor Han , Fabio Estevam , kernel@collabora.com, "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Sebastian, [Adding Martin on Cc who also tried to enable DBGEN bit in a previous patch] On Mon, Feb 26, 2018 at 10:47 AM, Sebastian Reichel wrote: > Hi Shawn, > > On Sat, Feb 24, 2018 at 03:45:44PM +0800, Shawn Guo wrote: >> On Mon, Feb 12, 2018 at 01:39:44PM +0100, Sebastian Reichel wrote: >> > On i.MX53 it is necessary to set the DBG_EN bit in the >> > platform GPC register to enable access to PMU counters >> > other than the cycle counter. >> > >> > Signed-off-by: Sebastian Reichel >> > --- >> > arch/arm/mach-imx/mach-imx53.c | 39 ++++++++++++++++++++++++++++++++++++++- >> > 1 file changed, 38 insertions(+), 1 deletion(-) >> > >> > diff --git a/arch/arm/mach-imx/mach-imx53.c b/arch/arm/mach-imx/mach-imx53.c >> > index 07c2e8dca494..658e28604dca 100644 >> > --- a/arch/arm/mach-imx/mach-imx53.c >> > +++ b/arch/arm/mach-imx/mach-imx53.c >> > @@ -28,10 +28,47 @@ static void __init imx53_init_early(void) >> > mxc_set_cpu_type(MXC_CPU_MX53); >> > } >> > >> > +#define MXC_CORTEXA8_PLAT_GPC 0x63fa0004 >> >> The base address should be retrieved from device tree. > > DT has no entry for 0x63fa0000-0x63fa3fff. iMX53 TRM lists it as "ARM Platform" > with 8 platform specific 32 bit registers. Do you think it's worth the trouble > adding a new binding? Do you have a suggestion for a compatible value? I also think we should add a compatible string for the "ARM platform" region. This way both mx51 and mx53 could retrieve the base address from the device tree. What about: --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi @@ -672,6 +672,11 @@ status = "disabled"; }; + arm_plat: arm-plat@63fa0000 { + compatible = "fsl,imx53-arm-plat", "fsl,imx51-arm-plat"; + reg = <0x63fa0000 0x4000>; + }; + owire: owire@63fa4000 { compatible = "fsl,imx53-owire", "fsl,imx21-owire"; reg = <0x63fa4000 0x4000>;