* [PATCH] arm64: dts: fsl: imx8mq: enable the thermal management unit (TMU)
@ 2019-03-11 21:31 Angus Ainslie (Purism)
2019-03-12 2:35 ` Andrey Smirnov
` (5 more replies)
0 siblings, 6 replies; 16+ messages in thread
From: Angus Ainslie (Purism) @ 2019-03-11 21:31 UTC (permalink / raw)
To: Mark Rutland
Cc: Rob Herring, Shawn Guo, Fabio Estevam, kernel, Lucas Stach,
abel.vesa, daniel.baluta, agx, linux-imx, devicetree,
linux-kernel, Angus Ainslie (Purism)
These are the TMU nodes from the NXP vendor kernel
Signed-off-by: Angus Ainslie (Purism) <angus@akkea.ca>
---
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 83 +++++++++++++++++++++++
1 file changed, 83 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index 9155bd4784eb..087620c6e17f 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -8,6 +8,7 @@
#include <dt-bindings/power/imx8mq-power.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/thermal/thermal.h>
#include "imx8mq-pinfunc.h"
/ {
@@ -89,6 +90,7 @@
reg = <0x0>;
enable-method = "psci";
next-level-cache = <&A53_L2>;
+ #cooling-cells = <2>;
};
A53_1: cpu@1 {
@@ -210,6 +212,87 @@
#interrupt-cells = <2>;
};
+ tmu: tmu@30260000 {
+ compatible = "fsl,imx8mq-tmu";
+ reg = <0x30260000 0x10000>;
+ interrupt = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ little-endian;
+ fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>;
+ fsl,tmu-calibration = <0x00000000 0x00000023
+ 0x00000001 0x00000029
+ 0x00000002 0x0000002f
+ 0x00000003 0x00000035
+ 0x00000004 0x0000003d
+ 0x00000005 0x00000043
+ 0x00000006 0x0000004b
+ 0x00000007 0x00000051
+ 0x00000008 0x00000057
+ 0x00000009 0x0000005f
+ 0x0000000a 0x00000067
+ 0x0000000b 0x0000006f
+
+ 0x00010000 0x0000001b
+ 0x00010001 0x00000023
+ 0x00010002 0x0000002b
+ 0x00010003 0x00000033
+ 0x00010004 0x0000003b
+ 0x00010005 0x00000043
+ 0x00010006 0x0000004b
+ 0x00010007 0x00000055
+ 0x00010008 0x0000005d
+ 0x00010009 0x00000067
+ 0x0001000a 0x00000070
+
+ 0x00020000 0x00000017
+ 0x00020001 0x00000023
+ 0x00020002 0x0000002d
+ 0x00020003 0x00000037
+ 0x00020004 0x00000041
+ 0x00020005 0x0000004b
+ 0x00020006 0x00000057
+ 0x00020007 0x00000063
+ 0x00020008 0x0000006f
+
+ 0x00030000 0x00000015
+ 0x00030001 0x00000021
+ 0x00030002 0x0000002d
+ 0x00030003 0x00000039
+ 0x00030004 0x00000045
+ 0x00030005 0x00000053
+ 0x00030006 0x0000005f
+ 0x00030007 0x00000071>;
+ #thermal-sensor-cells = <0>;
+ };
+
+ thermal-zones {
+ cpu-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <2000>;
+ thermal-sensors = <&tmu>;
+
+ trips {
+ cpu_alert0: trip0 {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu_crit0: trip1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert0>;
+ cooling-device = <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+ };
+
wdog1: watchdog@30280000 {
compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
reg = <0x30280000 0x10000>;
--
2.17.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH] arm64: dts: fsl: imx8mq: enable the thermal management unit (TMU)
2019-03-11 21:31 [PATCH] arm64: dts: fsl: imx8mq: enable the thermal management unit (TMU) Angus Ainslie (Purism)
@ 2019-03-12 2:35 ` Andrey Smirnov
2019-03-12 12:54 ` Angus Ainslie
2019-03-12 20:18 ` Angus Ainslie
2019-03-18 15:48 ` [PATCH v2] " Angus Ainslie (Purism)
` (4 subsequent siblings)
5 siblings, 2 replies; 16+ messages in thread
From: Andrey Smirnov @ 2019-03-12 2:35 UTC (permalink / raw)
To: Angus Ainslie (Purism)
Cc: Mark Rutland, Rob Herring, Shawn Guo, Fabio Estevam,
Sascha Hauer, Lucas Stach, Abel Vesa, daniel.baluta, agx,
dl-linux-imx,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-kernel
On Mon, Mar 11, 2019 at 2:35 PM Angus Ainslie (Purism) <angus@akkea.ca> wrote:
>
> These are the TMU nodes from the NXP vendor kernel
>
Hey Angus,
TMU block supports multiple thermal zones and vendor kernel doesn't
really account for that (see below). Latest version of the driver in
thermal tree now actually supports that feature (mulit-sensor), so I
think the code in DT should reflect that as well. I recently submitted
a series adding HWMON integration for TMU
(https://lore.kernel.org/lkml/20190222200508.26325-1-andrew.smirnov@gmail.com/T/#u)
and this is my take on this patch:
https://github.com/ndreys/linux/commit/09931e3d60af0a74377307b433db97da1be31570
All of the code there is up for grabs, if you feel like using it.
> Signed-off-by: Angus Ainslie (Purism) <angus@akkea.ca>
> ---
> arch/arm64/boot/dts/freescale/imx8mq.dtsi | 83 +++++++++++++++++++++++
> 1 file changed, 83 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> index 9155bd4784eb..087620c6e17f 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> @@ -8,6 +8,7 @@
> #include <dt-bindings/power/imx8mq-power.h>
> #include <dt-bindings/gpio/gpio.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/thermal/thermal.h>
> #include "imx8mq-pinfunc.h"
>
> / {
> @@ -89,6 +90,7 @@
> reg = <0x0>;
> enable-method = "psci";
> next-level-cache = <&A53_L2>;
> + #cooling-cells = <2>;
> };
>
> A53_1: cpu@1 {
> @@ -210,6 +212,87 @@
> #interrupt-cells = <2>;
> };
>
> + tmu: tmu@30260000 {
> + compatible = "fsl,imx8mq-tmu";
> + reg = <0x30260000 0x10000>;
> + interrupt = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
> + little-endian;
> + fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>;
> + fsl,tmu-calibration = <0x00000000 0x00000023
> + 0x00000001 0x00000029
> + 0x00000002 0x0000002f
> + 0x00000003 0x00000035
> + 0x00000004 0x0000003d
> + 0x00000005 0x00000043
> + 0x00000006 0x0000004b
> + 0x00000007 0x00000051
> + 0x00000008 0x00000057
> + 0x00000009 0x0000005f
> + 0x0000000a 0x00000067
> + 0x0000000b 0x0000006f
> +
> + 0x00010000 0x0000001b
> + 0x00010001 0x00000023
> + 0x00010002 0x0000002b
> + 0x00010003 0x00000033
> + 0x00010004 0x0000003b
> + 0x00010005 0x00000043
> + 0x00010006 0x0000004b
> + 0x00010007 0x00000055
> + 0x00010008 0x0000005d
> + 0x00010009 0x00000067
> + 0x0001000a 0x00000070
> +
> + 0x00020000 0x00000017
> + 0x00020001 0x00000023
> + 0x00020002 0x0000002d
> + 0x00020003 0x00000037
> + 0x00020004 0x00000041
> + 0x00020005 0x0000004b
> + 0x00020006 0x00000057
> + 0x00020007 0x00000063
> + 0x00020008 0x0000006f
> +
> + 0x00030000 0x00000015
> + 0x00030001 0x00000021
> + 0x00030002 0x0000002d
> + 0x00030003 0x00000039
> + 0x00030004 0x00000045
> + 0x00030005 0x00000053
> + 0x00030006 0x0000005f
> + 0x00030007 0x00000071>;
> + #thermal-sensor-cells = <0>;
As per #thermal-sensor-cells must be 1 (see
Documentation/devicetree/bindings/thermal/qoriq-thermal.txt), since as
I mentioned above there are multiple thermal zones (CPU, GPU, VPU).
> + };
> +
> + thermal-zones {
> + cpu-thermal {
> + polling-delay-passive = <250>;
> + polling-delay = <2000>;
> + thermal-sensors = <&tmu>;
Ditto.
Thanks,
Andrey Smirnov
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH] arm64: dts: fsl: imx8mq: enable the thermal management unit (TMU)
2019-03-12 2:35 ` Andrey Smirnov
@ 2019-03-12 12:54 ` Angus Ainslie
2019-03-12 20:18 ` Angus Ainslie
1 sibling, 0 replies; 16+ messages in thread
From: Angus Ainslie @ 2019-03-12 12:54 UTC (permalink / raw)
To: Andrey Smirnov
Cc: Mark Rutland, Rob Herring, Shawn Guo, Fabio Estevam,
Sascha Hauer, Lucas Stach, Abel Vesa, daniel.baluta, agx,
dl-linux-imx,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-kernel
On 2019-03-11 19:35, Andrey Smirnov wrote:
> On Mon, Mar 11, 2019 at 2:35 PM Angus Ainslie (Purism) <angus@akkea.ca>
> wrote:
>>
>> These are the TMU nodes from the NXP vendor kernel
>>
>
> Hey Angus,
>
> TMU block supports multiple thermal zones and vendor kernel doesn't
> really account for that (see below). Latest version of the driver in
> thermal tree now actually supports that feature (mulit-sensor), so I
> think the code in DT should reflect that as well. I recently submitted
> a series adding HWMON integration for TMU
> (https://lore.kernel.org/lkml/20190222200508.26325-1-andrew.smirnov@gmail.com/T/#u)
> and this is my take on this patch:
>
> https://github.com/ndreys/linux/commit/09931e3d60af0a74377307b433db97da1be31570
>
> All of the code there is up for grabs, if you feel like using it.
Thanks, I would prefer to use the multi sensor code but I assumed it
wasn't in yet so I followed
Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
I'll try some testing with the DT fragment you suggested.
>
>> Signed-off-by: Angus Ainslie (Purism) <angus@akkea.ca>
>> ---
>> arch/arm64/boot/dts/freescale/imx8mq.dtsi | 83
>> +++++++++++++++++++++++
>> 1 file changed, 83 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
>> b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
>> index 9155bd4784eb..087620c6e17f 100644
>> --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
>> +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
>> @@ -8,6 +8,7 @@
>> #include <dt-bindings/power/imx8mq-power.h>
>> #include <dt-bindings/gpio/gpio.h>
>> #include <dt-bindings/interrupt-controller/arm-gic.h>
>> +#include <dt-bindings/thermal/thermal.h>
>> #include "imx8mq-pinfunc.h"
>>
>> / {
>> @@ -89,6 +90,7 @@
>> reg = <0x0>;
>> enable-method = "psci";
>> next-level-cache = <&A53_L2>;
>> + #cooling-cells = <2>;
>> };
>>
>> A53_1: cpu@1 {
>> @@ -210,6 +212,87 @@
>> #interrupt-cells = <2>;
>> };
>>
>> + tmu: tmu@30260000 {
>> + compatible = "fsl,imx8mq-tmu";
>> + reg = <0x30260000 0x10000>;
>> + interrupt = <GIC_SPI 49
>> IRQ_TYPE_LEVEL_HIGH>;
>> + little-endian;
>> + fsl,tmu-range = <0xb0000 0xa0026
>> 0x80048 0x70061>;
>> + fsl,tmu-calibration = <0x00000000
>> 0x00000023
>> + 0x00000001
>> 0x00000029
>> + 0x00000002
>> 0x0000002f
>> + 0x00000003
>> 0x00000035
>> + 0x00000004
>> 0x0000003d
>> + 0x00000005
>> 0x00000043
>> + 0x00000006
>> 0x0000004b
>> + 0x00000007
>> 0x00000051
>> + 0x00000008
>> 0x00000057
>> + 0x00000009
>> 0x0000005f
>> + 0x0000000a
>> 0x00000067
>> + 0x0000000b
>> 0x0000006f
>> +
>> + 0x00010000
>> 0x0000001b
>> + 0x00010001
>> 0x00000023
>> + 0x00010002
>> 0x0000002b
>> + 0x00010003
>> 0x00000033
>> + 0x00010004
>> 0x0000003b
>> + 0x00010005
>> 0x00000043
>> + 0x00010006
>> 0x0000004b
>> + 0x00010007
>> 0x00000055
>> + 0x00010008
>> 0x0000005d
>> + 0x00010009
>> 0x00000067
>> + 0x0001000a
>> 0x00000070
>> +
>> + 0x00020000
>> 0x00000017
>> + 0x00020001
>> 0x00000023
>> + 0x00020002
>> 0x0000002d
>> + 0x00020003
>> 0x00000037
>> + 0x00020004
>> 0x00000041
>> + 0x00020005
>> 0x0000004b
>> + 0x00020006
>> 0x00000057
>> + 0x00020007
>> 0x00000063
>> + 0x00020008
>> 0x0000006f
>> +
>> + 0x00030000
>> 0x00000015
>> + 0x00030001
>> 0x00000021
>> + 0x00030002
>> 0x0000002d
>> + 0x00030003
>> 0x00000039
>> + 0x00030004
>> 0x00000045
>> + 0x00030005
>> 0x00000053
>> + 0x00030006
>> 0x0000005f
>> + 0x00030007
>> 0x00000071>;
>> + #thermal-sensor-cells = <0>;
>
> As per #thermal-sensor-cells must be 1 (see
> Documentation/devicetree/bindings/thermal/qoriq-thermal.txt), since as
> I mentioned above there are multiple thermal zones (CPU, GPU, VPU).
Thanks I missed that bringing it over.
Angus Ainslie
>
>> + };
>> +
>> + thermal-zones {
>> + cpu-thermal {
>> + polling-delay-passive = <250>;
>> + polling-delay = <2000>;
>> + thermal-sensors = <&tmu>;
>
> Ditto.
>
> Thanks,
> Andrey Smirnov
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH] arm64: dts: fsl: imx8mq: enable the thermal management unit (TMU)
2019-03-12 2:35 ` Andrey Smirnov
2019-03-12 12:54 ` Angus Ainslie
@ 2019-03-12 20:18 ` Angus Ainslie
2019-03-12 20:32 ` Fabio Estevam
2019-03-13 0:31 ` Andrey Smirnov
1 sibling, 2 replies; 16+ messages in thread
From: Angus Ainslie @ 2019-03-12 20:18 UTC (permalink / raw)
To: Andrey Smirnov
Cc: Mark Rutland, Rob Herring, Shawn Guo, Fabio Estevam,
Sascha Hauer, Lucas Stach, Abel Vesa, daniel.baluta, agx,
dl-linux-imx,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-kernel
Hi Andrey,
On 2019-03-11 19:35, Andrey Smirnov wrote:
> On Mon, Mar 11, 2019 at 2:35 PM Angus Ainslie (Purism) <angus@akkea.ca>
> wrote:
>>
>> These are the TMU nodes from the NXP vendor kernel
>>
>
> Hey Angus,
>
> TMU block supports multiple thermal zones and vendor kernel doesn't
> really account for that (see below). Latest version of the driver in
> thermal tree now actually supports that feature (mulit-sensor), so I
> think the code in DT should reflect that as well. I recently submitted
> a series adding HWMON integration for TMU
> (https://lore.kernel.org/lkml/20190222200508.26325-1-andrew.smirnov@gmail.com/T/#u)
I tried applying those to linux-next. They don't apply very cleanly
there so I gave up.
> and this is my take on this patch:
>
> https://github.com/ndreys/linux/commit/09931e3d60af0a74377307b433db97da1be31570
>
> All of the code there is up for grabs, if you feel like using it.
>
I followed that and I have a version that works with linux-next that
does not include the GPU
and VPU parts.
I also tested a version with the GPU and VPU parts and it "works" but
creates 2 useless
paths in /sys/class/thermal .
Should I wait for your changes to get into linux-next or resubmit a
version that works with the current one ?
Thanks
Angus
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH] arm64: dts: fsl: imx8mq: enable the thermal management unit (TMU)
2019-03-12 20:18 ` Angus Ainslie
@ 2019-03-12 20:32 ` Fabio Estevam
2019-03-13 0:31 ` Andrey Smirnov
1 sibling, 0 replies; 16+ messages in thread
From: Fabio Estevam @ 2019-03-12 20:32 UTC (permalink / raw)
To: Angus Ainslie
Cc: Andrey Smirnov, Mark Rutland, Rob Herring, Shawn Guo,
Sascha Hauer, Lucas Stach, Abel Vesa, Daniel Baluta,
Guido Günther, dl-linux-imx,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-kernel
Hi Angus,
On Tue, Mar 12, 2019 at 5:19 PM Angus Ainslie <angus@akkea.ca> wrote:
> I tried applying those to linux-next. They don't apply very cleanly
> there so I gave up.
You need to apply this commit first:
https://git.kernel.org/pub/scm/linux/kernel/git/evalenti/linux-soc-thermal.git/patch/?id=7797ff424818c975b59c35880dbc90fe08350204
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH] arm64: dts: fsl: imx8mq: enable the thermal management unit (TMU)
2019-03-12 20:18 ` Angus Ainslie
2019-03-12 20:32 ` Fabio Estevam
@ 2019-03-13 0:31 ` Andrey Smirnov
1 sibling, 0 replies; 16+ messages in thread
From: Andrey Smirnov @ 2019-03-13 0:31 UTC (permalink / raw)
To: Angus Ainslie
Cc: Mark Rutland, Rob Herring, Shawn Guo, Fabio Estevam,
Sascha Hauer, Lucas Stach, Abel Vesa, daniel.baluta, agx,
dl-linux-imx,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-kernel
On Tue, Mar 12, 2019 at 1:19 PM Angus Ainslie <angus@akkea.ca> wrote:
>
> Hi Andrey,
>
> On 2019-03-11 19:35, Andrey Smirnov wrote:
> > On Mon, Mar 11, 2019 at 2:35 PM Angus Ainslie (Purism) <angus@akkea.ca>
> > wrote:
> >>
> >> These are the TMU nodes from the NXP vendor kernel
> >>
> >
> > Hey Angus,
> >
> > TMU block supports multiple thermal zones and vendor kernel doesn't
> > really account for that (see below). Latest version of the driver in
> > thermal tree now actually supports that feature (mulit-sensor), so I
> > think the code in DT should reflect that as well. I recently submitted
> > a series adding HWMON integration for TMU
> > (https://lore.kernel.org/lkml/20190222200508.26325-1-andrew.smirnov@gmail.com/T/#u)
>
> I tried applying those to linux-next. They don't apply very cleanly
> there so I gave up.
>
> > and this is my take on this patch:
> >
> > https://github.com/ndreys/linux/commit/09931e3d60af0a74377307b433db97da1be31570
> >
> > All of the code there is up for grabs, if you feel like using it.
> >
>
> I followed that and I have a version that works with linux-next that
> does not include the GPU
> and VPU parts.
>
> I also tested a version with the GPU and VPU parts and it "works" but
> creates 2 useless
> paths in /sys/class/thermal .
>
> Should I wait for your changes to get into linux-next or resubmit a
> version that works with the current one ?
>
You don't really need my changes for multi sensor support, only the
patch Fabio pointed to. You can send the patch sans GPU and VPU nodes
to get it in sooner or you can wait until multi-sensor support patch
trickles down to get all in in a single patch. All options are fine by
me, so it's up to you and Shawn I'd say.
Thanks,
Andrey Smirnov
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v2] arm64: dts: fsl: imx8mq: enable the thermal management unit (TMU)
2019-03-11 21:31 [PATCH] arm64: dts: fsl: imx8mq: enable the thermal management unit (TMU) Angus Ainslie (Purism)
2019-03-12 2:35 ` Andrey Smirnov
@ 2019-03-18 15:48 ` Angus Ainslie (Purism)
2019-03-18 16:04 ` [PATCH] arm64: dts: fsl: imx8mq: enable the multi sensor TMU Angus Ainslie (Purism)
` (3 subsequent siblings)
5 siblings, 0 replies; 16+ messages in thread
From: Angus Ainslie (Purism) @ 2019-03-18 15:48 UTC (permalink / raw)
To: angus, andrew.smirnov
Cc: Rob Herring, Mark Rutland, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team,
Lucas Stach, Carlo Caione, Abel Vesa, Baruch Siach,
Guido Günther, devicetree, linux-arm-kernel, linux-kernel
Add the TMU node for the CPU
Changes since v1:
Fixed the muber of sensor cells to work with or without the multi
sensors patch.
Signed-off-by: Angus Ainslie (Purism) <angus@akkea.ca>
---
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 90 +++++++++++++++++++++++
1 file changed, 90 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index 9155bd4784eb..d367aa0023c4 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -8,6 +8,7 @@
#include <dt-bindings/power/imx8mq-power.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/thermal/thermal.h>
#include "imx8mq-pinfunc.h"
/ {
@@ -89,6 +90,7 @@
reg = <0x0>;
enable-method = "psci";
next-level-cache = <&A53_L2>;
+ #cooling-cells = <2>;
};
A53_1: cpu@1 {
@@ -97,6 +99,7 @@
reg = <0x1>;
enable-method = "psci";
next-level-cache = <&A53_L2>;
+ #cooling-cells = <2>;
};
A53_2: cpu@2 {
@@ -105,6 +108,7 @@
reg = <0x2>;
enable-method = "psci";
next-level-cache = <&A53_L2>;
+ #cooling-cells = <2>;
};
A53_3: cpu@3 {
@@ -113,6 +117,7 @@
reg = <0x3>;
enable-method = "psci";
next-level-cache = <&A53_L2>;
+ #cooling-cells = <2>;
};
A53_L2: l2-cache0 {
@@ -210,6 +215,91 @@
#interrupt-cells = <2>;
};
+ tmu: tmu@30260000 {
+ compatible = "fsl,imx8mq-tmu";
+ reg = <0x30260000 0x10000>;
+ interrupt = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ little-endian;
+ fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>;
+ fsl,tmu-calibration = <0x00000000 0x00000023
+ 0x00000001 0x00000029
+ 0x00000002 0x0000002f
+ 0x00000003 0x00000035
+ 0x00000004 0x0000003d
+ 0x00000005 0x00000043
+ 0x00000006 0x0000004b
+ 0x00000007 0x00000051
+ 0x00000008 0x00000057
+ 0x00000009 0x0000005f
+ 0x0000000a 0x00000067
+ 0x0000000b 0x0000006f
+
+ 0x00010000 0x0000001b
+ 0x00010001 0x00000023
+ 0x00010002 0x0000002b
+ 0x00010003 0x00000033
+ 0x00010004 0x0000003b
+ 0x00010005 0x00000043
+ 0x00010006 0x0000004b
+ 0x00010007 0x00000055
+ 0x00010008 0x0000005d
+ 0x00010009 0x00000067
+ 0x0001000a 0x00000070
+
+ 0x00020000 0x00000017
+ 0x00020001 0x00000023
+ 0x00020002 0x0000002d
+ 0x00020003 0x00000037
+ 0x00020004 0x00000041
+ 0x00020005 0x0000004b
+ 0x00020006 0x00000057
+ 0x00020007 0x00000063
+ 0x00020008 0x0000006f
+
+ 0x00030000 0x00000015
+ 0x00030001 0x00000021
+ 0x00030002 0x0000002d
+ 0x00030003 0x00000039
+ 0x00030004 0x00000045
+ 0x00030005 0x00000053
+ 0x00030006 0x0000005f
+ 0x00030007 0x00000071>;
+ #thermal-sensor-cells = <1>;
+ };
+
+ thermal-zones {
+ cpu-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <2000>;
+ thermal-sensors = <&tmu 0>;
+
+ trips {
+ cpu_alert: cpu-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu_crit {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert>;
+ cooling-device =
+ <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+ };
+
wdog1: watchdog@30280000 {
compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
reg = <0x30280000 0x10000>;
--
2.17.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH] arm64: dts: fsl: imx8mq: enable the multi sensor TMU
2019-03-11 21:31 [PATCH] arm64: dts: fsl: imx8mq: enable the thermal management unit (TMU) Angus Ainslie (Purism)
2019-03-12 2:35 ` Andrey Smirnov
2019-03-18 15:48 ` [PATCH v2] " Angus Ainslie (Purism)
@ 2019-03-18 16:04 ` Angus Ainslie (Purism)
2019-03-18 16:52 ` Fabio Estevam
2019-03-18 18:46 ` [PATCH v2] " Angus Ainslie (Purism)
` (2 subsequent siblings)
5 siblings, 1 reply; 16+ messages in thread
From: Angus Ainslie (Purism) @ 2019-03-18 16:04 UTC (permalink / raw)
To: angus, andrew.smirnov
Cc: Rob Herring, Mark Rutland, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team,
Lucas Stach, Carlo Caione, Abel Vesa, Baruch Siach,
Guido Günther, devicetree, linux-arm-kernel, linux-kernel
Add the imx8mq TMU (Thermal mannagement unit) nodes for CPU,
GPU, and VPU.
This patch requires that the multi sensor patch is already applied
https://git.kernel.org/pub/scm/linux/kernel/git/evalenti/linux-soc-thermal.git/patch/?id=7797ff424818c975b59c35880dbc90fe08350204
Signed-off-by: Angus Ainslie (Purism) <angus@akkea.ca>
---
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 118 ++++++++++++++++++++++
1 file changed, 118 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index 9155bd4784eb..885395e74452 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -8,6 +8,7 @@
#include <dt-bindings/power/imx8mq-power.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/thermal/thermal.h>
#include "imx8mq-pinfunc.h"
/ {
@@ -89,6 +90,7 @@
reg = <0x0>;
enable-method = "psci";
next-level-cache = <&A53_L2>;
+ #cooling-cells = <2>;
};
A53_1: cpu@1 {
@@ -97,6 +99,7 @@
reg = <0x1>;
enable-method = "psci";
next-level-cache = <&A53_L2>;
+ #cooling-cells = <2>;
};
A53_2: cpu@2 {
@@ -105,6 +108,7 @@
reg = <0x2>;
enable-method = "psci";
next-level-cache = <&A53_L2>;
+ #cooling-cells = <2>;
};
A53_3: cpu@3 {
@@ -113,6 +117,7 @@
reg = <0x3>;
enable-method = "psci";
next-level-cache = <&A53_L2>;
+ #cooling-cells = <2>;
};
A53_L2: l2-cache0 {
@@ -210,6 +215,119 @@
#interrupt-cells = <2>;
};
+ tmu: tmu@30260000 {
+ compatible = "fsl,imx8mq-tmu";
+ reg = <0x30260000 0x10000>;
+ interrupt = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ little-endian;
+ fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>;
+ fsl,tmu-calibration = <0x00000000 0x00000023
+ 0x00000001 0x00000029
+ 0x00000002 0x0000002f
+ 0x00000003 0x00000035
+ 0x00000004 0x0000003d
+ 0x00000005 0x00000043
+ 0x00000006 0x0000004b
+ 0x00000007 0x00000051
+ 0x00000008 0x00000057
+ 0x00000009 0x0000005f
+ 0x0000000a 0x00000067
+ 0x0000000b 0x0000006f
+
+ 0x00010000 0x0000001b
+ 0x00010001 0x00000023
+ 0x00010002 0x0000002b
+ 0x00010003 0x00000033
+ 0x00010004 0x0000003b
+ 0x00010005 0x00000043
+ 0x00010006 0x0000004b
+ 0x00010007 0x00000055
+ 0x00010008 0x0000005d
+ 0x00010009 0x00000067
+ 0x0001000a 0x00000070
+
+ 0x00020000 0x00000017
+ 0x00020001 0x00000023
+ 0x00020002 0x0000002d
+ 0x00020003 0x00000037
+ 0x00020004 0x00000041
+ 0x00020005 0x0000004b
+ 0x00020006 0x00000057
+ 0x00020007 0x00000063
+ 0x00020008 0x0000006f
+
+ 0x00030000 0x00000015
+ 0x00030001 0x00000021
+ 0x00030002 0x0000002d
+ 0x00030003 0x00000039
+ 0x00030004 0x00000045
+ 0x00030005 0x00000053
+ 0x00030006 0x0000005f
+ 0x00030007 0x00000071>;
+ #thermal-sensor-cells = <1>;
+ };
+
+ thermal-zones {
+ cpu-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <2000>;
+ thermal-sensors = <&tmu 0>;
+
+ trips {
+ cpu_alert: cpu-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu_crit {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert>;
+ cooling-device =
+ <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ gpu-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <2000>;
+ thermal-sensors = <&tmu 1>;
+
+ trips {
+ cpu-crit {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+
+ vpu-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <2000>;
+ thermal-sensors = <&tmu 2>;
+
+ trips {
+ cpu-crit {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+ };
+
wdog1: watchdog@30280000 {
compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
reg = <0x30280000 0x10000>;
--
2.17.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH] arm64: dts: fsl: imx8mq: enable the multi sensor TMU
2019-03-18 16:04 ` [PATCH] arm64: dts: fsl: imx8mq: enable the multi sensor TMU Angus Ainslie (Purism)
@ 2019-03-18 16:52 ` Fabio Estevam
0 siblings, 0 replies; 16+ messages in thread
From: Fabio Estevam @ 2019-03-18 16:52 UTC (permalink / raw)
To: Angus Ainslie (Purism)
Cc: Andrey Smirnov, Rob Herring, Mark Rutland, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, NXP Linux Team,
Lucas Stach, Carlo Caione, Abel Vesa, Baruch Siach,
Guido Günther,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
linux-kernel
On Mon, Mar 18, 2019 at 1:05 PM Angus Ainslie (Purism) <angus@akkea.ca> wrote:
>
> Add the imx8mq TMU (Thermal mannagement unit) nodes for CPU,
> GPU, and VPU.
>
> This patch requires that the multi sensor patch is already applied
>
> https://git.kernel.org/pub/scm/linux/kernel/git/evalenti/linux-soc-thermal.git/patch/?id=7797ff424818c975b59c35880dbc90fe08350204
Please remove the reference to this commit. It is already present in 5.1-rc1.
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v2] arm64: dts: fsl: imx8mq: enable the multi sensor TMU
2019-03-11 21:31 [PATCH] arm64: dts: fsl: imx8mq: enable the thermal management unit (TMU) Angus Ainslie (Purism)
` (2 preceding siblings ...)
2019-03-18 16:04 ` [PATCH] arm64: dts: fsl: imx8mq: enable the multi sensor TMU Angus Ainslie (Purism)
@ 2019-03-18 18:46 ` Angus Ainslie (Purism)
2019-03-19 11:46 ` Lucas Stach
2019-03-19 15:10 ` [PATCH v3] " Angus Ainslie (Purism)
2019-03-21 12:52 ` [PATCH v4] " Angus Ainslie (Purism)
5 siblings, 1 reply; 16+ messages in thread
From: Angus Ainslie (Purism) @ 2019-03-18 18:46 UTC (permalink / raw)
To: andrew.smirnov
Cc: Rob Herring, Mark Rutland, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team,
Lucas Stach, Carlo Caione, Abel Vesa, Angus Ainslie (Purism),
Baruch Siach, Guido Günther, devicetree, linux-arm-kernel,
linux-kernel
Add the imx8mq TMU (Thermal mannagement unit) nodes for CPU,
GPU, and VPU.
Changes since v1:
Removed references to multi sensor patch.
Signed-off-by: Angus Ainslie (Purism) <angus@akkea.ca>
---
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 118 ++++++++++++++++++++++
1 file changed, 118 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index 9155bd4784eb..885395e74452 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -8,6 +8,7 @@
#include <dt-bindings/power/imx8mq-power.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/thermal/thermal.h>
#include "imx8mq-pinfunc.h"
/ {
@@ -89,6 +90,7 @@
reg = <0x0>;
enable-method = "psci";
next-level-cache = <&A53_L2>;
+ #cooling-cells = <2>;
};
A53_1: cpu@1 {
@@ -97,6 +99,7 @@
reg = <0x1>;
enable-method = "psci";
next-level-cache = <&A53_L2>;
+ #cooling-cells = <2>;
};
A53_2: cpu@2 {
@@ -105,6 +108,7 @@
reg = <0x2>;
enable-method = "psci";
next-level-cache = <&A53_L2>;
+ #cooling-cells = <2>;
};
A53_3: cpu@3 {
@@ -113,6 +117,7 @@
reg = <0x3>;
enable-method = "psci";
next-level-cache = <&A53_L2>;
+ #cooling-cells = <2>;
};
A53_L2: l2-cache0 {
@@ -210,6 +215,119 @@
#interrupt-cells = <2>;
};
+ tmu: tmu@30260000 {
+ compatible = "fsl,imx8mq-tmu";
+ reg = <0x30260000 0x10000>;
+ interrupt = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ little-endian;
+ fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>;
+ fsl,tmu-calibration = <0x00000000 0x00000023
+ 0x00000001 0x00000029
+ 0x00000002 0x0000002f
+ 0x00000003 0x00000035
+ 0x00000004 0x0000003d
+ 0x00000005 0x00000043
+ 0x00000006 0x0000004b
+ 0x00000007 0x00000051
+ 0x00000008 0x00000057
+ 0x00000009 0x0000005f
+ 0x0000000a 0x00000067
+ 0x0000000b 0x0000006f
+
+ 0x00010000 0x0000001b
+ 0x00010001 0x00000023
+ 0x00010002 0x0000002b
+ 0x00010003 0x00000033
+ 0x00010004 0x0000003b
+ 0x00010005 0x00000043
+ 0x00010006 0x0000004b
+ 0x00010007 0x00000055
+ 0x00010008 0x0000005d
+ 0x00010009 0x00000067
+ 0x0001000a 0x00000070
+
+ 0x00020000 0x00000017
+ 0x00020001 0x00000023
+ 0x00020002 0x0000002d
+ 0x00020003 0x00000037
+ 0x00020004 0x00000041
+ 0x00020005 0x0000004b
+ 0x00020006 0x00000057
+ 0x00020007 0x00000063
+ 0x00020008 0x0000006f
+
+ 0x00030000 0x00000015
+ 0x00030001 0x00000021
+ 0x00030002 0x0000002d
+ 0x00030003 0x00000039
+ 0x00030004 0x00000045
+ 0x00030005 0x00000053
+ 0x00030006 0x0000005f
+ 0x00030007 0x00000071>;
+ #thermal-sensor-cells = <1>;
+ };
+
+ thermal-zones {
+ cpu-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <2000>;
+ thermal-sensors = <&tmu 0>;
+
+ trips {
+ cpu_alert: cpu-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu_crit {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert>;
+ cooling-device =
+ <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ gpu-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <2000>;
+ thermal-sensors = <&tmu 1>;
+
+ trips {
+ cpu-crit {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+
+ vpu-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <2000>;
+ thermal-sensors = <&tmu 2>;
+
+ trips {
+ cpu-crit {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+ };
+
wdog1: watchdog@30280000 {
compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
reg = <0x30280000 0x10000>;
--
2.17.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH v2] arm64: dts: fsl: imx8mq: enable the multi sensor TMU
2019-03-18 18:46 ` [PATCH v2] " Angus Ainslie (Purism)
@ 2019-03-19 11:46 ` Lucas Stach
0 siblings, 0 replies; 16+ messages in thread
From: Lucas Stach @ 2019-03-19 11:46 UTC (permalink / raw)
To: Angus Ainslie (Purism), andrew.smirnov
Cc: Rob Herring, Mark Rutland, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team,
Carlo Caione, Abel Vesa, Baruch Siach, Guido Günther,
devicetree, linux-arm-kernel, linux-kernel
Hi Angus,
Am Montag, den 18.03.2019, 11:46 -0700 schrieb Angus Ainslie (Purism):
> Add the imx8mq TMU (Thermal mannagement unit) nodes for CPU,
> GPU, and VPU.
>
> Changes since v1:
>
> Removed references to multi sensor patch.
>
> Signed-off-by: Angus Ainslie (Purism) <angus@akkea.ca>
> ---
> arch/arm64/boot/dts/freescale/imx8mq.dtsi | 118 ++++++++++++++++++++++
> 1 file changed, 118 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> index 9155bd4784eb..885395e74452 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
[...]
> + thermal-zones {
> + cpu-thermal {
> + polling-delay-passive = <250>;
> + polling-delay = <2000>;
> + thermal-sensors = <&tmu 0>;
> +
> + trips {
> + cpu_alert: cpu-alert {
> + temperature = <85000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> +
> + cpu_crit {
> + temperature = <95000>;
All the critical trip points seem to be too high. The consumer parts
have a maximum junction temperature of 95°C, so the common DT
configuration used by all boards should have a crit trip point at least
a few degrees below this value. Boards that only use the industrial
parts can always overwrite the trip points if the designer wishes to do
so.
> + hysteresis = <2000>;
> + type = "critical";
> + };
> + };
> +
> + cooling-maps {
> + map0 {
> + trip = <&cpu_alert>;
> + cooling-device =
> + <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> + };
> + };
> + };
> +
> + gpu-thermal {
> + polling-delay-passive = <250>;
> + polling-delay = <2000>;
> + thermal-sensors = <&tmu 1>;
> +
> + trips {
> + cpu-crit {
Should be gpu-crit.
> + temperature = <95000>;
> + hysteresis = <2000>;
> + type = "critical";
> + };
> + };
> + };
> +
> + vpu-thermal {
> + polling-delay-passive = <250>;
> + polling-delay = <2000>;
> + thermal-sensors = <&tmu 2>;
> +
> + trips {
> + cpu-crit {
Should be vpu-crit.
Regards,
Lucas
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v3] arm64: dts: fsl: imx8mq: enable the multi sensor TMU
2019-03-11 21:31 [PATCH] arm64: dts: fsl: imx8mq: enable the thermal management unit (TMU) Angus Ainslie (Purism)
` (3 preceding siblings ...)
2019-03-18 18:46 ` [PATCH v2] " Angus Ainslie (Purism)
@ 2019-03-19 15:10 ` Angus Ainslie (Purism)
2019-03-19 16:18 ` Fabio Estevam
2019-03-21 12:52 ` [PATCH v4] " Angus Ainslie (Purism)
5 siblings, 1 reply; 16+ messages in thread
From: Angus Ainslie (Purism) @ 2019-03-19 15:10 UTC (permalink / raw)
To: andrew.smirnov, Lucas Stach
Cc: Rob Herring, Mark Rutland, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team,
Carlo Caione, Abel Vesa, Baruch Siach, Guido Günther,
Angus Ainslie (Purism),
devicetree, linux-arm-kernel, linux-kernel
Add the imx8mq TMU (Thermal management unit) nodes for CPU,
GPU, and VPU.
Changes since v2:
Updated alert and critical temps for commercial parts.
Fixed node names.
Changes since v1:
Removed references to multi sensor patch.
Signed-off-by: Angus Ainslie (Purism) <angus@akkea.ca>
---
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 118 ++++++++++++++++++++++
1 file changed, 118 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index 9155bd4784eb..83c0187e1524 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -8,6 +8,7 @@
#include <dt-bindings/power/imx8mq-power.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/thermal/thermal.h>
#include "imx8mq-pinfunc.h"
/ {
@@ -89,6 +90,7 @@
reg = <0x0>;
enable-method = "psci";
next-level-cache = <&A53_L2>;
+ #cooling-cells = <2>;
};
A53_1: cpu@1 {
@@ -97,6 +99,7 @@
reg = <0x1>;
enable-method = "psci";
next-level-cache = <&A53_L2>;
+ #cooling-cells = <2>;
};
A53_2: cpu@2 {
@@ -105,6 +108,7 @@
reg = <0x2>;
enable-method = "psci";
next-level-cache = <&A53_L2>;
+ #cooling-cells = <2>;
};
A53_3: cpu@3 {
@@ -113,6 +117,7 @@
reg = <0x3>;
enable-method = "psci";
next-level-cache = <&A53_L2>;
+ #cooling-cells = <2>;
};
A53_L2: l2-cache0 {
@@ -210,6 +215,119 @@
#interrupt-cells = <2>;
};
+ tmu: tmu@30260000 {
+ compatible = "fsl,imx8mq-tmu";
+ reg = <0x30260000 0x10000>;
+ interrupt = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ little-endian;
+ fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>;
+ fsl,tmu-calibration = <0x00000000 0x00000023
+ 0x00000001 0x00000029
+ 0x00000002 0x0000002f
+ 0x00000003 0x00000035
+ 0x00000004 0x0000003d
+ 0x00000005 0x00000043
+ 0x00000006 0x0000004b
+ 0x00000007 0x00000051
+ 0x00000008 0x00000057
+ 0x00000009 0x0000005f
+ 0x0000000a 0x00000067
+ 0x0000000b 0x0000006f
+
+ 0x00010000 0x0000001b
+ 0x00010001 0x00000023
+ 0x00010002 0x0000002b
+ 0x00010003 0x00000033
+ 0x00010004 0x0000003b
+ 0x00010005 0x00000043
+ 0x00010006 0x0000004b
+ 0x00010007 0x00000055
+ 0x00010008 0x0000005d
+ 0x00010009 0x00000067
+ 0x0001000a 0x00000070
+
+ 0x00020000 0x00000017
+ 0x00020001 0x00000023
+ 0x00020002 0x0000002d
+ 0x00020003 0x00000037
+ 0x00020004 0x00000041
+ 0x00020005 0x0000004b
+ 0x00020006 0x00000057
+ 0x00020007 0x00000063
+ 0x00020008 0x0000006f
+
+ 0x00030000 0x00000015
+ 0x00030001 0x00000021
+ 0x00030002 0x0000002d
+ 0x00030003 0x00000039
+ 0x00030004 0x00000045
+ 0x00030005 0x00000053
+ 0x00030006 0x0000005f
+ 0x00030007 0x00000071>;
+ #thermal-sensor-cells = <1>;
+ };
+
+ thermal-zones {
+ cpu-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <2000>;
+ thermal-sensors = <&tmu 0>;
+
+ trips {
+ cpu_alert: cpu-alert {
+ temperature = <80000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu-crit {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert>;
+ cooling-device =
+ <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ gpu-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <2000>;
+ thermal-sensors = <&tmu 1>;
+
+ trips {
+ gpu-crit {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+
+ vpu-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <2000>;
+ thermal-sensors = <&tmu 2>;
+
+ trips {
+ vpu-crit {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+ };
+
wdog1: watchdog@30280000 {
compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
reg = <0x30280000 0x10000>;
--
2.17.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH v3] arm64: dts: fsl: imx8mq: enable the multi sensor TMU
2019-03-19 15:10 ` [PATCH v3] " Angus Ainslie (Purism)
@ 2019-03-19 16:18 ` Fabio Estevam
0 siblings, 0 replies; 16+ messages in thread
From: Fabio Estevam @ 2019-03-19 16:18 UTC (permalink / raw)
To: Angus Ainslie (Purism)
Cc: Andrey Smirnov, Lucas Stach, Rob Herring, Mark Rutland,
Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, NXP Linux Team,
Carlo Caione, Abel Vesa, Baruch Siach, Guido Günther,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
linux-kernel
On Tue, Mar 19, 2019 at 12:10 PM Angus Ainslie (Purism) <angus@akkea.ca> wrote:
>
> Add the imx8mq TMU (Thermal management unit) nodes for CPU,
> GPU, and VPU.
>
> Changes since v2:
>
> Updated alert and critical temps for commercial parts.
> Fixed node names.
>
> Changes since v1:
>
> Removed references to multi sensor patch.
Please put the change history below the --- line, so that it does not
appear in the commit log text.
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v4] arm64: dts: fsl: imx8mq: enable the multi sensor TMU
2019-03-11 21:31 [PATCH] arm64: dts: fsl: imx8mq: enable the thermal management unit (TMU) Angus Ainslie (Purism)
` (4 preceding siblings ...)
2019-03-19 15:10 ` [PATCH v3] " Angus Ainslie (Purism)
@ 2019-03-21 12:52 ` Angus Ainslie (Purism)
2019-03-21 14:48 ` Lucas Stach
2019-03-22 2:11 ` Shawn Guo
5 siblings, 2 replies; 16+ messages in thread
From: Angus Ainslie (Purism) @ 2019-03-21 12:52 UTC (permalink / raw)
To: Fabio Estevam
Cc: Rob Herring, Mark Rutland, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, NXP Linux Team, Lucas Stach,
Carlo Caione, Abel Vesa, Daniel Baluta, Angus Ainslie (Purism),
Guido Günther, devicetree, linux-arm-kernel, linux-kernel
Add the imx8mq TMU (Thermal management unit) nodes for CPU,
GPU, and VPU.
Signed-off-by: Angus Ainslie (Purism) <angus@akkea.ca>
---
Changes since v3:
Moved the annotation.
Changes since v2:
Updated alert and critical temps for commercial parts.
Fixed node names.
Changes since v1:
Removed references to multi sensor patch.
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 118 ++++++++++++++++++++++
1 file changed, 118 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index b39c6c75c043..81d5ce1b1ec1 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -8,6 +8,7 @@
#include <dt-bindings/power/imx8mq-power.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/thermal/thermal.h>
#include "imx8mq-pinfunc.h"
/ {
@@ -89,6 +90,7 @@
reg = <0x0>;
enable-method = "psci";
next-level-cache = <&A53_L2>;
+ #cooling-cells = <2>;
};
A53_1: cpu@1 {
@@ -97,6 +99,7 @@
reg = <0x1>;
enable-method = "psci";
next-level-cache = <&A53_L2>;
+ #cooling-cells = <2>;
};
A53_2: cpu@2 {
@@ -105,6 +108,7 @@
reg = <0x2>;
enable-method = "psci";
next-level-cache = <&A53_L2>;
+ #cooling-cells = <2>;
};
A53_3: cpu@3 {
@@ -113,6 +117,7 @@
reg = <0x3>;
enable-method = "psci";
next-level-cache = <&A53_L2>;
+ #cooling-cells = <2>;
};
A53_L2: l2-cache0 {
@@ -210,6 +215,119 @@
#interrupt-cells = <2>;
};
+ tmu: tmu@30260000 {
+ compatible = "fsl,imx8mq-tmu";
+ reg = <0x30260000 0x10000>;
+ interrupt = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ little-endian;
+ fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>;
+ fsl,tmu-calibration = <0x00000000 0x00000023
+ 0x00000001 0x00000029
+ 0x00000002 0x0000002f
+ 0x00000003 0x00000035
+ 0x00000004 0x0000003d
+ 0x00000005 0x00000043
+ 0x00000006 0x0000004b
+ 0x00000007 0x00000051
+ 0x00000008 0x00000057
+ 0x00000009 0x0000005f
+ 0x0000000a 0x00000067
+ 0x0000000b 0x0000006f
+
+ 0x00010000 0x0000001b
+ 0x00010001 0x00000023
+ 0x00010002 0x0000002b
+ 0x00010003 0x00000033
+ 0x00010004 0x0000003b
+ 0x00010005 0x00000043
+ 0x00010006 0x0000004b
+ 0x00010007 0x00000055
+ 0x00010008 0x0000005d
+ 0x00010009 0x00000067
+ 0x0001000a 0x00000070
+
+ 0x00020000 0x00000017
+ 0x00020001 0x00000023
+ 0x00020002 0x0000002d
+ 0x00020003 0x00000037
+ 0x00020004 0x00000041
+ 0x00020005 0x0000004b
+ 0x00020006 0x00000057
+ 0x00020007 0x00000063
+ 0x00020008 0x0000006f
+
+ 0x00030000 0x00000015
+ 0x00030001 0x00000021
+ 0x00030002 0x0000002d
+ 0x00030003 0x00000039
+ 0x00030004 0x00000045
+ 0x00030005 0x00000053
+ 0x00030006 0x0000005f
+ 0x00030007 0x00000071>;
+ #thermal-sensor-cells = <1>;
+ };
+
+ thermal-zones {
+ cpu-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <2000>;
+ thermal-sensors = <&tmu 0>;
+
+ trips {
+ cpu_alert: cpu-alert {
+ temperature = <80000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu-crit {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert>;
+ cooling-device =
+ <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ gpu-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <2000>;
+ thermal-sensors = <&tmu 1>;
+
+ trips {
+ gpu-crit {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+
+ vpu-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <2000>;
+ thermal-sensors = <&tmu 2>;
+
+ trips {
+ vpu-crit {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+ };
+
wdog1: watchdog@30280000 {
compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
reg = <0x30280000 0x10000>;
--
2.17.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH v4] arm64: dts: fsl: imx8mq: enable the multi sensor TMU
2019-03-21 12:52 ` [PATCH v4] " Angus Ainslie (Purism)
@ 2019-03-21 14:48 ` Lucas Stach
2019-03-22 2:11 ` Shawn Guo
1 sibling, 0 replies; 16+ messages in thread
From: Lucas Stach @ 2019-03-21 14:48 UTC (permalink / raw)
To: Angus Ainslie (Purism), Fabio Estevam
Cc: Rob Herring, Mark Rutland, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, NXP Linux Team, Carlo Caione, Abel Vesa,
Daniel Baluta, Guido Günther, devicetree, linux-arm-kernel,
linux-kernel
Am Donnerstag, den 21.03.2019, 05:52 -0700 schrieb Angus Ainslie (Purism):
> Add the imx8mq TMU (Thermal management unit) nodes for CPU,
> GPU, and VPU.
>
> Signed-off-by: Angus Ainslie (Purism) <angus@akkea.ca>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
> ---
>
> Changes since v3:
>
> Moved the annotation.
>
> Changes since v2:
>
> Updated alert and critical temps for commercial parts.
> Fixed node names.
>
> Changes since v1:
>
> Removed references to multi sensor patch.
>
> arch/arm64/boot/dts/freescale/imx8mq.dtsi | 118 ++++++++++++++++++++++
> 1 file changed, 118 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> index b39c6c75c043..81d5ce1b1ec1 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> @@ -8,6 +8,7 @@
> #include <dt-bindings/power/imx8mq-power.h>
> #include <dt-bindings/gpio/gpio.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/thermal/thermal.h>
> #include "imx8mq-pinfunc.h"
>
> / {
> @@ -89,6 +90,7 @@
> > reg = <0x0>;
> > enable-method = "psci";
> > next-level-cache = <&A53_L2>;
> > + #cooling-cells = <2>;
> > };
>
> > > A53_1: cpu@1 {
> @@ -97,6 +99,7 @@
> > reg = <0x1>;
> > enable-method = "psci";
> > next-level-cache = <&A53_L2>;
> > + #cooling-cells = <2>;
> > };
>
> > > A53_2: cpu@2 {
> @@ -105,6 +108,7 @@
> > reg = <0x2>;
> > enable-method = "psci";
> > next-level-cache = <&A53_L2>;
> > + #cooling-cells = <2>;
> > };
>
> > > A53_3: cpu@3 {
> @@ -113,6 +117,7 @@
> > reg = <0x3>;
> > enable-method = "psci";
> > next-level-cache = <&A53_L2>;
> > + #cooling-cells = <2>;
> > };
>
> > A53_L2: l2-cache0 {
> @@ -210,6 +215,119 @@
> > #interrupt-cells = <2>;
> > };
>
> > > + tmu: tmu@30260000 {
> > + compatible = "fsl,imx8mq-tmu";
> > + reg = <0x30260000 0x10000>;
> > + interrupt = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
> > + little-endian;
> > + fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>;
> > + fsl,tmu-calibration = <0x00000000 0x00000023
> > + 0x00000001 0x00000029
> > + 0x00000002 0x0000002f
> > + 0x00000003 0x00000035
> > + 0x00000004 0x0000003d
> > + 0x00000005 0x00000043
> > + 0x00000006 0x0000004b
> > + 0x00000007 0x00000051
> > + 0x00000008 0x00000057
> > + 0x00000009 0x0000005f
> > + 0x0000000a 0x00000067
> > + 0x0000000b 0x0000006f
> +
> > + 0x00010000 0x0000001b
> > + 0x00010001 0x00000023
> > + 0x00010002 0x0000002b
> > + 0x00010003 0x00000033
> > + 0x00010004 0x0000003b
> > + 0x00010005 0x00000043
> > + 0x00010006 0x0000004b
> > + 0x00010007 0x00000055
> > + 0x00010008 0x0000005d
> > + 0x00010009 0x00000067
> > + 0x0001000a 0x00000070
> +
> > + 0x00020000 0x00000017
> > + 0x00020001 0x00000023
> > + 0x00020002 0x0000002d
> > + 0x00020003 0x00000037
> > + 0x00020004 0x00000041
> > + 0x00020005 0x0000004b
> > + 0x00020006 0x00000057
> > + 0x00020007 0x00000063
> > + 0x00020008 0x0000006f
> +
> > + 0x00030000 0x00000015
> > + 0x00030001 0x00000021
> > + 0x00030002 0x0000002d
> > + 0x00030003 0x00000039
> > + 0x00030004 0x00000045
> > + 0x00030005 0x00000053
> > + 0x00030006 0x0000005f
> > + 0x00030007 0x00000071>;
> > + #thermal-sensor-cells = <1>;
> > + };
> +
> > + thermal-zones {
> > + cpu-thermal {
> > + polling-delay-passive = <250>;
> > + polling-delay = <2000>;
> > + thermal-sensors = <&tmu 0>;
> +
> > + trips {
> > + cpu_alert: cpu-alert {
> > + temperature = <80000>;
> > + hysteresis = <2000>;
> > + type = "passive";
> > + };
> +
> > + cpu-crit {
> > + temperature = <90000>;
> > + hysteresis = <2000>;
> > + type = "critical";
> > + };
> > + };
> +
> > + cooling-maps {
> > + map0 {
> > + trip = <&cpu_alert>;
> > + cooling-device =
> > + <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> > + <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> > + <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> > + <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> > + };
> > + };
> > + };
> +
> > + gpu-thermal {
> > + polling-delay-passive = <250>;
> > + polling-delay = <2000>;
> > + thermal-sensors = <&tmu 1>;
> +
> > + trips {
> > + gpu-crit {
> > + temperature = <90000>;
> > + hysteresis = <2000>;
> > + type = "critical";
> > + };
> > + };
> > + };
> +
> > + vpu-thermal {
> > + polling-delay-passive = <250>;
> > + polling-delay = <2000>;
> > + thermal-sensors = <&tmu 2>;
> +
> > + trips {
> > + vpu-crit {
> > + temperature = <90000>;
> > + hysteresis = <2000>;
> > + type = "critical";
> > + };
> > + };
> > + };
> > + };
> +
> > > wdog1: watchdog@30280000 {
> > compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
> > reg = <0x30280000 0x10000>;
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v4] arm64: dts: fsl: imx8mq: enable the multi sensor TMU
2019-03-21 12:52 ` [PATCH v4] " Angus Ainslie (Purism)
2019-03-21 14:48 ` Lucas Stach
@ 2019-03-22 2:11 ` Shawn Guo
1 sibling, 0 replies; 16+ messages in thread
From: Shawn Guo @ 2019-03-22 2:11 UTC (permalink / raw)
To: Angus Ainslie (Purism)
Cc: Fabio Estevam, Rob Herring, Mark Rutland, Sascha Hauer,
Pengutronix Kernel Team, NXP Linux Team, Lucas Stach,
Carlo Caione, Abel Vesa, Daniel Baluta, Guido Günther,
devicetree, linux-arm-kernel, linux-kernel
On Thu, Mar 21, 2019 at 05:52:52AM -0700, Angus Ainslie (Purism) wrote:
> Add the imx8mq TMU (Thermal management unit) nodes for CPU,
> GPU, and VPU.
>
> Signed-off-by: Angus Ainslie (Purism) <angus@akkea.ca>
Subject prefix 'arm64: dts: imx8mq:' would be good enough. I changed it
and applied patch.
Shawn
> ---
>
> Changes since v3:
>
> Moved the annotation.
>
> Changes since v2:
>
> Updated alert and critical temps for commercial parts.
> Fixed node names.
>
> Changes since v1:
>
> Removed references to multi sensor patch.
>
> arch/arm64/boot/dts/freescale/imx8mq.dtsi | 118 ++++++++++++++++++++++
> 1 file changed, 118 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> index b39c6c75c043..81d5ce1b1ec1 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> @@ -8,6 +8,7 @@
> #include <dt-bindings/power/imx8mq-power.h>
> #include <dt-bindings/gpio/gpio.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/thermal/thermal.h>
> #include "imx8mq-pinfunc.h"
>
> / {
> @@ -89,6 +90,7 @@
> reg = <0x0>;
> enable-method = "psci";
> next-level-cache = <&A53_L2>;
> + #cooling-cells = <2>;
> };
>
> A53_1: cpu@1 {
> @@ -97,6 +99,7 @@
> reg = <0x1>;
> enable-method = "psci";
> next-level-cache = <&A53_L2>;
> + #cooling-cells = <2>;
> };
>
> A53_2: cpu@2 {
> @@ -105,6 +108,7 @@
> reg = <0x2>;
> enable-method = "psci";
> next-level-cache = <&A53_L2>;
> + #cooling-cells = <2>;
> };
>
> A53_3: cpu@3 {
> @@ -113,6 +117,7 @@
> reg = <0x3>;
> enable-method = "psci";
> next-level-cache = <&A53_L2>;
> + #cooling-cells = <2>;
> };
>
> A53_L2: l2-cache0 {
> @@ -210,6 +215,119 @@
> #interrupt-cells = <2>;
> };
>
> + tmu: tmu@30260000 {
> + compatible = "fsl,imx8mq-tmu";
> + reg = <0x30260000 0x10000>;
> + interrupt = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
> + little-endian;
> + fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>;
> + fsl,tmu-calibration = <0x00000000 0x00000023
> + 0x00000001 0x00000029
> + 0x00000002 0x0000002f
> + 0x00000003 0x00000035
> + 0x00000004 0x0000003d
> + 0x00000005 0x00000043
> + 0x00000006 0x0000004b
> + 0x00000007 0x00000051
> + 0x00000008 0x00000057
> + 0x00000009 0x0000005f
> + 0x0000000a 0x00000067
> + 0x0000000b 0x0000006f
> +
> + 0x00010000 0x0000001b
> + 0x00010001 0x00000023
> + 0x00010002 0x0000002b
> + 0x00010003 0x00000033
> + 0x00010004 0x0000003b
> + 0x00010005 0x00000043
> + 0x00010006 0x0000004b
> + 0x00010007 0x00000055
> + 0x00010008 0x0000005d
> + 0x00010009 0x00000067
> + 0x0001000a 0x00000070
> +
> + 0x00020000 0x00000017
> + 0x00020001 0x00000023
> + 0x00020002 0x0000002d
> + 0x00020003 0x00000037
> + 0x00020004 0x00000041
> + 0x00020005 0x0000004b
> + 0x00020006 0x00000057
> + 0x00020007 0x00000063
> + 0x00020008 0x0000006f
> +
> + 0x00030000 0x00000015
> + 0x00030001 0x00000021
> + 0x00030002 0x0000002d
> + 0x00030003 0x00000039
> + 0x00030004 0x00000045
> + 0x00030005 0x00000053
> + 0x00030006 0x0000005f
> + 0x00030007 0x00000071>;
> + #thermal-sensor-cells = <1>;
> + };
> +
> + thermal-zones {
> + cpu-thermal {
> + polling-delay-passive = <250>;
> + polling-delay = <2000>;
> + thermal-sensors = <&tmu 0>;
> +
> + trips {
> + cpu_alert: cpu-alert {
> + temperature = <80000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> +
> + cpu-crit {
> + temperature = <90000>;
> + hysteresis = <2000>;
> + type = "critical";
> + };
> + };
> +
> + cooling-maps {
> + map0 {
> + trip = <&cpu_alert>;
> + cooling-device =
> + <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> + };
> + };
> + };
> +
> + gpu-thermal {
> + polling-delay-passive = <250>;
> + polling-delay = <2000>;
> + thermal-sensors = <&tmu 1>;
> +
> + trips {
> + gpu-crit {
> + temperature = <90000>;
> + hysteresis = <2000>;
> + type = "critical";
> + };
> + };
> + };
> +
> + vpu-thermal {
> + polling-delay-passive = <250>;
> + polling-delay = <2000>;
> + thermal-sensors = <&tmu 2>;
> +
> + trips {
> + vpu-crit {
> + temperature = <90000>;
> + hysteresis = <2000>;
> + type = "critical";
> + };
> + };
> + };
> + };
> +
> wdog1: watchdog@30280000 {
> compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
> reg = <0x30280000 0x10000>;
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2019-03-22 2:11 UTC | newest]
Thread overview: 16+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-03-11 21:31 [PATCH] arm64: dts: fsl: imx8mq: enable the thermal management unit (TMU) Angus Ainslie (Purism)
2019-03-12 2:35 ` Andrey Smirnov
2019-03-12 12:54 ` Angus Ainslie
2019-03-12 20:18 ` Angus Ainslie
2019-03-12 20:32 ` Fabio Estevam
2019-03-13 0:31 ` Andrey Smirnov
2019-03-18 15:48 ` [PATCH v2] " Angus Ainslie (Purism)
2019-03-18 16:04 ` [PATCH] arm64: dts: fsl: imx8mq: enable the multi sensor TMU Angus Ainslie (Purism)
2019-03-18 16:52 ` Fabio Estevam
2019-03-18 18:46 ` [PATCH v2] " Angus Ainslie (Purism)
2019-03-19 11:46 ` Lucas Stach
2019-03-19 15:10 ` [PATCH v3] " Angus Ainslie (Purism)
2019-03-19 16:18 ` Fabio Estevam
2019-03-21 12:52 ` [PATCH v4] " Angus Ainslie (Purism)
2019-03-21 14:48 ` Lucas Stach
2019-03-22 2:11 ` Shawn Guo
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