From: Michal Suchanek <hramrach@gmail.com>
To: Mark Brown <broonie@kernel.org>
Cc: "Emilio López" <emilio@elopez.com.ar>,
linux-sunxi <linux-sunxi@googlegroups.com>,
"Rob Herring" <robh+dt@kernel.org>,
"Pawel Moll" <pawel.moll@arm.com>,
"Mark Rutland" <mark.rutland@arm.com>,
"Ian Campbell" <ijc+devicetree@hellion.org.uk>,
"Kumar Gala" <galak@codeaurora.org>,
"Russell King" <linux@arm.linux.org.uk>,
"Maxime Ripard" <maxime.ripard@free-electrons.com>,
devicetree <devicetree@vger.kernel.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"Linux Kernel Mailing List" <linux-kernel@vger.kernel.org>,
linux-spi <linux-spi@vger.kernel.org>,
"Priit Laes" <plaes@plaes.org>
Subject: Re: [linux-sunxi] Re: [PATCH 4/9] spi: sun4i: add DMA support
Date: Tue, 17 May 2016 07:44:36 +0200 [thread overview]
Message-ID: <CAOMqctQPUDm3XDf_YAVubzq2op=j6Qs6R4hjjCaa=ELoeHzjhQ@mail.gmail.com> (raw)
In-Reply-To: <20150820185850.GQ12027@sirena.org.uk>
On 20 August 2015 at 16:56, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
>> + /* Enable Dedicated DMA requests */
>> + reg = sun4i_spi_read(sspi, SUN4I_CTL_REG);
>> + reg |= SUN4I_CTL_DMAMC_DEDICATED;
>> + sun4i_spi_write(sspi, SUN4I_CTL_REG, reg);
>> + sun4i_spi_write(sspi, SUN4I_DMA_CTL_REG, trigger);
>> + } else {
>> + dev_dbg(&sspi->master->dev, "Using PIO mode for transfer\n");
>> +
>> + /* Disable DMA requests */
>> + reg = sun4i_spi_read(sspi, SUN4I_CTL_REG);
>> + sun4i_spi_write(sspi, SUN4I_CTL_REG,
>> + reg & ~SUN4I_CTL_DMAMC_DEDICATED);
>> + sun4i_spi_write(sspi, SUN4I_DMA_CTL_REG, 0);
>> +
>> + /* Fill the TX FIFO */
>> + /* Filling the fifo fully causes timeout for some reason
>> + * at least on spi2 on a10s */
>> + sun4i_spi_fill_fifo(sspi, SUN4I_FIFO_DEPTH - 1);
>> + }
>> +
>> /* Start the transfer */
>> reg = sun4i_spi_read(sspi, SUN4I_CTL_REG);
>> sun4i_spi_write(sspi, SUN4I_CTL_REG, reg | SUN4I_CTL_XCH);
>> @@ -303,7 +363,12 @@ static int sun4i_spi_transfer_one(struct spi_master *master,
>> goto out;
>> }
>>
>> - sun4i_spi_drain_fifo(sspi, SUN4I_FIFO_DEPTH);
>> + if (sun4i_spi_can_dma(master, spi, tfr) && desc_rx) {
>> + /* The receive transfer should be the last one to finish */
>> + dma_wait_for_async_tx(desc_rx);
>
> Nope, this is only meant for async_tx. You should register a callback
> in your transfer that will mark the completion structure as completed,
> and then drain the FIFO only if not using DMA.
What exactly is wrong with this?
I did not observe data corruption. Passing desc_rx to
dma_wait_for_async_tx looks odd on closer inspection, though. Will
look through some other spi driver code.
>> - init_completion(&sspi->done);
>> + master->dma_tx = dma_request_slave_channel_reason(&pdev->dev, "tx");
>> + if (IS_ERR(master->dma_tx)) {
>> + dev_err(&pdev->dev, "Unable to acquire DMA channel TX\n");
>> + ret = PTR_ERR(master->dma_tx);
>> + goto err_free_master;
>> + }
>> +
>> + dma_sconfig.direction = DMA_MEM_TO_DEV;
>> + dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
>> + dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
>> + dma_sconfig.dst_addr = res->start + SUN4I_TXDATA_REG;
>> + dma_sconfig.src_maxburst = 1;
>> + dma_sconfig.dst_maxburst = 1;
>> +
>> + ret = dmaengine_slave_config(master->dma_tx, &dma_sconfig);
>> + if (ret) {
>> + dev_err(&pdev->dev, "Unable to configure TX DMA slave\n");
>> + goto err_tx_dma_release;
>> + }
>> +
>> + master->dma_rx = dma_request_slave_channel_reason(&pdev->dev, "rx");
>> + if (IS_ERR(master->dma_rx)) {
>> + dev_err(&pdev->dev, "Unable to acquire DMA channel RX\n");
>> + ret = PTR_ERR(master->dma_rx);
>> + goto err_tx_dma_release;
>> + }
>> +
>> + dma_sconfig.direction = DMA_DEV_TO_MEM;
>> + dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
>> + dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
>> + dma_sconfig.src_addr = res->start + SUN4I_RXDATA_REG;
>> + dma_sconfig.src_maxburst = 1;
>> + dma_sconfig.dst_maxburst = 1;
>
> We can't use a higher bust size?
Who actually does?
It accomplishes the transfer with burst size of 1 so that's good enough.
Researching alignment requirements and other oddities of Chinese
controllers when larger burst size is used can be topic for another
patch.
On 20 August 2015 at 20:58, Mark Brown <broonie@kernel.org> wrote:
> On Thu, Aug 20, 2015 at 02:19:46PM -0000, Emilio López wrote:
>
>> - sun4i_spi_drain_fifo(sspi, SUN4I_FIFO_DEPTH);
>> + if (sun4i_spi_can_dma(master, spi, tfr) && desc_rx) {
>> + /* The receive transfer should be the last one to finish */
>> + dma_wait_for_async_tx(desc_rx);
>
> What if it's a transmit only transfer? We'll fall over to this...
>
>> + } else {
>> + sun4i_spi_drain_fifo(sspi, SUN4I_FIFO_DEPTH);
>> + }
>
> ...which manually reads data from the FIFO which doesn't seem like what
... which should be empty since RX is not enabled.
> we want, won't it conflict with the DMA?
It does not seem to conflict in practice.
Thanks
Michal
next prev parent reply other threads:[~2016-05-17 5:45 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <cover.1440080122.git.hramrach@gmail.com>
[not found] ` <0e0b52774a48ddb71dc8095b66942451cd31ff7d.1440080122.git.hramrach@gmail.com>
2015-08-20 14:43 ` [PATCH 1/9] spi: sunxi: fix transfer timeout Maxime Ripard
2015-08-20 18:41 ` Mark Brown
2015-08-20 19:34 ` Maxime Ripard
2015-08-20 21:08 ` Mark Brown
2015-08-20 21:18 ` Maxime Ripard
2015-08-20 21:29 ` Mark Brown
[not found] ` <a40fbf7ca8bd36f08f5e9d3fb6f6de2454066af7.1440080122.git.hramrach@gmail.com>
2015-08-20 14:45 ` [PATCH 2/9] spi: sun4i: fix FIFO limit Maxime Ripard
[not found] ` <ccf776869b0d7fe2c78bcc41d6cd1896bf732296.1440080122.git.hramrach@gmail.com>
2015-08-20 14:24 ` [linux-sunxi] [PATCH 4/9] spi: sun4i: add DMA support Michal Suchanek
2015-08-20 14:56 ` Maxime Ripard
2015-08-20 18:58 ` Mark Brown
2016-05-17 5:44 ` Michal Suchanek [this message]
2015-08-20 19:00 ` Mark Brown
[not found] ` <a5a061d98b7ff851866cc668cd8bf8f6fc99d002.1440080122.git.hramrach@gmail.com>
2015-08-20 14:58 ` [PATCH 5/9] ARM: dts: sun7i: cubieboard2: Enable SPI0 Maxime Ripard
[not found] ` <90730047894f6ec84cd70062a27b7085c2016260.1440080122.git.hramrach@gmail.com>
2015-08-20 15:00 ` [PATCH 7/9] ARM: dts: sun5i: add SPI pins on A13 and A10s Maxime Ripard
[not found] ` <3688fab67e7cdc7bcbff73dfd6b0fcdcc4e79eb6.1440080122.git.hramrach@gmail.com>
2015-08-20 14:48 ` [PATCH 3/9] spi: sunxi: check that transfer speed is non-zero Maxime Ripard
2015-08-20 19:45 ` Michal Suchanek
2015-08-20 21:23 ` Maxime Ripard
2015-08-20 18:45 ` Mark Brown
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