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From: Michal Suchanek <hramrach@gmail.com>
Date: Sun, 16 Aug 2015 12:20:15 +0200
Message-ID: <CAOMqctTQjA5S9ZnR-k5+jFyTOAc-wvWG1mS_21OmJYmtCP+UiA@mail.gmail.com>
Subject: Re: [PATCH v4 0/7] Add spi-nor SPI transfer error handling
To: =?UTF-8?B?QmVhbiBIdW8g6ZyN5paM5paMIChiZWFuaHVvKQ==?= 
	<beanhuo@micron.com>
Cc: Hou Zhiqiang <B48286@freescale.com>,
        "shijie.huang@intel.com" <shijie.huang@intel.com>,
        David Woodhouse <dwmw2@infradead.org>,
        Brian Norris <computersforpeace@gmail.com>,
        Han Xu <han.xu@freescale.com>,
        =?UTF-8?B?UmFmYcOF4oCaIE1pw4XigJplY2tp?= <zajec5@gmail.com>,
        Ben Hutchings <ben@decadent.org.uk>, Marek Vasut <marex@denx.de>,
        Gabor Juhos <juhosg@openwrt.org>,
        "linux-mtd@lists.infradead.org" <linux-mtd@lists.infradead.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
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Hello,

On 15 August 2015 at 03:51, Bean Huo 霍斌斌 (beanhuo) <beanhuo@micron.com> wrote:
>>Hello,
>
>>with these patches SPI transfer errors are not silently ignored but rather reported to spi-nor users.
>
>>This should prevent silently dropping data to the floor in cases when the SPI transfer fails and the failure is detected.
>
>>It has been pointed out that MTD users do not handle the case when data is read only partially so this version adds the last patch which handles this in spi-nor.
>
>>Thanks
>
>>Michal
>  Seems parallel nand read/write also has the same condition.

I am not familiar with parallel NAND drivers so I have no idea if
parallel nand can fail in similar way.

As I understand it the parallel nand controller is dedicated piece of
hardware just for accessing the nand so there may not be any problems
similar to what the generic SPI bus has.

Thanks

Michal