From: Atish Patra <atishp@atishpatra.org>
To: Rob Herring <robh@kernel.org>
Cc: "linux-kernel@vger.kernel.org List"
<linux-kernel@vger.kernel.org>, Alexandre Ghiti <alex@ghiti.fr>,
Anup Patel <anup.patel@wdc.com>,
Greentime Hu <greentime.hu@sifive.com>,
Guo Ren <guoren@linux.alibaba.com>,
Heinrich Schuchardt <xypron.glpk@gmx.de>,
Ingo Molnar <mingo@kernel.org>,
Jisheng Zhang <jszhang@kernel.org>,
kvm-riscv@lists.infradead.org, KVM General <kvm@vger.kernel.org>,
linux-riscv <linux-riscv@lists.infradead.org>,
Marc Zyngier <maz@kernel.org>,
Nanyong Sun <sunnanyong@huawei.com>,
Nick Kossifidis <mick@ics.forth.gr>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Pekka Enberg <penberg@kernel.org>,
Vincent Chen <vincent.chen@sifive.com>,
Vitaly Wool <vitaly.wool@konsulko.com>
Subject: Re: [RFC 0/6] Sparse HART id support
Date: Mon, 13 Dec 2021 16:58:40 -0800 [thread overview]
Message-ID: <CAOnJCU+3cxXDZcnzFpXb+2CLYk7=0aiD6zyCU5=SCWMCFLKPzw@mail.gmail.com> (raw)
In-Reply-To: <CAL_JsqL_DXTJMdUGVwa1T9HqzcJkae=PS12dBbhFS9A22XK6=w@mail.gmail.com>
On Mon, Dec 13, 2021 at 3:11 PM Rob Herring <robh@kernel.org> wrote:
>
> On Mon, Dec 13, 2021 at 3:27 PM Atish Patra <atishp@atishpatra.org> wrote:
> >
> > On Mon, Dec 6, 2021 at 7:28 AM Rob Herring <robh@kernel.org> wrote:
> > >
> > > On Fri, Dec 03, 2021 at 04:20:32PM -0800, Atish Patra wrote:
> > > > Currently, sparse hartid is not supported for Linux RISC-V for the following
> > > > reasons.
> > > > 1. Both spinwait and ordered booting method uses __cpu_up_stack/task_pointer
> > > > which is an array size of NR_CPUs.
> > > > 2. During early booting, any hartid greater than NR_CPUs are not booted at all.
> > > > 3. riscv_cpuid_to_hartid_mask uses struct cpumask for generating hartid bitmap.
> > > > 4. SBI v0.2 implementation uses NR_CPUs as the maximum hartid number while
> > > > generating hartmask.
> > > >
> > > > In order to support sparse hartid, the hartid & NR_CPUS needs to be disassociated
> > > > which was logically incorrect anyways. NR_CPUs represent the maximum logical|
> > > > CPU id configured in the kernel while the hartid represent the physical hartid
> > > > stored in mhartid CSR defined by the privilege specification. Thus, hartid
> > > > can have much greater value than logical cpuid.
> > >
> > > We already have a couple of architectures with logical to physical CPU
> > > id maps. See cpu_logical_map. Can we make that common and use it here?
> >
> > Yes. We can move the cpu_logical_map(which is a macro) &
> > __cpu_logical_map(actual array with NR_CPUS size)
> > to common code so that all the architecture can use it instead of
> > defining it separately.
>
> IIRC, the macro is what varies by arch and I would move to static
> inlines rather than supporting:
>
> cpu_logical_map(cpu) = 0xdeadbeef;
>
Sounds good.
> >
> > > That would also possibly allow for common populating the map from DT.
> > >
> >
> > I didn't understand this part. The mapping is populated at run time
> > [1] as the boot cpu can be any hart in RISC-V.
> > That booting hart will be mapped to cpu 0. All others will be mapped
> > based on how the cpu node is laid out in the DT.
> > Do you mean we can move the 2nd part to common code as well ?
>
> Yes, as the DT platforms just loop thru the cpu nodes and fill the
> logical map based on 'reg', I don't think that needs to be per arch
> once we have a common map. But not asking for that now.
>
It would make sense to keep them together in a series. I can take a stab
at it once this series is merged so that we don't end up in
conflicting changes between
two series.
> Rob
--
Regards,
Atish
prev parent reply other threads:[~2021-12-14 0:58 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-04 0:20 [RFC 0/6] Sparse HART id support Atish Patra
2021-12-04 0:20 ` [RFC 1/6] RISC-V: Avoid using per cpu array for ordered booting Atish Patra
2021-12-13 12:48 ` Anup Patel
2021-12-13 21:05 ` Atish Patra
2021-12-04 0:20 ` [RFC 2/6] RISC-V: Do not print the SBI version during HSM extension boot print Atish Patra
2021-12-13 12:49 ` Anup Patel
2021-12-04 0:20 ` [RFC 3/6] RISC-V: Use __cpu_up_stack/task_pointer only for spinwait method Atish Patra
2021-12-13 12:50 ` Anup Patel
2021-12-13 12:59 ` Marc Zyngier
2021-12-13 21:12 ` Atish Patra
2021-12-04 0:20 ` [RFC 5/6] RISC-V: Move spinwait booting method to its own config Atish Patra
2021-12-04 0:40 ` Randy Dunlap
2021-12-13 13:01 ` Anup Patel
2021-12-13 21:08 ` Atish Patra
2021-12-04 0:20 ` [RFC 6/6] RISC-V: Do not use cpumask data structure for hartid bitmap Atish Patra
2021-12-06 15:28 ` [RFC 0/6] Sparse HART id support Rob Herring
2021-12-13 21:27 ` Atish Patra
2021-12-13 23:11 ` Rob Herring
2021-12-14 0:58 ` Atish Patra [this message]
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