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From: "Jan Dąbroś" <jsd@semihalf.com>
To: Jarkko Nikula <jarkko.nikula@linux.intel.com>
Cc: Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
	linux-i2c <linux-i2c@vger.kernel.org>,
	Andy Shevchenko <andriy.shevchenko@linux.intel.com>,
	Mika Westerberg <mika.westerberg@linux.intel.com>,
	Raul E Rangel <rrangel@chromium.org>,
	"Easow, Nimesh" <Nimesh.Easow@amd.com>,
	upstream@semihalf.com
Subject: Re: [PATCH] i2c: designware: Modify timing parameters for amdpsp mailbox
Date: Thu, 28 Apr 2022 15:42:11 +0200	[thread overview]
Message-ID: <CAOtMz3OeLzvtJ_T6w9v-OYCbTTxpfQjLsajN-a439QuETod7hQ@mail.gmail.com> (raw)
In-Reply-To: <60218a3b-9b56-d9c1-a0f4-97c171a050ba@linux.intel.com>

czw., 28 kwi 2022 o 15:07 Jarkko Nikula
<jarkko.nikula@linux.intel.com> napisał(a):
>
> On 4/28/22 15:26, Jan Dabros wrote:
> > Adjust retry period and timeout values for x86-PSP mailbox based on the
> > typical I2C traffic generated by PSP. In order to limit the possibility
> > of timeouts, x86 should reduce the interval between retries as well as
> > increase overall time after which it gives up.
> >
> > Signed-off-by: Jan Dabros <jsd@semihalf.com>
> > ---
> >   drivers/i2c/busses/i2c-designware-amdpsp.c | 4 ++--
> >   1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/i2c/busses/i2c-designware-amdpsp.c b/drivers/i2c/busses/i2c-designware-amdpsp.c
> > index 9b37f2b95abc..b624356c945f 100644
> > --- a/drivers/i2c/busses/i2c-designware-amdpsp.c
> > +++ b/drivers/i2c/busses/i2c-designware-amdpsp.c
> > @@ -16,8 +16,8 @@
> >   #define PSP_CMD_TIMEOUT_US  (500 * USEC_PER_MSEC)
> >
> >   #define PSP_I2C_REQ_BUS_CMD         0x64
> > -#define PSP_I2C_REQ_RETRY_CNT                10
> > -#define PSP_I2C_REQ_RETRY_DELAY_US   (50 * USEC_PER_MSEC)
> > +#define PSP_I2C_REQ_RETRY_CNT                400
> > +#define PSP_I2C_REQ_RETRY_DELAY_US   (25 * USEC_PER_MSEC)
> >   #define PSP_I2C_REQ_STS_OK          0x0
> >   #define PSP_I2C_REQ_STS_BUS_BUSY    0x1
> >   #define PSP_I2C_REQ_STS_INV_PARAM   0x3
>
> Out of curiosity, can it be up to 400 * 25 ms = 10 s?

Right, worst case x86 is trying to take arbitration of the bus for
10s. But this is very unlikely (margin of safety).

> Acked-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>

Thanks!

Best Regards,
Jan

  reply	other threads:[~2022-04-28 13:42 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-04-28 12:26 [PATCH] i2c: designware: Modify timing parameters for amdpsp mailbox Jan Dabros
2022-04-28 13:07 ` Jarkko Nikula
2022-04-28 13:42   ` Jan Dąbroś [this message]
2022-05-04 19:55 ` Wolfram Sang
2022-05-16 13:34   ` Jan Dąbroś

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