From: Kyle Huey <me@kylehuey.com>
To: Thomas Gleixner <tglx@linutronix.de>
Cc: "David Matlack" <dmatlack@google.com>,
"Robert O'Callahan" <robert@ocallahan.org>,
"Andy Lutomirski" <luto@kernel.org>,
"Ingo Molnar" <mingo@redhat.com>,
"H. Peter Anvin" <hpa@zytor.com>, "X86 ML" <x86@kernel.org>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Radim Krčmář" <rkrcmar@redhat.com>,
"Jeff Dike" <jdike@addtoit.com>,
"Richard Weinberger" <richard@nod.at>,
"Alexander Viro" <viro@zeniv.linux.org.uk>,
"Shuah Khan" <shuah@kernel.org>,
"Dave Hansen" <dave.hansen@linux.intel.com>,
"Borislav Petkov" <bp@suse.de>,
"Peter Zijlstra" <peterz@infradead.org>,
"Boris Ostrovsky" <boris.ostrovsky@oracle.com>,
"Len Brown" <len.brown@intel.com>,
"Rafael J. Wysocki" <rafael.j.wysocki@intel.com>,
"Dmitry Safonov" <dsafonov@virtuozzo.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"open list:USER-MODE LINUX (UML)"
<user-mode-linux-devel@lists.sourceforge.net>,
"open list:USER-MODE LINUX (UML)"
<user-mode-linux-user@lists.sourceforge.net>,
"open list:FILESYSTEMS (VFS and infrastructure)"
<linux-fsdevel@vger.kernel.org>,
"open list:KERNEL SELFTEST FRAMEWORK"
<linux-kselftest@vger.kernel.org>,
"kvm list" <kvm@vger.kernel.org>
Subject: Re: [PATCH v9 7/7] KVM: x86: virtualize cpuid faulting
Date: Tue, 8 Nov 2016 10:00:18 -0800 [thread overview]
Message-ID: <CAP045Ar24oEUG3XcAtyv66Ch6Mi+Sdk7AokXkaPntLHb7VbCgw@mail.gmail.com> (raw)
In-Reply-To: <alpine.DEB.2.20.1611081851380.3501@nanos>
On Tue, Nov 8, 2016 at 9:53 AM, Thomas Gleixner <tglx@linutronix.de> wrote:
> On Tue, 8 Nov 2016, Kyle Huey wrote:
>> > It will simplify the MSR get/set code, and make it easier to plumb
>> > support for new bits in these MSRs.
>>
>> I'm inclined to do this for MSR_PLATFORM_INFO but not
>> MSR_MISC_FEATURES_ENABLES. The former actually has other bits, and
>> isn't used outside the msr handling code (yet, anyways).
>> MSR_MISC_FEATURES_ENABLES doesn't have any other bits (it's actually
>> not documented by Intel at all outside of that virtualization paper)
>> and after masking bits in cpuid.c or adding a helper function the
>> complexity would be a wash at best.
>
> The feature MSR is also used for enabling ring3 MWAIT, which is obviously
> not documented either. So there is more stuff coming along....
>
> Thanks,
>
> tglx
>
Bah :) Ok.
- Kyle
next prev parent reply other threads:[~2016-11-08 18:00 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-11-06 20:57 [PATCH v9 0/7] x86/arch_prctl Add ARCH_[GET|SET]_CPUID for controlling the CPUID instruction Kyle Huey
2016-11-06 20:57 ` [PATCH v9 1/7] x86/arch_prctl/64: Use SYSCALL_DEFINE2 to define sys_arch_prctl Kyle Huey
2016-11-06 20:57 ` [PATCH v9 2/7] x86/arch_prctl/64: Rename do_arch_prctl to do_arch_prctl_64 Kyle Huey
2016-11-06 20:57 ` [PATCH v9 3/7] x86/arch_prctl: Add do_arch_prctl_common Kyle Huey
2016-11-06 20:57 ` [PATCH v9 4/7] x86/syscalls/32: Wire up arch_prctl on x86-32 Kyle Huey
2016-11-06 20:57 ` [PATCH v9 5/7] x86/cpufeature: Detect CPUID faulting support Kyle Huey
2016-11-06 20:57 ` [PATCH v9 6/7] x86/arch_prctl: Add ARCH_[GET|SET]_CPUID Kyle Huey
2016-11-06 20:57 ` [PATCH v9 7/7] KVM: x86: virtualize cpuid faulting Kyle Huey
2016-11-07 20:13 ` David Matlack
2016-11-08 17:42 ` Kyle Huey
2016-11-08 17:53 ` Thomas Gleixner
2016-11-08 18:00 ` Kyle Huey [this message]
2016-11-08 17:58 ` Kyle Huey
2016-11-08 17:58 ` Kyle Huey
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