From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C7B04C3F2CE for ; Wed, 4 Mar 2020 16:37:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 9D4CA2166E for ; Wed, 4 Mar 2020 16:37:25 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="b/h5yz5w" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729837AbgCDQhY (ORCPT ); Wed, 4 Mar 2020 11:37:24 -0500 Received: from mail-vs1-f68.google.com ([209.85.217.68]:34197 "EHLO mail-vs1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726694AbgCDQhY (ORCPT ); Wed, 4 Mar 2020 11:37:24 -0500 Received: by mail-vs1-f68.google.com with SMTP id y204so1577872vsy.1 for ; Wed, 04 Mar 2020 08:37:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=hABaqSyYZLOUCpK2+i1NqdTSDdnUnv1VCEKCW00h9WI=; b=b/h5yz5wlSBuj4Lbv+kbPLguRwtFdV5HC/ap61En5X/K6/4YD+4zRyFLn78H9qD27V 7GAA7Uuczidrny2Vt2luLVc9+Ex0aJ/lGNQ8tEBs+DmWPecQpoBQb9F4JV2uw2bgipSd CAvK4wsRbKO/d+Z9hQUQmcLpGcMtuAroXiK2hFYLHgxsa0Ifiu+7sZ7f5dG1zniuK5l+ zPvvbaNW6IJT2P4KEmZdKgwZ2kGkOtvy8B3ZjXOvKK+D2Ptk8sh8yVy91lCEUh+rSHVp 1UwsYKyiQMqvc89tkSoFnVWGIhC5EDiBTZ9whQR4DYCLTFMHOLW8XrXJrII2HeibgVs6 W4NA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=hABaqSyYZLOUCpK2+i1NqdTSDdnUnv1VCEKCW00h9WI=; b=JsFTFn8GaHh2eDl0e7YseS1OA/ebMjzqFMS+9ywMvoSyTxn+9TfgJ4LZHpui1agTch vJCqIl9tLdrpOfvFGCvUdhBZQ7c+mtjUdJrpGPSFUwVUXcn0r4BPUw2pP/bzPDMeDB6+ c9QO8zr8LhLLF9HoijmUd7iLHHOweZzWejZOfv+Xgw74a2U3QhXzHHAK588wCov6A9Oq c2VgVnV/XaOslIAIMHTJU1T20OPKlwW/m9iZ2hx8col2IdzB6NftBr4X1QEv1o4Bhvur bJXElJIzh34WvUBusSO+fMs4tzPWBuRnmTU6yOBnqudWibueOr7qvMltik9r5h+FF8ro HyoA== X-Gm-Message-State: ANhLgQ0HnJ+wSCayvTlIjZGQ9grUZMlB6jvT1sibWV58bXHm24601APd Xom+hvJ4zVAtVGwp6qExJs326q1HTlctftogHf7/6g== X-Google-Smtp-Source: ADFU+vsqaKb2RoRKxPcXhxp65L9DlvDybJ++9ZBqVDK57rvpHpGbRYrYO7V96B/Jdy+fc8mQrqBMgQDJ+jef4TTwT+Y= X-Received: by 2002:a67:7fd0:: with SMTP id a199mr2328053vsd.200.1583339842981; Wed, 04 Mar 2020 08:37:22 -0800 (PST) MIME-Version: 1.0 References: <20200224231841.26550-1-digetx@gmail.com> <20200224231841.26550-4-digetx@gmail.com> <44c22925-a14e-96d0-1f93-1979c0c60525@wwwdotorg.org> In-Reply-To: <44c22925-a14e-96d0-1f93-1979c0c60525@wwwdotorg.org> From: Ulf Hansson Date: Wed, 4 Mar 2020 17:36:46 +0100 Message-ID: Subject: Re: [PATCH v1 3/3] partitions: Introduce NVIDIA Tegra Partition Table To: Stephen Warren , Dmitry Osipenko Cc: Jens Axboe , Thierry Reding , Jonathan Hunter , =?UTF-8?B?TWljaGHFgiBNaXJvc8WCYXc=?= , David Heidelberg , Peter Geis , Nicolas Chauvet , Adrian Hunter , Billy Laws , linux-tegra , linux-block , Andrey Danin , Gilles Grandou , Ryan Grachek , "linux-mmc@vger.kernel.org" , Linux Kernel Mailing List Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, 25 Feb 2020 at 01:20, Stephen Warren wrote: > > On 2/24/20 4:18 PM, Dmitry Osipenko wrote: > > All NVIDIA Tegra devices use a special partition table format for the > > internal storage partitioning. Most of Tegra devices have GPT partition > > in addition to TegraPT, but some older Android consumer-grade devices do > > not or GPT is placed in a wrong sector, and thus, the TegraPT is needed > > in order to support these devices properly in the upstream kernel. This > > patch adds support for NVIDIA Tegra Partition Table format that is used > > at least by all NVIDIA Tegra20 and Tegra30 devices. > > > diff --git a/arch/arm/mach-tegra/tegra.c b/arch/arm/mach-tegra/tegra.c > > > +static void __init tegra_boot_config_table_init(void) > > +{ > > + void __iomem *bct_base; > > + u16 pt_addr, pt_size; > > + > > + bct_base = IO_ADDRESS(TEGRA_IRAM_BASE) + TEGRA_IRAM_BCT_OFFSET; > > This shouldn't be hard-coded. IIRC, the boot ROM writes a BIT (Boot > Information Table) to a fixed location in IRAM, and there's some value > in the BIT that points to where the BCT is in IRAM. In practice, it > might work out that the BCT is always at the same place in IRAM, but > this certainly isn't guaranteed. I think there's code in U-Boot which > extracts the BCT location from the BIT? Yes, see > arch/arm/mach-tegra/ap.c:get_odmdata(). So, have you considered using the command line partition option, rather than adding yet another partition scheme to the kernel? In principle, you would let the boot loader scan for the partitions, likely from machine specific code in U-boot. Then you append these to the kernel command line and let block/partitions/cmdline.c scan for it. Kind regards Uffe