From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4BFE1C433EF for ; Fri, 1 Oct 2021 15:02:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 36AD86126A for ; Fri, 1 Oct 2021 15:02:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1354778AbhJAPDn (ORCPT ); Fri, 1 Oct 2021 11:03:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33348 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1354747AbhJAPDf (ORCPT ); Fri, 1 Oct 2021 11:03:35 -0400 Received: from mail-lf1-x12f.google.com (mail-lf1-x12f.google.com [IPv6:2a00:1450:4864:20::12f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E20A6C06177D for ; Fri, 1 Oct 2021 08:01:50 -0700 (PDT) Received: by mail-lf1-x12f.google.com with SMTP id i4so40379931lfv.4 for ; Fri, 01 Oct 2021 08:01:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=Wl3ZMyIoq68XUN9ZysEDdbNyOTOcWVKDq09iuCEsZmc=; b=nc/wRiOyNThsvZAoZqrqxfcMp5xM4+z3v5LBnRr7cDxfQB3CuDz+w9I+DrmCVjWOKl np27NqLQZ/GN1BOsQnTqAa2UnIwF19eGxu64prAseFDGzGs8fstw8HcPfShlYRQ0qE1c WBjvqHBepPh7/S1osWRA5oJkTk2LMoL8V+Rr/1CAVQRt+OOzX2VJn6rhiBggeGf0jaLd I5s3lo9wgue1e92EUCmCI977jDYPuMA5YYpLfqE1ZPhrxcH8sAmJV+ED8ef6hVn8S0D5 bD46sji6e0iHnnK6F4WHN2ijZ4ehxPr5Lmm8HNBreW4wKt5dklt3O1Dh0kW0EnVCwAx4 w7NQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=Wl3ZMyIoq68XUN9ZysEDdbNyOTOcWVKDq09iuCEsZmc=; b=XvGqqmcH7vzLZybuPDEGLKZmukybRealZIu/mcmp6BJ0/a1zmYQQ0wYUeYWW5fU34y jh4Mr+ybj0DUWqZ0Jyq9mxNlqri00JATbGWV9RRWnsDhdAKuxoEdjaj6zFbON0KllaE5 P5DQecQVfQQmyXk5+5Za8JsaW6ysTV/1LN7UBRxBoIy0URndfv9zqeP+K4xUL4+SiyA8 CYXQineWVJCUK2+9a/+euG6KhHHnSr5EzUt1mvt+JmDBErRNeAx37JpQHTlcS/WgxDPy 72mwCn58ukSqqYeE/bPs3mScFlv+rtsfLJn+9X8V9zPWpYWbuMqgUiXC2QsvNy0BaISZ y5ug== X-Gm-Message-State: AOAM533lyj7kkhoJmj3iY8D9mmi8fXj5B+CQj9/e4iSlyZODYlrmW3q8 gTBe4mIipCMr/BiFz64Gl+D1fuAI3BezXVJLk9Dh2g== X-Google-Smtp-Source: ABdhPJzMALxdSFVvKbncpXSAkoeLVU4WvZ1aDrH/nsBIXY0lecURQDTr7J6h8lUkTNpeSwp11syRcpWCl/bNnJtDs94= X-Received: by 2002:a05:6512:2397:: with SMTP id c23mr5737854lfv.358.1633100509099; Fri, 01 Oct 2021 08:01:49 -0700 (PDT) MIME-Version: 1.0 References: <20210926224058.1252-1-digetx@gmail.com> <20210926224058.1252-21-digetx@gmail.com> <0bcbcd3d-2154-03d2-f572-dc9032125c26@gmail.com> In-Reply-To: <0bcbcd3d-2154-03d2-f572-dc9032125c26@gmail.com> From: Ulf Hansson Date: Fri, 1 Oct 2021 17:01:12 +0200 Message-ID: Subject: Re: [PATCH v13 20/35] mtd: rawnand: tegra: Add runtime PM and OPP support To: Dmitry Osipenko Cc: Thierry Reding , Jonathan Hunter , Viresh Kumar , Stephen Boyd , Peter De Schrijver , Mikko Perttunen , Peter Chen , Lee Jones , =?UTF-8?Q?Uwe_Kleine=2DK=C3=B6nig?= , Nishanth Menon , Adrian Hunter , Michael Turquette , Linux Kernel Mailing List , linux-tegra , Linux PM , Linux USB List , linux-staging@lists.linux.dev, linux-pwm@vger.kernel.org, linux-mmc , dri-devel , DTML , linux-clk , Mark Brown , Vignesh Raghavendra , Richard Weinberger , Miquel Raynal , Lucas Stach , Stefan Agner , Mauro Carvalho Chehab , David Heidelberg Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, 1 Oct 2021 at 16:35, Dmitry Osipenko wrote: > > 01.10.2021 17:24, Ulf Hansson =D0=BF=D0=B8=D1=88=D0=B5=D1=82: > > On Mon, 27 Sept 2021 at 00:42, Dmitry Osipenko wrote= : > >> > >> The NAND on Tegra belongs to the core power domain and we're going to > >> enable GENPD support for the core domain. Now NAND must be resumed usi= ng > >> runtime PM API in order to initialize the NAND power state. Add runtim= e PM > >> and OPP support to the NAND driver. > >> > >> Acked-by: Miquel Raynal > >> Signed-off-by: Dmitry Osipenko > >> --- > >> drivers/mtd/nand/raw/tegra_nand.c | 55 ++++++++++++++++++++++++++----= - > >> 1 file changed, 47 insertions(+), 8 deletions(-) > >> > >> diff --git a/drivers/mtd/nand/raw/tegra_nand.c b/drivers/mtd/nand/raw/= tegra_nand.c > >> index 32431bbe69b8..098fcc9cb9df 100644 > >> --- a/drivers/mtd/nand/raw/tegra_nand.c > >> +++ b/drivers/mtd/nand/raw/tegra_nand.c > >> @@ -17,8 +17,11 @@ > >> #include > >> #include > >> #include > >> +#include > >> #include > >> > >> +#include > >> + > >> #define COMMAND 0x00 > >> #define COMMAND_GO BIT(31) > >> #define COMMAND_CLE BIT(30) > >> @@ -1151,6 +1154,7 @@ static int tegra_nand_probe(struct platform_devi= ce *pdev) > >> return -ENOMEM; > >> > >> ctrl->dev =3D &pdev->dev; > >> + platform_set_drvdata(pdev, ctrl); > >> nand_controller_init(&ctrl->controller); > >> ctrl->controller.ops =3D &tegra_nand_controller_ops; > >> > >> @@ -1166,14 +1170,22 @@ static int tegra_nand_probe(struct platform_de= vice *pdev) > >> if (IS_ERR(ctrl->clk)) > >> return PTR_ERR(ctrl->clk); > >> > >> - err =3D clk_prepare_enable(ctrl->clk); > >> + err =3D devm_pm_runtime_enable(&pdev->dev); > >> + if (err) > >> + return err; > >> + > >> + err =3D devm_tegra_core_dev_init_opp_table_common(&pdev->dev); > >> + if (err) > >> + return err; > >> + > >> + err =3D pm_runtime_resume_and_get(&pdev->dev); > >> if (err) > >> return err; > >> > >> err =3D reset_control_reset(rst); > >> if (err) { > >> dev_err(ctrl->dev, "Failed to reset HW: %d\n", err); > >> - goto err_disable_clk; > >> + goto err_put_pm; > >> } > >> > >> writel_relaxed(HWSTATUS_CMD_DEFAULT, ctrl->regs + HWSTATUS_CMD= ); > >> @@ -1188,21 +1200,19 @@ static int tegra_nand_probe(struct platform_de= vice *pdev) > >> dev_name(&pdev->dev), ctrl); > >> if (err) { > >> dev_err(ctrl->dev, "Failed to get IRQ: %d\n", err); > >> - goto err_disable_clk; > >> + goto err_put_pm; > >> } > >> > >> writel_relaxed(DMA_MST_CTRL_IS_DONE, ctrl->regs + DMA_MST_CTRL= ); > >> > >> err =3D tegra_nand_chips_init(ctrl->dev, ctrl); > >> if (err) > >> - goto err_disable_clk; > >> - > >> - platform_set_drvdata(pdev, ctrl); > >> + goto err_put_pm; > >> > > > > There is no corresponding call pm_runtime_put() here. Is it > > intentional to always leave the device runtime resumed after ->probe() > > has succeeded? > > > > I noticed you included some comments about this for some other > > drivers, as those needed more tweaks. Is that also the case for this > > driver? > > Could you please clarify? There is pm_runtime_put() in both probe-error > and remove() code paths here. I was not considering the error path of ->probe() (or ->remove()), but was rather thinking about when ->probe() completes successfully. Then you keep the device runtime resumed, because you have called pm_runtime_resume_and_get() for it. Shouldn't you have a corresponding pm_runtime_put() in ->probe(), allowing it to be runtime suspended, until the device is really needed later on. No? > > I assume you're meaning pm_runtime_disable(), but this patch uses > resource-managed devm_pm_runtime_enable(), and thus, explicit disable > isn't needed. > > >> return 0; > >> > >> -err_disable_clk: > >> - clk_disable_unprepare(ctrl->clk); > >> +err_put_pm: > >> + pm_runtime_put(ctrl->dev); > >> return err; > >> } > >> [...] Kind regards Uffe