From: Ulf Hansson <ulf.hansson@linaro.org>
To: Rajat Jain <rajatja@google.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>,
Bjorn Helgaas <bhelgaas@google.com>,
linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-pci@vger.kernel.org, rajatxjain@gmail.com,
jsbarnes@google.com, gwendal@google.com
Subject: Re: [PATCH] pci/quirks: Add quirk for Bayhub O2 SD controller
Date: Thu, 9 Dec 2021 11:05:56 +0100 [thread overview]
Message-ID: <CAPDyKFqW_ttFxyVixWSuYwQa_SPcecRmf=u9KgMScGn0dd+uCg@mail.gmail.com> (raw)
In-Reply-To: <20211208000948.487820-1-rajatja@google.com>
On Wed, 8 Dec 2021 at 01:09, Rajat Jain <rajatja@google.com> wrote:
>
> This particular SD controller from O2 / Bayhub only allows dword
> accesses to its LTR max latency registers:
> https://github.com/rajatxjain/public_shared/blob/main/OZ711LV2_appnote.pdf
>
> Thus add a quirk that saves and restores these registers
> manually using dword acesses:
> LTR Max Snoop Latency Register
> LTR Max No-Snoop Latency Register
>
> Signed-off-by: Rajat Jain <rajatja@google.com>
Acked-by: Ulf Hansson <ulf.hansson@linaro.org>
Kind regards
Uffe
> ---
> drivers/mmc/host/sdhci-pci.h | 1 -
> drivers/pci/quirks.c | 39 ++++++++++++++++++++++++++++++++++++
> include/linux/pci_ids.h | 1 +
> 3 files changed, 40 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/mmc/host/sdhci-pci.h b/drivers/mmc/host/sdhci-pci.h
> index 5e3193278ff9..d47cc0ba7ca4 100644
> --- a/drivers/mmc/host/sdhci-pci.h
> +++ b/drivers/mmc/host/sdhci-pci.h
> @@ -10,7 +10,6 @@
> #define PCI_DEVICE_ID_O2_SDS1 0x8421
> #define PCI_DEVICE_ID_O2_FUJIN2 0x8520
> #define PCI_DEVICE_ID_O2_SEABIRD0 0x8620
> -#define PCI_DEVICE_ID_O2_SEABIRD1 0x8621
>
> #define PCI_DEVICE_ID_INTEL_PCH_SDIO0 0x8809
> #define PCI_DEVICE_ID_INTEL_PCH_SDIO1 0x880a
> diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
> index 003950c738d2..b7bd19802744 100644
> --- a/drivers/pci/quirks.c
> +++ b/drivers/pci/quirks.c
> @@ -5857,3 +5857,42 @@ static void nvidia_ion_ahci_fixup(struct pci_dev *pdev)
> pdev->dev_flags |= PCI_DEV_FLAGS_HAS_MSI_MASKING;
> }
> DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, 0x0ab8, nvidia_ion_ahci_fixup);
> +
> +/*
> + * Bayhub OZ711LV2 SD controller has an errata that only allows DWORD accesses
> + * to the LTR max latency registers. Thus need to save and restore these
> + * registers manually.
> + */
> +static void o2_seabird1_save_ltr(struct pci_dev *dev)
> +{
> + struct pci_cap_saved_state *save_state;
> + u32 *reg32;
> +
> + save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_LTR);
> + if (save_state) {
> + reg32 = &save_state->cap.data[0];
> + /* Preserve PCI_LTR_MAX_SNOOP_LAT & PCI_LTR_MAX_NOSNOOP_LAT */
> + pci_read_config_dword(dev, 0x234, reg32);
> + } else {
> + pci_err(dev, "quirk can't save LTR snoop latency\n");
> + }
> +}
> +
> +static void o2_seabird1_restore_ltr(struct pci_dev *dev)
> +{
> + struct pci_cap_saved_state *save_state;
> + u32 *reg32;
> +
> + save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_LTR);
> + if (save_state) {
> + reg32 = &save_state->cap.data[0];
> + /* Restore PCI_LTR_MAX_SNOOP_LAT & PCI_LTR_MAX_NOSNOOP_LAT */
> + pci_write_config_dword(dev, 0x234, *reg32);
> + } else {
> + pci_err(dev, "quirk can't restore LTR snoop latency\n");
> + }
> +}
> +DECLARE_PCI_FIXUP_SUSPEND_LATE(PCI_VENDOR_ID_O2, PCI_DEVICE_ID_O2_SEABIRD1,
> + o2_seabird1_save_ltr);
> +DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_O2, PCI_DEVICE_ID_O2_SEABIRD1,
> + o2_seabird1_restore_ltr);
> diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
> index 011f2f1ea5bb..6ed16aa38196 100644
> --- a/include/linux/pci_ids.h
> +++ b/include/linux/pci_ids.h
> @@ -1717,6 +1717,7 @@
> #define PCI_DEVICE_ID_O2_8221 0x8221
> #define PCI_DEVICE_ID_O2_8320 0x8320
> #define PCI_DEVICE_ID_O2_8321 0x8321
> +#define PCI_DEVICE_ID_O2_SEABIRD1 0x8621
>
> #define PCI_VENDOR_ID_3DFX 0x121a
> #define PCI_DEVICE_ID_3DFX_VOODOO 0x0001
> --
> 2.34.1.400.ga245620fadb-goog
>
next prev parent reply other threads:[~2021-12-09 10:06 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-08 0:09 [PATCH] pci/quirks: Add quirk for Bayhub O2 SD controller Rajat Jain
2021-12-09 10:05 ` Ulf Hansson [this message]
2021-12-15 18:04 ` Bjorn Helgaas
2021-12-15 18:15 ` Rajat Jain
2021-12-15 20:27 ` Bjorn Helgaas
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to='CAPDyKFqW_ttFxyVixWSuYwQa_SPcecRmf=u9KgMScGn0dd+uCg@mail.gmail.com' \
--to=ulf.hansson@linaro.org \
--cc=adrian.hunter@intel.com \
--cc=bhelgaas@google.com \
--cc=gwendal@google.com \
--cc=jsbarnes@google.com \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mmc@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=rajatja@google.com \
--cc=rajatxjain@gmail.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).