From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 26769C04FF3 for ; Mon, 24 May 2021 17:03:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 04D906140B for ; Mon, 24 May 2021 17:03:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233345AbhEXRFL (ORCPT ); Mon, 24 May 2021 13:05:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39350 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233282AbhEXRFD (ORCPT ); Mon, 24 May 2021 13:05:03 -0400 Received: from mail-vs1-xe33.google.com (mail-vs1-xe33.google.com [IPv6:2607:f8b0:4864:20::e33]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BDF19C06138B for ; Mon, 24 May 2021 10:03:35 -0700 (PDT) Received: by mail-vs1-xe33.google.com with SMTP id f9so8119339vsp.6 for ; Mon, 24 May 2021 10:03:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=MrqSOYj5g/obDVKIYAxmyXoOnQCVk6QwshkTvwsi7m4=; b=XyizKqOVbO1O1kqzeiPXF8NjsBV2U9Z+KYkApDRPMhoQY9Wd7aF4XJyesh+GK1YVA5 Ub6EukTa0vgpcTPIyPKsHpKh8SRsQbQFCcP+++VNYz1YXYz2lXhoZ9bBghOFurhlwHUk ntb6/JFWmPTTq0gQYS4pNRcJkazgXeDtfbxp9tzTP5JJPQigo4i7WjDXP7dQV6MLvvtw Qq5CbguJpgjiczI1re747pjjYIB5h37C9+mXIwbmORKayNQgqiFyUkiDzDaCY3IBenHt FoTmh0hk4Y2MQQcmxH9KYKLxjMIIAayyNq0B4tqy1nc2mlsNk7avsezzUrjOaV2gKEQJ ohfw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=MrqSOYj5g/obDVKIYAxmyXoOnQCVk6QwshkTvwsi7m4=; b=rHkEDLcfrMsnWXMPSLaEpZ8txeCXD0pCOccdCcxNIl70iOpDMWrv3a8Ils+2JWybaB iNt7ZFTqrKX6uJY4ZjPrHDTVKUf7zkGHWZl+ay3tuOY82XHS99MLoRHIA1GOCXFHUYMp 6ig6GYo3Im575EZXRAXRjGjTw6XKbRuOgknbPcXDMc6phy19PkDFRMt9aa0SnKi4Z4pz 1VR6EW6/qvdGHiotBkSvKaK4uCeUUTgJzD5Qr3xH2bGKehWo32QJ3vOX2O3XUwBLu0Hi fH9YPDRV1gQ+TlhbQR753BiSN6sK0ownt1KmmpDuTImTkgMukrnzlcpJpe0k0ULhXlOG G90w== X-Gm-Message-State: AOAM531P6OXMZgD5LnjDyCPiSBniCSiNh4Em+H6vIiEMK9u0T0vBQlMm 9iN8hEpm+Iqf0BpnMYV83jSKeITZudEEFNJndeiPgA== X-Google-Smtp-Source: ABdhPJwH7kYxWSa0u/62FyAK1s59dR0TfrwpFa2o7rML8WoewkAZu/jGtDNEsxL3yqDKybD0PBSBisVCRwo/3Ef5YLg= X-Received: by 2002:a05:6102:7b4:: with SMTP id x20mr23350062vsg.48.1621875814897; Mon, 24 May 2021 10:03:34 -0700 (PDT) MIME-Version: 1.0 References: <20210523231335.8238-1-digetx@gmail.com> <20210523231335.8238-13-digetx@gmail.com> In-Reply-To: <20210523231335.8238-13-digetx@gmail.com> From: Ulf Hansson Date: Mon, 24 May 2021 19:02:58 +0200 Message-ID: Subject: Re: [PATCH v2 12/14] dt-bindings: soc: tegra-pmc: Document core power domain To: Dmitry Osipenko Cc: Thierry Reding , Jonathan Hunter , =?UTF-8?B?TWljaGHFgiBNaXJvc8WCYXc=?= , =?UTF-8?Q?Nikola_Milosavljevi=C4=87?= , Peter Geis , Nicolas Chauvet , Viresh Kumar , Stephen Boyd , Matt Merhar , Paul Fertser , Mark Brown , Liam Girdwood , Krzysztof Kozlowski , Mikko Perttunen , Linux Kernel Mailing List , linux-tegra , DTML , Linux PM , Nathan Chancellor , linux-clk Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 24 May 2021 at 01:13, Dmitry Osipenko wrote: > > All NVIDIA Tegra SoCs have a core power domain where majority of hardware > blocks reside. Document the new core power domain properties. > > Reviewed-by: Rob Herring > Signed-off-by: Dmitry Osipenko Reviewed-by: Ulf Hansson Kind regards Uffe > --- > .../arm/tegra/nvidia,tegra20-pmc.yaml | 35 +++++++++++++++++++ > 1 file changed, 35 insertions(+) > > diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml > index 43fd2f8927d0..0afec83cc723 100644 > --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml > +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml > @@ -301,6 +301,33 @@ patternProperties: > > additionalProperties: false > > + core-domain: > + type: object > + description: | > + The vast majority of hardware blocks of Tegra SoC belong to a > + Core power domain, which has a dedicated voltage rail that powers > + the blocks. > + > + properties: > + operating-points-v2: > + description: > + Should contain level, voltages and opp-supported-hw property. > + The supported-hw is a bitfield indicating SoC speedo or process > + ID mask. > + > + "#power-domain-cells": > + const: 0 > + > + required: > + - operating-points-v2 > + - "#power-domain-cells" > + > + additionalProperties: false > + > + core-supply: > + description: > + Phandle to voltage regulator connected to the SoC Core power rail. > + > required: > - compatible > - reg > @@ -325,6 +352,7 @@ examples: > tegra_pmc: pmc@7000e400 { > compatible = "nvidia,tegra210-pmc"; > reg = <0x7000e400 0x400>; > + core-supply = <®ulator>; > clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; > clock-names = "pclk", "clk32k_in"; > #clock-cells = <1>; > @@ -338,17 +366,24 @@ examples: > nvidia,core-power-req-active-high; > nvidia,sys-clock-req-active-high; > > + pd_core: core-domain { > + operating-points-v2 = <&core_opp_table>; > + #power-domain-cells = <0>; > + }; > + > powergates { > pd_audio: aud { > clocks = <&tegra_car TEGRA210_CLK_APE>, > <&tegra_car TEGRA210_CLK_APB2APE>; > resets = <&tegra_car 198>; > + power-domains = <&pd_core>; > #power-domain-cells = <0>; > }; > > pd_xusbss: xusba { > clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>; > resets = <&tegra_car TEGRA210_CLK_XUSB_SS>; > + power-domains = <&pd_core>; > #power-domain-cells = <0>; > }; > }; > -- > 2.30.2 >