From: "Lespiau, Damien" <damien.lespiau@intel.com>
To: Keith Packard <keithp@keithp.com>
Cc: intel-gfx@lists.freedesktop.org,
Daniel Vetter <daniel.vetter@ffwll.ch>,
linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 6/7] drm/i915: Disable FDI RX before FDI TX
Date: Fri, 17 Aug 2012 17:43:22 +0100 [thread overview]
Message-ID: <CAPX-8+_bZNyXL0b8nBkN97sj-KnT_eZXZ-5Hp5R6P-L-D-QAKg@mail.gmail.com> (raw)
In-Reply-To: <1344918891-6283-7-git-send-email-keithp@keithp.com>
On Tue, Aug 14, 2012 at 5:34 AM, Keith Packard <keithp@keithp.com> wrote:
> Doesn't make sense to disable in the other order.
>
> Signed-off-by: Keith Packard <keithp@keithp.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 10 +++++-----
> 1 file changed, 5 insertions(+), 5 deletions(-)
I can't see anything in the docs about an order requirement for those.
Not sure why the other way does not make sense. Somehow disabling TX
before RX makes some sense to me (TX enabled without a ready RX looks
weird?, no data should flow as the pipe is shutdown at that point
anyway). Maybe it just does not matter?
Another detail is that disabling the PLLs seem to have an order in the
disabling sequence, TX, then RX.
I. Disable CPU FDI Transmitter PLL
II. Disable PCH FDI Receiver PLL
--
Damien
next prev parent reply other threads:[~2012-08-17 16:43 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <1344918891-6283-1-git-send-email-keithp@keithp.com>
[not found] ` <1344918891-6283-2-git-send-email-keithp@keithp.com>
2012-08-15 22:42 ` [PATCH 1/7] drm/i915: Allow VGA on CRTC 2 Daniel Vetter
[not found] ` <1344918891-6283-3-git-send-email-keithp@keithp.com>
2012-08-17 14:45 ` [Intel-gfx] [PATCH 2/7] drm/i915: FDI B/C share 4 lanes on Ivybridge Lespiau, Damien
2012-08-17 15:00 ` Keith Packard
2012-08-17 15:12 ` Lespiau, Damien
[not found] ` <1344918891-6283-5-git-send-email-keithp@keithp.com>
2012-08-17 14:58 ` [Intel-gfx] [PATCH 4/7] drm/i915: Check display_bpc against max_fdi_bpp after display_bpc is set Lespiau, Damien
[not found] ` <1344918891-6283-4-git-send-email-keithp@keithp.com>
2012-08-17 15:34 ` [Intel-gfx] [PATCH 3/7] drm/i915: Delay between FDI link training tries. Clear FDI_RX_IIR before training Lespiau, Damien
[not found] ` <1344918891-6283-6-git-send-email-keithp@keithp.com>
2012-08-17 15:50 ` [Intel-gfx] [PATCH 5/7] drm/i915: Pipe-C only configurations would not get SR Lespiau, Damien
[not found] ` <1344918891-6283-7-git-send-email-keithp@keithp.com>
2012-08-17 16:43 ` Lespiau, Damien [this message]
2012-08-17 23:10 ` [Intel-gfx] [PATCH 6/7] drm/i915: Disable FDI RX before FDI TX Keith Packard
[not found] ` <1344918891-6283-8-git-send-email-keithp@keithp.com>
2012-08-17 17:14 ` [Intel-gfx] [PATCH 7/7] drm/i915: Merge FDI RX reg writes during training Lespiau, Damien
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