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From: Dan Williams <>
To: Linus Torvalds <>
Cc:, Linux NVDIMM <>,
	Linux PCI <>,
	Linux Kernel Mailing List <>
Subject: [GIT PULL] Compute Express Link (CXL) update for v5.14
Date: Sat, 3 Jul 2021 08:08:28 -0700	[thread overview]
Message-ID: <> (raw)

Hi Linus, please pull from:

  git:// tags/cxl-for-5.14 receive the CXL update for v5.14. This subsystem is still in the
build-out phase as the bulk of the update is improvements to
enumeration and fleshing out the device model. In terms of new
features, more mailbox commands have been added to the allowed-list in
support of persistent memory provisioning support targeting v5.15. The
critical update from an enumeration perspective is support for the CXL
Fixed Memory Window Structure that indicates to Linux which system
physical address ranges decode to the CXL Host Bridges in the system.
This allows the driver to detect which address ranges have been mapped
by firmware and what address ranges are available for future hotplug.

So, again, mostly skeleton this round, with more meat targeting v5.15.

The bulk of this has been in -next with no reported issues. The top 3
commits were promoted from the cxl 'pending' to 'next' branch recently
and -next has not had a chance to pick those up yet, but the kbuild
robot has chewed on that pending branch for a couple weeks.

Please pull, thanks.


The following changes since commit 4a2c1dcfaf59be4b357400d893c3f5daff6cab6c:

  ACPICA: Add the CFMWS structure definition to the CEDT table
(2021-06-07 14:04:43 +0200)

are available in the Git repository at:

  git:// tags/cxl-for-5.14

for you to fetch changes up to 4ad6181e4b216ed0cb52f45d3c6d2c70c8ae9243:

  cxl/pci: Rename CXL REGLOC ID (2021-06-17 17:37:18 -0700)

cxl for 5.14

- Add support for the CXL Fixed Memory Window Structure, a recent
  extension of the ACPI CEDT (CXL Early Discovery Table)

- Add infrastructure for component registers

- Add HDM (Host-managed device memory) decoder definitions

- Define a device model for an HDM decoder tree

- Bridge CXL persistent memory capabilities to an NVDIMM bus /

- Switch to fine grained mapping of CXL MMIO registers to allow
  different drivers / system software to own individual register blocks

- Enable media provisioning commands, and publish the label storage area
  size in sysfs

- Miscellaneous cleanups and fixes

Alison Schofield (2):
      cxl/acpi: Add the Host Bridge base address to CXL port objects
      cxl/acpi: Use the ACPI CFMWS to create static decoder objects

Ben Widawsky (11):
      cxl: Rename mem to pci
      cxl/mem: Demarcate vendor specific capability IDs
      cxl/mem: Use dev instead of pdev->dev
      cxl/mem: Split creation from mapping in probe
      cxl/mem: Move register locator logic into reg setup
      cxl/mem: Get rid of @cxlm.base
      cxl/pci: Add HDM decoder capabilities
      cxl/hdm: Fix decoder count calculation
      cxl/component_regs: Fix offset
      cxl/pci: Add media provisioning required commands
      cxl/pci: Rename CXL REGLOC ID

Dan Williams (17):
      cxl/mem: Move some definitions to mem.h
      cxl/mem: Introduce 'struct cxl_regs' for "composable" CXL devices
      cxl/core: Rename bus.c to core.c
      cxl/core: Refactor CXL register lookup for bridge reuse
      cxl/docs: Fix "Title underline too short" warning
      cxl/pci: Fixup devm_cxl_iomap_block() to take a 'struct device *'
      Merge branch 'rafael/acpica/cfmws' into for-5.14/cxl
      cxl/acpi: Introduce the root of a cxl_port topology
      cxl/Kconfig: Default drivers to CONFIG_CXL_BUS
      cxl/acpi: Add downstream port data to cxl_port instances
      cxl/acpi: Enumerate host bridge root ports
      cxl/acpi: Introduce cxl_decoder objects
      cxl/core: Add cxl-bus driver infrastructure
      cxl/pmem: Add initial infrastructure for pmem support
      libnvdimm: Export nvdimm shutdown helper, nvdimm_delete()
      libnvdimm: Drop unused device power management support
      cxl/pmem: Register 'pmem' / cxl_nvdimm devices

Ira Weiny (4):
      cxl/pci: Introduce cxl_decode_register_block()
      cxl/pci: Reserve all device regions at once
      cxl/pci: Map registers based on capabilities
      cxl/pci: Reserve individual register block regions

Vishal Verma (1):
      cxl/pci.c: Add a 'label_storage_size' attribute to the memdev

 Documentation/ABI/testing/sysfs-bus-cxl         |  103 +++
 Documentation/driver-api/cxl/memory-devices.rst |   20 +-
 drivers/cxl/Kconfig                             |   43 +-
 drivers/cxl/Makefile                            |   12 +-
 drivers/cxl/acpi.c                              |  434 +++++++++
 drivers/cxl/bus.c                               |   29 -
 drivers/cxl/core.c                              | 1067 +++++++++++++++++++++++
 drivers/cxl/cxl.h                               |  332 +++++--
 drivers/cxl/mem.h                               |   81 ++
 drivers/cxl/{mem.c => pci.c}                    |  439 ++++++----
 drivers/cxl/pci.h                               |    2 +-
 drivers/cxl/pmem.c                              |  230 +++++
 drivers/nvdimm/bus.c                            |   64 +-
 drivers/nvdimm/dimm_devs.c                      |   18 +
 include/linux/libnvdimm.h                       |    1 +
 include/uapi/linux/cxl_mem.h                    |   12 +
 16 files changed, 2596 insertions(+), 291 deletions(-)
 create mode 100644 drivers/cxl/acpi.c
 delete mode 100644 drivers/cxl/bus.c
 create mode 100644 drivers/cxl/core.c
 create mode 100644 drivers/cxl/mem.h
 rename drivers/cxl/{mem.c => pci.c} (86%)
 create mode 100644 drivers/cxl/pmem.c

             reply	other threads:[~2021-07-03 15:08 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-03 15:08 Dan Williams [this message]
2021-07-04 20:09 ` [GIT PULL] Compute Express Link (CXL) update for v5.14 pr-tracker-bot

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