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From: Hao Peng <flyingpenghao@gmail.com>
To: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
Cc: tglx@linutronix.de, mingo@redhat.com,
	Borislav Petkov <bp@alien8.de>,
	x86@kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH] x86/tsx: clear RTM and HLE when MSR_IA32_TSX_CTRL is not supported
Date: Tue, 7 Sep 2021 14:36:21 +0800	[thread overview]
Message-ID: <CAPm50aLWUJZbgmvrt09S9LKowuH28NQpn7ZSuCkJGf_=jKFjXg@mail.gmail.com> (raw)
In-Reply-To: <20210907051454.56eocxfxeuqixlf6@gupta-dev2.localdomain>

On Tue, Sep 7, 2021 at 1:13 PM Pawan Gupta
<pawan.kumar.gupta@linux.intel.com> wrote:
>
> On 06.09.2021 10:46, Hao Peng wrote:
> >If hypervisor does not support MSR_IA32_TSX_CTRL, but guest supports
> >RTM and HLE features, it will affect TAA mitigation.
>
> Guests are on purpose not allowed to control TSX via MSR_IA32_TSX_CTRL,
> otherwise a malicious guest can enable TSX and attack host or other
> guests. The TAA mitigation within a guest is same as MDS i.e.
> micro-architectural buffer clear using VERW instruction. Support for
> VERW is added by the microcode update and enumerate by
> MSR_ARCH_CAP[MD_CLEAR] bit.
>
> >Signed-off-by: Peng Hao <flyingpeng@tencent.com>
> >---
> > arch/x86/kernel/cpu/tsx.c | 7 +++++++
> > 1 file changed, 7 insertions(+)
> >
> >diff --git a/arch/x86/kernel/cpu/tsx.c b/arch/x86/kernel/cpu/tsx.c
> >index 9c7a5f049292..5e852c14fef2 100644
> >--- a/arch/x86/kernel/cpu/tsx.c
> >+++ b/arch/x86/kernel/cpu/tsx.c
> >@@ -122,6 +122,13 @@ void __init tsx_init(void)
> >
> >        if (!tsx_ctrl_is_supported()) {
> >                tsx_ctrl_state = TSX_CTRL_NOT_SUPPORTED;
> >+
> >+               /* If hypervisor does not support MSR_IA32_TSX_CTRL emulation,
> >+                * but guest supports RTM and HLE features, it will affect TAA
> >+                * (tsx_async_abort)mitigation.
> >+                */
> >+               setup_clear_cpu_cap(X86_FEATURE_RTM);
> >+               setup_clear_cpu_cap(X86_FEATURE_HLE);
>
> This is not correct. TSX feature can exist without TSX_CTRL MSR.
> Moreover, clearing the cached bits with setup_clear_cpu_cap() doesn't
> disable the TSX feature in CPU.
>
After applying this patch, the output of
/sys/devices/system/cpu/vulnerabilities/tsx_async_abort
becomes “Mitigation: TSX disabled”.Do you mean that tsx is still
enabled in this case in guest?
I made a mistake in the description before. This problem occurred
under the qemu -cpu Icelake-server .
When I debug this problem to -cpu host, the guest can see taa-no.
Thanks.
> Thanks,
> Pawan

  reply	other threads:[~2021-09-07  6:36 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-06  2:46 [PATCH] x86/tsx: clear RTM and HLE when MSR_IA32_TSX_CTRL is not supported Hao Peng
2021-09-06  9:30 ` Borislav Petkov
2021-09-07  1:47   ` Hao Peng
2021-09-07  2:08     ` Xiaoyao Li
2021-09-07  2:35       ` Hao Peng
2021-09-07  2:56         ` Xiaoyao Li
2021-09-07  3:40           ` Hao Peng
2021-09-07  4:26             ` Xiaoyao Li
2021-09-07  4:39               ` Hao Peng
2021-09-07  5:38                 ` Pawan Gupta
2021-09-07  6:56                   ` Hao Peng
2021-09-07 23:07                     ` Pawan Gupta
2021-09-07  5:28           ` Pawan Gupta
2021-09-07  5:14 ` Pawan Gupta
2021-09-07  6:36   ` Hao Peng [this message]
2021-09-07 22:59     ` Pawan Gupta
2021-09-08  5:06       ` Hao Peng
2021-09-08 16:02         ` Pawan Gupta

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