* [PATCH] bus: mhi: pci_generic: Introduce Foxconn T99W175 support
@ 2021-04-07 2:50 Jarvis Jiang
2021-04-07 6:46 ` Manivannan Sadhasivam
2021-04-07 8:30 ` Loic Poulain
0 siblings, 2 replies; 5+ messages in thread
From: Jarvis Jiang @ 2021-04-07 2:50 UTC (permalink / raw)
To: mani, hemantk
Cc: linux-kernel, linux-arm-msm, cchen50, mpearson, Jarvis Jiang
Add support for T99W175 modems, this modem series is based on SDX55
qcom chip. The modem is mainly based on MBIM protocol for both the
data and control path.
This patch was tested with Ubuntu 20.04 X86_64 PC as host
Signed-off-by: Jarvis Jiang <jarvis.w.jiang@gmail.com>
---
drivers/bus/mhi/pci_generic.c | 58 +++++++++++++++++++++++++++++++++++
1 file changed, 58 insertions(+)
diff --git a/drivers/bus/mhi/pci_generic.c b/drivers/bus/mhi/pci_generic.c
index 5cf44bcfe040..3e396c65a758 100644
--- a/drivers/bus/mhi/pci_generic.c
+++ b/drivers/bus/mhi/pci_generic.c
@@ -260,6 +260,52 @@ static const struct mhi_pci_dev_info mhi_quectel_em1xx_info = {
.dma_data_width = 32
};
+static const struct mhi_channel_config mhi_foxconn_sdx55_channels[] = {
+ MHI_CHANNEL_CONFIG_UL(0, "LOOPBACK", 32, 0),
+ MHI_CHANNEL_CONFIG_DL(1, "LOOPBACK", 32, 0),
+ MHI_CHANNEL_CONFIG_UL(4, "DIAG", 32, 1),
+ MHI_CHANNEL_CONFIG_DL(5, "DIAG", 32, 1),
+ MHI_CHANNEL_CONFIG_UL(12, "MBIM", 32, 0),
+ MHI_CHANNEL_CONFIG_DL(13, "MBIM", 32, 0),
+ MHI_CHANNEL_CONFIG_UL(14, "QMI", 32, 0),
+ MHI_CHANNEL_CONFIG_DL(15, "QMI", 32, 0),
+ MHI_CHANNEL_CONFIG_UL(16, "QMI1", 32, 0),
+ MHI_CHANNEL_CONFIG_DL(17, "QMI1", 32, 0),
+ MHI_CHANNEL_CONFIG_UL(18, "IP_CTRL", 32, 0),
+ MHI_CHANNEL_CONFIG_DL(19, "IP_CTRL", 32, 0),
+ MHI_CHANNEL_CONFIG_UL(20, "IPCR", 32, 0),
+ MHI_CHANNEL_CONFIG_DL(21, "IPCR", 32, 0),
+ MHI_CHANNEL_CONFIG_UL(32, "AT", 32, 0),
+ MHI_CHANNEL_CONFIG_DL(33, "AT", 32, 0),
+ MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0_MBIM", 128, 2),
+ MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0_MBIM", 128, 3),
+};
+
+static struct mhi_event_config mhi_foxconn_sdx55_events[] = {
+ MHI_EVENT_CONFIG_CTRL(0, 128),
+ MHI_EVENT_CONFIG_DATA(1, 128),
+ MHI_EVENT_CONFIG_HW_DATA(2, 1024, 100),
+ MHI_EVENT_CONFIG_HW_DATA(3, 1024, 101)
+};
+
+static struct mhi_controller_config modem_foxconn_sdx55_config = {
+ .max_channels = 128,
+ .timeout_ms = 20000,
+ .num_channels = ARRAY_SIZE(mhi_foxconn_sdx55_channels),
+ .ch_cfg = mhi_foxconn_sdx55_channels,
+ .num_events = ARRAY_SIZE(mhi_foxconn_sdx55_events),
+ .event_cfg = mhi_foxconn_sdx55_events,
+};
+
+static const struct mhi_pci_dev_info mhi_foxconn_sdx55_info = {
+ .name = "foxconn-sdx55",
+ .fw = "qcom/sdx55m/sbl1.mbn",
+ .edl = "qcom/sdx55m/edl.mbn",
+ .config = &modem_foxconn_sdx55_config,
+ .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
+ .dma_data_width = 32
+};
+
static const struct pci_device_id mhi_pci_id_table[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0306),
.driver_data = (kernel_ulong_t) &mhi_qcom_sdx55_info },
@@ -269,6 +315,18 @@ static const struct pci_device_id mhi_pci_id_table[] = {
.driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info },
{ PCI_DEVICE(0x1eac, 0x1002), /* EM160R-GL (sdx24) */
.driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info },
+ { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0ab), /* T99W175 (sdx55) */
+ .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx55_info },
+ { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0b2), /* T99W175 (sdx55) */
+ .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx55_info },
+ { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0b3), /* T99W175 (sdx55) */
+ .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx55_info },
+ /* DW5930e (sdx55), With eSIM, It's also T99W175 */
+ { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0b0),
+ .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx55_info },
+ /* DW5930e (sdx55), Non-eSIM, It's also T99W175 */
+ { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0b1),
+ .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx55_info },
{ }
};
MODULE_DEVICE_TABLE(pci, mhi_pci_id_table);
--
2.25.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH] bus: mhi: pci_generic: Introduce Foxconn T99W175 support
2021-04-07 2:50 [PATCH] bus: mhi: pci_generic: Introduce Foxconn T99W175 support Jarvis Jiang
@ 2021-04-07 6:46 ` Manivannan Sadhasivam
2021-04-07 8:16 ` Jarvis Jiang
2021-04-07 8:30 ` Loic Poulain
1 sibling, 1 reply; 5+ messages in thread
From: Manivannan Sadhasivam @ 2021-04-07 6:46 UTC (permalink / raw)
To: Jarvis Jiang; +Cc: hemantk, linux-kernel, linux-arm-msm, cchen50, mpearson
On Tue, Apr 06, 2021 at 07:50:29PM -0700, Jarvis Jiang wrote:
> Add support for T99W175 modems, this modem series is based on SDX55
> qcom chip. The modem is mainly based on MBIM protocol for both the
> data and control path.
>
List the modems whose support is being added.
> This patch was tested with Ubuntu 20.04 X86_64 PC as host
>
> Signed-off-by: Jarvis Jiang <jarvis.w.jiang@gmail.com>
> ---
> drivers/bus/mhi/pci_generic.c | 58 +++++++++++++++++++++++++++++++++++
> 1 file changed, 58 insertions(+)
>
> diff --git a/drivers/bus/mhi/pci_generic.c b/drivers/bus/mhi/pci_generic.c
> index 5cf44bcfe040..3e396c65a758 100644
> --- a/drivers/bus/mhi/pci_generic.c
> +++ b/drivers/bus/mhi/pci_generic.c
> @@ -260,6 +260,52 @@ static const struct mhi_pci_dev_info mhi_quectel_em1xx_info = {
> .dma_data_width = 32
> };
>
> +static const struct mhi_channel_config mhi_foxconn_sdx55_channels[] = {
> + MHI_CHANNEL_CONFIG_UL(0, "LOOPBACK", 32, 0),
> + MHI_CHANNEL_CONFIG_DL(1, "LOOPBACK", 32, 0),
> + MHI_CHANNEL_CONFIG_UL(4, "DIAG", 32, 1),
> + MHI_CHANNEL_CONFIG_DL(5, "DIAG", 32, 1),
> + MHI_CHANNEL_CONFIG_UL(12, "MBIM", 32, 0),
> + MHI_CHANNEL_CONFIG_DL(13, "MBIM", 32, 0),
> + MHI_CHANNEL_CONFIG_UL(14, "QMI", 32, 0),
> + MHI_CHANNEL_CONFIG_DL(15, "QMI", 32, 0),
> + MHI_CHANNEL_CONFIG_UL(16, "QMI1", 32, 0),
> + MHI_CHANNEL_CONFIG_DL(17, "QMI1", 32, 0),
> + MHI_CHANNEL_CONFIG_UL(18, "IP_CTRL", 32, 0),
> + MHI_CHANNEL_CONFIG_DL(19, "IP_CTRL", 32, 0),
> + MHI_CHANNEL_CONFIG_UL(20, "IPCR", 32, 0),
> + MHI_CHANNEL_CONFIG_DL(21, "IPCR", 32, 0),
> + MHI_CHANNEL_CONFIG_UL(32, "AT", 32, 0),
> + MHI_CHANNEL_CONFIG_DL(33, "AT", 32, 0),
> + MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0_MBIM", 128, 2),
> + MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0_MBIM", 128, 3),
> +};
> +
> +static struct mhi_event_config mhi_foxconn_sdx55_events[] = {
> + MHI_EVENT_CONFIG_CTRL(0, 128),
> + MHI_EVENT_CONFIG_DATA(1, 128),
> + MHI_EVENT_CONFIG_HW_DATA(2, 1024, 100),
> + MHI_EVENT_CONFIG_HW_DATA(3, 1024, 101)
> +};
> +
> +static struct mhi_controller_config modem_foxconn_sdx55_config = {
> + .max_channels = 128,
> + .timeout_ms = 20000,
> + .num_channels = ARRAY_SIZE(mhi_foxconn_sdx55_channels),
> + .ch_cfg = mhi_foxconn_sdx55_channels,
> + .num_events = ARRAY_SIZE(mhi_foxconn_sdx55_events),
> + .event_cfg = mhi_foxconn_sdx55_events,
> +};
> +
> +static const struct mhi_pci_dev_info mhi_foxconn_sdx55_info = {
> + .name = "foxconn-sdx55",
> + .fw = "qcom/sdx55m/sbl1.mbn",
> + .edl = "qcom/sdx55m/edl.mbn",
> + .config = &modem_foxconn_sdx55_config,
> + .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
> + .dma_data_width = 32
> +};
> +
> static const struct pci_device_id mhi_pci_id_table[] = {
> { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0306),
> .driver_data = (kernel_ulong_t) &mhi_qcom_sdx55_info },
> @@ -269,6 +315,18 @@ static const struct pci_device_id mhi_pci_id_table[] = {
> .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info },
> { PCI_DEVICE(0x1eac, 0x1002), /* EM160R-GL (sdx24) */
> .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info },
> + { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0ab), /* T99W175 (sdx55) */
> + .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx55_info },
> + { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0b2), /* T99W175 (sdx55) */
> + .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx55_info },
> + { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0b3), /* T99W175 (sdx55) */
> + .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx55_info },
Please add a comment about these devices as you did below. Using T99W175 (sdx55)
for all is not sufficient.
Thanks,
Mani
> + /* DW5930e (sdx55), With eSIM, It's also T99W175 */
> + { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0b0),
> + .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx55_info },
> + /* DW5930e (sdx55), Non-eSIM, It's also T99W175 */
> + { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0b1),
> + .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx55_info },
> { }
> };
> MODULE_DEVICE_TABLE(pci, mhi_pci_id_table);
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] bus: mhi: pci_generic: Introduce Foxconn T99W175 support
2021-04-07 6:46 ` Manivannan Sadhasivam
@ 2021-04-07 8:16 ` Jarvis Jiang
0 siblings, 0 replies; 5+ messages in thread
From: Jarvis Jiang @ 2021-04-07 8:16 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: hemantk, linux-kernel, linux-arm-msm, cchen50, mpearson
On Wed, Apr 7, 2021 at 2:46 PM Manivannan Sadhasivam <mani@kernel.org> wrote:
>
> On Tue, Apr 06, 2021 at 07:50:29PM -0700, Jarvis Jiang wrote:
> > Add support for T99W175 modems, this modem series is based on SDX55
> > qcom chip. The modem is mainly based on MBIM protocol for both the
> > data and control path.
> >
>
> List the modems whose support is being added.
Ok, I will add the modems supported in the next iteration.
>
> > This patch was tested with Ubuntu 20.04 X86_64 PC as host
> >
> > Signed-off-by: Jarvis Jiang <jarvis.w.jiang@gmail.com>
> > ---
> > drivers/bus/mhi/pci_generic.c | 58 +++++++++++++++++++++++++++++++++++
> > 1 file changed, 58 insertions(+)
> >
> > diff --git a/drivers/bus/mhi/pci_generic.c b/drivers/bus/mhi/pci_generic.c
> > index 5cf44bcfe040..3e396c65a758 100644
> > --- a/drivers/bus/mhi/pci_generic.c
> > +++ b/drivers/bus/mhi/pci_generic.c
> > @@ -260,6 +260,52 @@ static const struct mhi_pci_dev_info mhi_quectel_em1xx_info = {
> > .dma_data_width = 32
> > };
> >
> > +static const struct mhi_channel_config mhi_foxconn_sdx55_channels[] = {
> > + MHI_CHANNEL_CONFIG_UL(0, "LOOPBACK", 32, 0),
> > + MHI_CHANNEL_CONFIG_DL(1, "LOOPBACK", 32, 0),
> > + MHI_CHANNEL_CONFIG_UL(4, "DIAG", 32, 1),
> > + MHI_CHANNEL_CONFIG_DL(5, "DIAG", 32, 1),
> > + MHI_CHANNEL_CONFIG_UL(12, "MBIM", 32, 0),
> > + MHI_CHANNEL_CONFIG_DL(13, "MBIM", 32, 0),
> > + MHI_CHANNEL_CONFIG_UL(14, "QMI", 32, 0),
> > + MHI_CHANNEL_CONFIG_DL(15, "QMI", 32, 0),
> > + MHI_CHANNEL_CONFIG_UL(16, "QMI1", 32, 0),
> > + MHI_CHANNEL_CONFIG_DL(17, "QMI1", 32, 0),
> > + MHI_CHANNEL_CONFIG_UL(18, "IP_CTRL", 32, 0),
> > + MHI_CHANNEL_CONFIG_DL(19, "IP_CTRL", 32, 0),
> > + MHI_CHANNEL_CONFIG_UL(20, "IPCR", 32, 0),
> > + MHI_CHANNEL_CONFIG_DL(21, "IPCR", 32, 0),
> > + MHI_CHANNEL_CONFIG_UL(32, "AT", 32, 0),
> > + MHI_CHANNEL_CONFIG_DL(33, "AT", 32, 0),
> > + MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0_MBIM", 128, 2),
> > + MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0_MBIM", 128, 3),
> > +};
> > +
> > +static struct mhi_event_config mhi_foxconn_sdx55_events[] = {
> > + MHI_EVENT_CONFIG_CTRL(0, 128),
> > + MHI_EVENT_CONFIG_DATA(1, 128),
> > + MHI_EVENT_CONFIG_HW_DATA(2, 1024, 100),
> > + MHI_EVENT_CONFIG_HW_DATA(3, 1024, 101)
> > +};
> > +
> > +static struct mhi_controller_config modem_foxconn_sdx55_config = {
> > + .max_channels = 128,
> > + .timeout_ms = 20000,
> > + .num_channels = ARRAY_SIZE(mhi_foxconn_sdx55_channels),
> > + .ch_cfg = mhi_foxconn_sdx55_channels,
> > + .num_events = ARRAY_SIZE(mhi_foxconn_sdx55_events),
> > + .event_cfg = mhi_foxconn_sdx55_events,
> > +};
> > +
> > +static const struct mhi_pci_dev_info mhi_foxconn_sdx55_info = {
> > + .name = "foxconn-sdx55",
> > + .fw = "qcom/sdx55m/sbl1.mbn",
> > + .edl = "qcom/sdx55m/edl.mbn",
> > + .config = &modem_foxconn_sdx55_config,
> > + .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
> > + .dma_data_width = 32
> > +};
> > +
> > static const struct pci_device_id mhi_pci_id_table[] = {
> > { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0306),
> > .driver_data = (kernel_ulong_t) &mhi_qcom_sdx55_info },
> > @@ -269,6 +315,18 @@ static const struct pci_device_id mhi_pci_id_table[] = {
> > .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info },
> > { PCI_DEVICE(0x1eac, 0x1002), /* EM160R-GL (sdx24) */
> > .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info },
> > + { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0ab), /* T99W175 (sdx55) */
> > + .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx55_info },
> > + { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0b2), /* T99W175 (sdx55) */
> > + .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx55_info },
> > + { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0b3), /* T99W175 (sdx55) */
> > + .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx55_info },
>
> Please add a comment about these devices as you did below. Using T99W175 (sdx55)
> for all is not sufficient.
>
> Thanks,
> Mani
>
Ok, thanks, I will give more comments in the next patch.
Jarvis.
> > + /* DW5930e (sdx55), With eSIM, It's also T99W175 */
> > + { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0b0),
> > + .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx55_info },
> > + /* DW5930e (sdx55), Non-eSIM, It's also T99W175 */
> > + { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0b1),
> > + .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx55_info },
> > { }
> > };
> > MODULE_DEVICE_TABLE(pci, mhi_pci_id_table);
> > --
> > 2.25.1
> >
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] bus: mhi: pci_generic: Introduce Foxconn T99W175 support
2021-04-07 2:50 [PATCH] bus: mhi: pci_generic: Introduce Foxconn T99W175 support Jarvis Jiang
2021-04-07 6:46 ` Manivannan Sadhasivam
@ 2021-04-07 8:30 ` Loic Poulain
2021-04-08 6:10 ` Jarvis Jiang
1 sibling, 1 reply; 5+ messages in thread
From: Loic Poulain @ 2021-04-07 8:30 UTC (permalink / raw)
To: Jarvis Jiang
Cc: Manivannan Sadhasivam, Hemant Kumar, open list, linux-arm-msm,
cchen50, mpearson
Hi Jarvis,
On Wed, 7 Apr 2021 at 04:51, Jarvis Jiang <jarvis.w.jiang@gmail.com> wrote:
>
> Add support for T99W175 modems, this modem series is based on SDX55
> qcom chip. The modem is mainly based on MBIM protocol for both the
> data and control path.
>
> This patch was tested with Ubuntu 20.04 X86_64 PC as host
>
> Signed-off-by: Jarvis Jiang <jarvis.w.jiang@gmail.com>
> ---
> drivers/bus/mhi/pci_generic.c | 58 +++++++++++++++++++++++++++++++++++
> 1 file changed, 58 insertions(+)
>
> diff --git a/drivers/bus/mhi/pci_generic.c b/drivers/bus/mhi/pci_generic.c
> index 5cf44bcfe040..3e396c65a758 100644
> --- a/drivers/bus/mhi/pci_generic.c
> +++ b/drivers/bus/mhi/pci_generic.c
> @@ -260,6 +260,52 @@ static const struct mhi_pci_dev_info mhi_quectel_em1xx_info = {
> .dma_data_width = 32
> };
>
> +static const struct mhi_channel_config mhi_foxconn_sdx55_channels[] = {
> + MHI_CHANNEL_CONFIG_UL(0, "LOOPBACK", 32, 0),
> + MHI_CHANNEL_CONFIG_DL(1, "LOOPBACK", 32, 0),
> + MHI_CHANNEL_CONFIG_UL(4, "DIAG", 32, 1),
> + MHI_CHANNEL_CONFIG_DL(5, "DIAG", 32, 1),
> + MHI_CHANNEL_CONFIG_UL(12, "MBIM", 32, 0),
> + MHI_CHANNEL_CONFIG_DL(13, "MBIM", 32, 0),
> + MHI_CHANNEL_CONFIG_UL(14, "QMI", 32, 0),
> + MHI_CHANNEL_CONFIG_DL(15, "QMI", 32, 0),
> + MHI_CHANNEL_CONFIG_UL(16, "QMI1", 32, 0),
> + MHI_CHANNEL_CONFIG_DL(17, "QMI1", 32, 0),
Are these QMI channels need to be exposed, vendors usually expose
either QMI+QMAP or MBIM (for data and control), here you expose
IP_HW0_MBIM as 'data' channel, so I would expect that MBIM is all you
need for the 'control' channel.
> + MHI_CHANNEL_CONFIG_UL(18, "IP_CTRL", 32, 0),
> + MHI_CHANNEL_CONFIG_DL(19, "IP_CTRL", 32, 0),
> + MHI_CHANNEL_CONFIG_UL(20, "IPCR", 32, 0),
> + MHI_CHANNEL_CONFIG_DL(21, "IPCR", 32, 0),
> + MHI_CHANNEL_CONFIG_UL(32, "AT", 32, 0),
> + MHI_CHANNEL_CONFIG_DL(33, "AT", 32, 0),
> + MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0_MBIM", 128, 2),
> + MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0_MBIM", 128, 3),
> +};
> +
> +static struct mhi_event_config mhi_foxconn_sdx55_events[] = {
> + MHI_EVENT_CONFIG_CTRL(0, 128),
> + MHI_EVENT_CONFIG_DATA(1, 128),
> + MHI_EVENT_CONFIG_HW_DATA(2, 1024, 100),
> + MHI_EVENT_CONFIG_HW_DATA(3, 1024, 101)
> +};
> +
> +static struct mhi_controller_config modem_foxconn_sdx55_config = {
> + .max_channels = 128,
> + .timeout_ms = 20000,
> + .num_channels = ARRAY_SIZE(mhi_foxconn_sdx55_channels),
> + .ch_cfg = mhi_foxconn_sdx55_channels,
> + .num_events = ARRAY_SIZE(mhi_foxconn_sdx55_events),
> + .event_cfg = mhi_foxconn_sdx55_events,
> +};
> +
> +static const struct mhi_pci_dev_info mhi_foxconn_sdx55_info = {
> + .name = "foxconn-sdx55",
> + .fw = "qcom/sdx55m/sbl1.mbn",
> + .edl = "qcom/sdx55m/edl.mbn",
> + .config = &modem_foxconn_sdx55_config,
> + .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
> + .dma_data_width = 32
> +};
> +
> static const struct pci_device_id mhi_pci_id_table[] = {
> { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0306),
> .driver_data = (kernel_ulong_t) &mhi_qcom_sdx55_info },
> @@ -269,6 +315,18 @@ static const struct pci_device_id mhi_pci_id_table[] = {
> .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info },
> { PCI_DEVICE(0x1eac, 0x1002), /* EM160R-GL (sdx24) */
> .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info },
> + { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0ab), /* T99W175 (sdx55) */
> + .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx55_info },
> + { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0b2), /* T99W175 (sdx55) */
> + .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx55_info },
> + { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0b3), /* T99W175 (sdx55) */
> + .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx55_info },
> + /* DW5930e (sdx55), With eSIM, It's also T99W175 */
> + { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0b0),
> + .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx55_info },
> + /* DW5930e (sdx55), Non-eSIM, It's also T99W175 */
> + { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0b1),
> + .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx55_info },
> { }
> };
> MODULE_DEVICE_TABLE(pci, mhi_pci_id_table);
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] bus: mhi: pci_generic: Introduce Foxconn T99W175 support
2021-04-07 8:30 ` Loic Poulain
@ 2021-04-08 6:10 ` Jarvis Jiang
0 siblings, 0 replies; 5+ messages in thread
From: Jarvis Jiang @ 2021-04-08 6:10 UTC (permalink / raw)
To: Loic Poulain
Cc: Manivannan Sadhasivam, Hemant Kumar, open list, linux-arm-msm,
cchen50, mpearson
On Wed, Apr 7, 2021 at 4:22 PM Loic Poulain <loic.poulain@linaro.org> wrote:
>
> Hi Jarvis,
>
> On Wed, 7 Apr 2021 at 04:51, Jarvis Jiang <jarvis.w.jiang@gmail.com> wrote:
> >
> > Add support for T99W175 modems, this modem series is based on SDX55
> > qcom chip. The modem is mainly based on MBIM protocol for both the
> > data and control path.
> >
> > This patch was tested with Ubuntu 20.04 X86_64 PC as host
> >
> > Signed-off-by: Jarvis Jiang <jarvis.w.jiang@gmail.com>
> > ---
> > drivers/bus/mhi/pci_generic.c | 58 +++++++++++++++++++++++++++++++++++
> > 1 file changed, 58 insertions(+)
> >
> > diff --git a/drivers/bus/mhi/pci_generic.c b/drivers/bus/mhi/pci_generic.c
> > index 5cf44bcfe040..3e396c65a758 100644
> > --- a/drivers/bus/mhi/pci_generic.c
> > +++ b/drivers/bus/mhi/pci_generic.c
> > @@ -260,6 +260,52 @@ static const struct mhi_pci_dev_info mhi_quectel_em1xx_info = {
> > .dma_data_width = 32
> > };
> >
> > +static const struct mhi_channel_config mhi_foxconn_sdx55_channels[] = {
> > + MHI_CHANNEL_CONFIG_UL(0, "LOOPBACK", 32, 0),
> > + MHI_CHANNEL_CONFIG_DL(1, "LOOPBACK", 32, 0),
> > + MHI_CHANNEL_CONFIG_UL(4, "DIAG", 32, 1),
> > + MHI_CHANNEL_CONFIG_DL(5, "DIAG", 32, 1),
> > + MHI_CHANNEL_CONFIG_UL(12, "MBIM", 32, 0),
> > + MHI_CHANNEL_CONFIG_DL(13, "MBIM", 32, 0),
> > + MHI_CHANNEL_CONFIG_UL(14, "QMI", 32, 0),
> > + MHI_CHANNEL_CONFIG_DL(15, "QMI", 32, 0),
> > + MHI_CHANNEL_CONFIG_UL(16, "QMI1", 32, 0),
> > + MHI_CHANNEL_CONFIG_DL(17, "QMI1", 32, 0),
>
> Are these QMI channels need to be exposed, vendors usually expose
> either QMI+QMAP or MBIM (for data and control), here you expose
> IP_HW0_MBIM as 'data' channel, so I would expect that MBIM is all you
> need for the 'control' channel.
Yes, the unnecessary channels will be removed in the next patch.
Thanks,
Jarvis
>
> > + MHI_CHANNEL_CONFIG_UL(18, "IP_CTRL", 32, 0),
> > + MHI_CHANNEL_CONFIG_DL(19, "IP_CTRL", 32, 0),
> > + MHI_CHANNEL_CONFIG_UL(20, "IPCR", 32, 0),
> > + MHI_CHANNEL_CONFIG_DL(21, "IPCR", 32, 0),
> > + MHI_CHANNEL_CONFIG_UL(32, "AT", 32, 0),
> > + MHI_CHANNEL_CONFIG_DL(33, "AT", 32, 0),
> > + MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0_MBIM", 128, 2),
> > + MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0_MBIM", 128, 3),
> > +};
> > +
> > +static struct mhi_event_config mhi_foxconn_sdx55_events[] = {
> > + MHI_EVENT_CONFIG_CTRL(0, 128),
> > + MHI_EVENT_CONFIG_DATA(1, 128),
> > + MHI_EVENT_CONFIG_HW_DATA(2, 1024, 100),
> > + MHI_EVENT_CONFIG_HW_DATA(3, 1024, 101)
> > +};
> > +
> > +static struct mhi_controller_config modem_foxconn_sdx55_config = {
> > + .max_channels = 128,
> > + .timeout_ms = 20000,
> > + .num_channels = ARRAY_SIZE(mhi_foxconn_sdx55_channels),
> > + .ch_cfg = mhi_foxconn_sdx55_channels,
> > + .num_events = ARRAY_SIZE(mhi_foxconn_sdx55_events),
> > + .event_cfg = mhi_foxconn_sdx55_events,
> > +};
> > +
> > +static const struct mhi_pci_dev_info mhi_foxconn_sdx55_info = {
> > + .name = "foxconn-sdx55",
> > + .fw = "qcom/sdx55m/sbl1.mbn",
> > + .edl = "qcom/sdx55m/edl.mbn",
> > + .config = &modem_foxconn_sdx55_config,
> > + .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
> > + .dma_data_width = 32
> > +};
> > +
> > static const struct pci_device_id mhi_pci_id_table[] = {
> > { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0306),
> > .driver_data = (kernel_ulong_t) &mhi_qcom_sdx55_info },
> > @@ -269,6 +315,18 @@ static const struct pci_device_id mhi_pci_id_table[] = {
> > .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info },
> > { PCI_DEVICE(0x1eac, 0x1002), /* EM160R-GL (sdx24) */
> > .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info },
> > + { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0ab), /* T99W175 (sdx55) */
> > + .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx55_info },
> > + { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0b2), /* T99W175 (sdx55) */
> > + .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx55_info },
> > + { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0b3), /* T99W175 (sdx55) */
> > + .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx55_info },
> > + /* DW5930e (sdx55), With eSIM, It's also T99W175 */
> > + { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0b0),
> > + .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx55_info },
> > + /* DW5930e (sdx55), Non-eSIM, It's also T99W175 */
> > + { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0b1),
> > + .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx55_info },
> > { }
> > };
> > MODULE_DEVICE_TABLE(pci, mhi_pci_id_table);
> > --
> > 2.25.1
> >
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2021-04-08 6:10 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-04-07 2:50 [PATCH] bus: mhi: pci_generic: Introduce Foxconn T99W175 support Jarvis Jiang
2021-04-07 6:46 ` Manivannan Sadhasivam
2021-04-07 8:16 ` Jarvis Jiang
2021-04-07 8:30 ` Loic Poulain
2021-04-08 6:10 ` Jarvis Jiang
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).