From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752566AbdARPrO (ORCPT ); Wed, 18 Jan 2017 10:47:14 -0500 Received: from mail-wj0-f194.google.com ([209.85.210.194]:33619 "EHLO mail-wj0-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751992AbdARPq7 (ORCPT ); Wed, 18 Jan 2017 10:46:59 -0500 MIME-Version: 1.0 In-Reply-To: <5ad3cedd-35c3-42c5-010c-dc8311905abc@wedev4u.fr> References: <20161202113144.17970-1-ricardo.ribalda@gmail.com> <5ad3cedd-35c3-42c5-010c-dc8311905abc@wedev4u.fr> From: Ricardo Ribalda Delgado Date: Wed, 18 Jan 2017 16:46:34 +0100 Message-ID: Subject: Re: [PATCH v9] mtd: spi-nor: Add support for S3AN spi-nor devices To: Cyrille Pitchen Cc: Marek Vasut , Cyrille Pitchen , David Woodhouse , Brian Norris , Boris Brezillon , Richard Weinberger , "linux-mtd@lists.infradead.org" , LKML Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from quoted-printable to 8bit by mail.home.local id v0IFlbpK012937 Hi Cyrille I have found a bug on the way the address is generated in special mode. Do you prefer a v9 of this patch or a patch? Regards! On Tue, Dec 13, 2016 at 5:30 PM, Cyrille Pitchen wrote: > Le 13/12/2016 à 08:53, Marek Vasut a écrit : >> On 12/02/2016 12:31 PM, Ricardo Ribalda Delgado wrote: >>> Xilinx Spartan-3AN FPGAs contain an In-System Flash where they keep >>> their configuration data and (optionally) some user data. >>> >>> The protocol of this flash follows most of the spi-nor standard. With >>> the following differences: >>> >>> - Page size might not be a power of two. >>> - The address calculation (default addressing mode). >>> - The spi nor commands used. >>> >>> Protocol is described on Xilinx User Guide UG333 >>> >>> Reviewed-by: Cyrille Pitchen >>> Signed-off-by: Ricardo Ribalda Delgado >>> Cc: Boris Brezillon >>> Cc: Brian Norris >>> Cc: Marek Vasut >> >> [...] >> >>> +static int s3an_nor_scan(const struct flash_info *info, struct spi_nor *nor) >>> +{ >>> + int ret; >>> + u8 val; >>> + >>> + ret = nor->read_reg(nor, SPINOR_OP_XRDSR, &val, 1); >>> + if (ret < 0) { >>> + dev_err(nor->dev, "error %d reading XRDSR\n", (int) ret); >>> + return ret; >>> + } >>> + >>> + nor->erase_opcode = SPINOR_OP_XSE; >>> + nor->program_opcode = SPINOR_OP_XPP; >>> + nor->read_opcode = SPINOR_OP_READ; >>> + nor->flags |= SNOR_F_NO_OP_CHIP_ERASE ; >> >> NIT: You have an extra space before ; ^ >> >>> + >>> + /* >>> + * This flashes have a page size of 264 or 528 bytes (known as >>> + * Default addressing mode). It can be changed to a more standard >>> + * Power of two mode where the page size is 256/512. This comes >>> + * with a price: there is 3% less of space, the data is corrupted >>> + * and the page size cannot be changed back to default addressing >>> + * mode. >>> + * >>> + * The current addressing mode can be read from the XRDSR register >>> + * and should not be changed, because is a destructive operation. >>> + */ >>> + if (val & XSR_PAGESIZE) { >>> + /* Flash in Power of 2 mode */ >>> + nor->page_size = (nor->page_size == 264) ? 256 : 512; >>> + nor->mtd.writebufsize = nor->page_size; >>> + nor->mtd.size = 8 * nor->page_size * info->n_sectors; >>> + nor->mtd.erasesize = 8 * nor->page_size; >>> + } else { >>> + /* Flash in Default addressing mode */ >>> + nor->flags |= SNOR_F_S3AN_ADDR_DEFAULT; >>> + } >>> + >>> + return 0; >>> +} >> >> Looks great otherwise: >> Reviewed-by: Marek Vasut >> > Applied to git://github.com/spi-nor/linux.git > > I've removed the additional SPACE before ';' as reported by Marek. > > Thanks! -- Ricardo Ribalda