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([fe80::c0b:d777:b62d:9a5%7]) with mapi id 15.20.2347.028; Mon, 21 Oct 2019 08:40:01 +0000 From: Gustavo Pimentel To: Dilip Kota , "jingoohan1@gmail.com" , "gustavo.pimentel@synopsys.com" , "lorenzo.pieralisi@arm.com" , "andrew.murray@arm.com" , "robh@kernel.org" , "martin.blumenstingl@googlemail.com" , "linux-pci@vger.kernel.org" , "hch@infradead.org" , "devicetree@vger.kernel.org" CC: "linux-kernel@vger.kernel.org" , "andriy.shevchenko@intel.com" , "cheol.yong.kim@intel.com" , "chuanhua.lei@linux.intel.com" , "qi-ming.wu@intel.com" Subject: RE: [PATCH v4 3/3] pci: intel: Add sysfs attributes to configure pcie link Thread-Topic: [PATCH v4 3/3] pci: intel: Add sysfs attributes to configure pcie link Thread-Index: AQHVh9pkg5qa2l7qKkufp5bM7YjXW6dkxV8w Date: Mon, 21 Oct 2019 08:40:01 +0000 Message-ID: References: In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-dg-ref: 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VB0Zq+tUX37tQzbdfxkVRjtgwVNHz2M6LCcxnZe31gNlQ2SiNKaNt4qc+1KADzvFUy4oS79NZQXTRdCo7prUReQftVuzX9pwonSMrhhdvRGmCGsCzjbduknqJSaENJh93Nzg9DtKzq62yteIcoQypseYnpHWlxoY4JFmG7Sh2PhC2DhU75GdtuNSmJNTmyVgN5NT/10G2vqyWsBN7R2ncC3ePQT5K/jbFepY17wE0pyZS95xHtzsgVSbJaGVG1ZpYNxjzDMkh2LXu27AAyu8rV7wFxfUywPXa7Dg07pYVeWpblbLZyj7zngAftu86Z+XeRUnUrcg7d+oeg3r93qyjAhFJZUumdkoBUTNQ+5P14VtWhq5x3eq7A9puPwElmnrbnF50c/NlBGVv2ya84IHWoaj3YvrWRPrFbxXVLQvAps= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: 004be349-487d-4d0e-53ed-08d756024362 X-MS-Exchange-CrossTenant-originalarrivaltime: 21 Oct 2019 08:40:01.5146 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: c33c9f88-1eb7-4099-9700-16013fd9e8aa X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: LHI/zRvB5ym40rJlcGBP11ppr66qVdlxEilvzhwhuEpCfv9QHzVTk32bHKGOPbni6Mg/gQI1tTYgBFZ83PjSrQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB3926 X-OriginatorOrg: synopsys.com Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Oct 21, 2019 at 7:39:20, Dilip Kota =20 wrote: > PCIe RC driver on Intel Gateway SoCs have a requirement > of changing link width and speed on the fly. > So add the sysfs attributes to show and store the link > properties. > Add the respective link resize function in pcie DesignWare > framework so that Intel PCIe driver can use during link > width configuration on the fly. >=20 > Signed-off-by: Dilip Kota > --- > drivers/pci/controller/dwc/pcie-designware.c | 9 +++ > drivers/pci/controller/dwc/pcie-designware.h | 3 + > drivers/pci/controller/dwc/pcie-intel-gw.c | 112 +++++++++++++++++++++= +++++- > 3 files changed, 123 insertions(+), 1 deletion(-) >=20 > diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/c= ontroller/dwc/pcie-designware.c > index 4c391bfd681a..662fdcb4f2d6 100644 > --- a/drivers/pci/controller/dwc/pcie-designware.c > +++ b/drivers/pci/controller/dwc/pcie-designware.c > @@ -474,6 +474,15 @@ int dw_pcie_link_up(struct dw_pcie *pci) > (!(val & PCIE_PORT_DEBUG1_LINK_IN_TRAINING))); > } > =20 > +void dw_pcie_link_width_resize(struct dw_pcie *pci, u32 lane_width) > +{ > + u32 val; > + > + val =3D dw_pcie_readl_dbi(pci, PCIE_PORT_MULTI_LANE_CTRL); > + val &=3D ~(PORT_MLTI_LNK_WDTH_CHNG | PORT_MLTI_LNK_WDTH); > + val |=3D PORT_MLTI_LNK_WDTH_CHNG | lane_width; > + dw_pcie_writel_dbi(pci, PCIE_PORT_MULTI_LANE_CTRL, val); > +} > =20 > void dw_pcie_upconfig_setup(struct dw_pcie *pci) > { > diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/c= ontroller/dwc/pcie-designware.h > index 3beac10e4a4c..fcf0442341fd 100644 > --- a/drivers/pci/controller/dwc/pcie-designware.h > +++ b/drivers/pci/controller/dwc/pcie-designware.h > @@ -67,6 +67,8 @@ > #define PCIE_MSI_INTR0_STATUS 0x830 > =20 > #define PCIE_PORT_MULTI_LANE_CTRL 0x8C0 > +#define PORT_MLTI_LNK_WDTH GENMASK(5, 0) > +#define PORT_MLTI_LNK_WDTH_CHNG BIT(6) > #define PORT_MLTI_UPCFG_SUPPORT BIT(7) > =20 > #define PCIE_ATU_VIEWPORT 0x900 > @@ -282,6 +284,7 @@ void dw_pcie_write_dbi2(struct dw_pcie *pci, u32 reg,= size_t size, u32 val); > u32 dw_pcie_read_atu(struct dw_pcie *pci, u32 reg, size_t size); > void dw_pcie_write_atu(struct dw_pcie *pci, u32 reg, size_t size, u32 va= l); > int dw_pcie_link_up(struct dw_pcie *pci); > +void dw_pcie_link_width_resize(struct dw_pcie *pci, u32 lane_width); > void dw_pcie_upconfig_setup(struct dw_pcie *pci); > void dw_pcie_link_speed_change(struct dw_pcie *pci, bool enable); > void dw_pcie_link_set_n_fts(struct dw_pcie *pci, u32 n_fts); > diff --git a/drivers/pci/controller/dwc/pcie-intel-gw.c b/drivers/pci/con= troller/dwc/pcie-intel-gw.c > index 9142c70db808..b9be0921671d 100644 > --- a/drivers/pci/controller/dwc/pcie-intel-gw.c > +++ b/drivers/pci/controller/dwc/pcie-intel-gw.c > @@ -146,6 +146,22 @@ static void intel_pcie_ltssm_disable(struct intel_pc= ie_port *lpp) > pcie_app_wr_mask(lpp, PCIE_APP_CCR_LTSSM_ENABLE, 0, PCIE_APP_CCR); > } > =20 > +static const char *pcie_link_gen_to_str(int gen) > +{ > + switch (gen) { > + case PCIE_LINK_SPEED_GEN1: > + return "2.5"; > + case PCIE_LINK_SPEED_GEN2: > + return "5.0"; > + case PCIE_LINK_SPEED_GEN3: > + return "8.0"; > + case PCIE_LINK_SPEED_GEN4: > + return "16.0"; > + default: > + return "???"; > + } > +} > + > static void intel_pcie_link_setup(struct intel_pcie_port *lpp) > { > u32 val; > @@ -444,6 +460,91 @@ static int intel_pcie_host_setup(struct intel_pcie_p= ort *lpp) > return ret; > } > =20 > +static ssize_t pcie_link_status_show(struct device *dev, > + struct device_attribute *attr, char *buf) > +{ > + struct intel_pcie_port *lpp =3D dev_get_drvdata(dev); > + u32 reg, width, gen; > + > + reg =3D pcie_rc_cfg_rd(lpp, PCIE_CAP_OFST + PCI_EXP_LNKCTL); > + width =3D FIELD_GET(PCI_EXP_LNKSTA_NLW, reg >> 16); > + gen =3D FIELD_GET(PCI_EXP_LNKSTA_CLS, reg >> 16); > + > + if (gen > lpp->max_speed) > + return -EINVAL; > + > + return sprintf(buf, "Port %2u Width x%u Speed %s GT/s\n", lpp->id, > + width, pcie_link_gen_to_str(gen)); > +} > +static DEVICE_ATTR_RO(pcie_link_status); Dilip please check pci.h there are there already enums and strings=20 relatively to PCIe speed and width, that you can use. > + > +static ssize_t pcie_speed_store(struct device *dev, > + struct device_attribute *attr, > + const char *buf, size_t len) > +{ > + struct intel_pcie_port *lpp =3D dev_get_drvdata(dev); > + unsigned long val; > + int ret; > + > + ret =3D kstrtoul(buf, 10, &val); > + if (ret) > + return ret; > + > + if (val > lpp->max_speed) > + return -EINVAL; > + > + lpp->link_gen =3D val; > + intel_pcie_max_speed_setup(lpp); > + dw_pcie_link_speed_change(&lpp->pci, false); > + dw_pcie_link_speed_change(&lpp->pci, true); > + > + return len; > +} > +static DEVICE_ATTR_WO(pcie_speed); > + > +/* > + * Link width change on the fly is not always successful. > + * It also depends on the partner. > + */ > +static ssize_t pcie_width_store(struct device *dev, > + struct device_attribute *attr, > + const char *buf, size_t len) > +{ > + struct intel_pcie_port *lpp =3D dev_get_drvdata(dev); > + unsigned long val; > + int ret; > + > + lpp =3D dev_get_drvdata(dev); > + > + ret =3D kstrtoul(buf, 10, &val); > + if (ret) > + return ret; > + > + if (val > lpp->max_width) > + return -EINVAL; > + > + /* HW auto bandwidth negotiation must be enabled */ > + pcie_rc_cfg_wr_mask(lpp, PCI_EXP_LNKCTL_HAWD, 0, > + PCIE_CAP_OFST + PCI_EXP_LNKCTL); > + dw_pcie_link_width_resize(&lpp->pci, val); > + > + return len; > +} > +static DEVICE_ATTR_WO(pcie_width); > + > +static struct attribute *pcie_cfg_attrs[] =3D { > + &dev_attr_pcie_link_status.attr, > + &dev_attr_pcie_speed.attr, > + &dev_attr_pcie_width.attr, > + NULL, > +}; > +ATTRIBUTE_GROUPS(pcie_cfg); > + > +static int intel_pcie_sysfs_init(struct intel_pcie_port *lpp) > +{ > + return devm_device_add_groups(lpp->pci.dev, pcie_cfg_groups); > +} > + > static void __intel_pcie_remove(struct intel_pcie_port *lpp) > { > intel_pcie_core_irq_disable(lpp); > @@ -490,8 +591,17 @@ static int intel_pcie_rc_init(struct pcie_port *pp) > { > struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); > struct intel_pcie_port *lpp =3D dev_get_drvdata(pci->dev); > + int ret; > =20 > - return intel_pcie_host_setup(lpp); > + ret =3D intel_pcie_host_setup(lpp); > + if (ret) > + return ret; > + > + ret =3D intel_pcie_sysfs_init(lpp); > + if (ret) > + __intel_pcie_remove(lpp); > + > + return ret; > } > =20 > int intel_pcie_msi_init(struct pcie_port *pp) > --=20 > 2.11.0