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x-originating-ip: [114.143.65.226] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 14e6593d-8c96-4156-f35c-08d759157fa9 x-ms-traffictypediagnostic: CH2PR13MB3798: x-ld-processed: 22f88e9d-ae0d-4ed9-b984-cdc9be1529f1,ExtAddr x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:8882; x-forefront-prvs: 02015246A9 x-forefront-antispam-report: SFV:NSPM;SFS:(10009020)(366004)(376002)(39850400004)(346002)(136003)(396003)(199004)(189003)(8676002)(305945005)(8936002)(81166006)(446003)(11346002)(14444005)(7696005)(476003)(6246003)(66556008)(81156014)(66946007)(7416002)(64756008)(66446008)(76116006)(66476007)(6506007)(53546011)(26005)(76176011)(186003)(66066001)(86362001)(99286004)(71200400001)(486006)(25786009)(102836004)(71190400001)(44832011)(478600001)(4326008)(3846002)(6116002)(14454004)(229853002)(52536014)(7736002)(9686003)(33656002)(2906002)(256004)(110136005)(54906003)(55016002)(4001150100001)(74316002)(316002)(5660300002)(6436002);DIR:OUT;SFP:1101;SCL:1;SRVR:CH2PR13MB3798;H:CH2PR13MB3368.namprd13.prod.outlook.com;FPR:;SPF:None;LANG:en;PTR:InfoNoRecords;A:1;MX:1; received-spf: None (protection.outlook.com: sifive.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: AjmcaU0Lot10SoUatcJ2lfNZLIO5AQsdgpBkXrDjCumogdfR8MxIqlXAJP8awfYPMCv8twSHL/2PvYH7u0SE59boWh/K+U/zuLKDK9flmMV1WNMvv9594/4Glg5LALG5T9k4OQAqR6rAGNzMuD8wOsv5GF/l4uJXwiJxn94plqqP7zzzkCYGKEBzukw3m8GtV6DtbwsNmpSeiZ+BKj9xrCUD0rYLX3fVxyM5B6KIj3Y1Y+eLwXEGi8M3C8Ki/V1D+0R1MXE+TJH+XZHHlq8DS/HGv9ktKgRfNGpksaCG5p8Jflhmq+GcTK7Q/ak9+FUcknXZpmKyO6TJ90pnSrkpg9e2iEGEi+Eq85jeYt2MqrBGjv72zj1qbWX2ueBUN7sFbYg/AZrIUNUVl7pXHx3jW0gb7geU6SaMeGs7NuwNVN+SYp932M9IPnaigC34CS3M Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: sifive.com X-MS-Exchange-CrossTenant-Network-Message-Id: 14e6593d-8c96-4156-f35c-08d759157fa9 X-MS-Exchange-CrossTenant-originalarrivaltime: 25 Oct 2019 06:35:16.5045 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 22f88e9d-ae0d-4ed9-b984-cdc9be1529f1 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: tp7XZ96WdrU1ampxmcqzLYin5BxPUY8abvs0oN8kxQ7VyPYlZzwTNnYZbTZPOE4ICD3dCQEJghAL9S4AYAgSnw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR13MB3798 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > On Thu, 24 Oct 2019, Logan Gunthorpe wrote: >=20 > > On 2019-10-24 3:14 a.m., Yash Shah wrote: > > > For I/O BARs to work correctly on RISC-V Linux, we need to establish > > > a reserved memory region for them, so that drivers that wish to use > > > I/O BARs can issue reads and writes against a memory region that is > > > mapped to the host PCIe controller's I/O BAR MMIO mapping. > > > > I don't think other arches do this. >=20 > $ git grep 'define PCI_IOBASE' arch/ > arch/arm/include/asm/io.h:#define PCI_IOBASE ((void __iomem > *)PCI_IO_VIRT_BASE) > arch/arm64/include/asm/io.h:#define PCI_IOBASE ((void __iomem > *)PCI_IO_START) > arch/m68k/include/asm/io_no.h:#define PCI_IOBASE ((void __iomem *) > PCI_IO_PA) > arch/microblaze/include/asm/io.h:#define PCI_IOBASE ((void __iomem > *)_IO_BASE) > arch/unicore32/include/asm/io.h:#define PCI_IOBASE > PKUNITY_PCILIO_BASE > arch/xtensa/include/asm/io.h:#define PCI_IOBASE ((void __iomem > *)XCHAL_KIO_BYPASS_VADDR) > $ >=20 > This is for the old x86-style, non-memory mapped I/O address space the > legacy PCI stuff that one would use in{b,w,l}()/out{b,w,l}() for. >=20 > Yash, you might consider updating your patch description to note that thi= s is > for "legacy I/O BARs (i.e., non-MMIO BARs)" or something similar. That > might make things clearer. Sure, will update the description and send v2. - Yash >=20 > > ioremap() typically just uses virtual address space in the VMALLOC > > region, PCI doesn't need it's own range. As far as I know the > > ioremap() implementation in riscv already does this. > > > > In any case, 16MB for PCI bar space seems woefully inadequate. >=20 > The modern MMIO PCI resources wind up in jost controller apertures, which > as you note, are usually much larger. They don't go in this legacy space= . >=20 > Regarding sizing - I haven't seen any PCIe cards with more than 64KiB of > legacy I/O resources. (16MiB / 64KiB) =3D 256, so 16MiB sounds reasonabl= e > from that point of view? ARM64 is using that. >=20 >=20 > - Paul