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From: Yash Shah <yash.shah@sifive.com>
To: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Cc: "linus.walleij@linaro.org" <linus.walleij@linaro.org>,
	"robh+dt@kernel.org" <robh+dt@kernel.org>,
	"mark.rutland@arm.com" <mark.rutland@arm.com>,
	"palmer@dabbelt.com" <palmer@dabbelt.com>,
	"Paul Walmsley ( Sifive)" <paul.walmsley@sifive.com>,
	"aou@eecs.berkeley.edu" <aou@eecs.berkeley.edu>,
	"tglx@linutronix.de" <tglx@linutronix.de>,
	"jason@lakedaemon.net" <jason@lakedaemon.net>,
	"maz@kernel.org" <maz@kernel.org>,
	"bmeng.cn@gmail.com" <bmeng.cn@gmail.com>,
	"atish.patra@wdc.com" <atish.patra@wdc.com>,
	Sagar Kadam <sagar.kadam@sifive.com>,
	"linux-gpio@vger.kernel.org" <linux-gpio@vger.kernel.org>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	"linux-riscv@lists.infradead.org"
	<linux-riscv@lists.infradead.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	Sachin Ghadi <sachin.ghadi@sifive.com>
Subject: RE: [PATCH v2 4/5] gpio: sifive: Add GPIO driver for SiFive SoCs
Date: Thu, 21 Nov 2019 08:32:33 +0000	[thread overview]
Message-ID: <CH2PR13MB3368A85F74CA82994E8C0D1B8C4E0@CH2PR13MB3368.namprd13.prod.outlook.com> (raw)
In-Reply-To: <CAMpxmJX0A+_6LmrWPe=Ne5KGhG9r_HySpstDhV5ZTnpz2QXF7Q@mail.gmail.com>

> -----Original Message-----
> From: Bartosz Golaszewski <bgolaszewski@baylibre.com>
> Sent: 20 November 2019 15:31
> To: Yash Shah <yash.shah@sifive.com>
> Cc: linus.walleij@linaro.org; robh+dt@kernel.org; mark.rutland@arm.com;
> palmer@dabbelt.com; Paul Walmsley ( Sifive) <paul.walmsley@sifive.com>;
> aou@eecs.berkeley.edu; tglx@linutronix.de; jason@lakedaemon.net;
> maz@kernel.org; bmeng.cn@gmail.com; atish.patra@wdc.com; Sagar Kadam
> <sagar.kadam@sifive.com>; linux-gpio@vger.kernel.org;
> devicetree@vger.kernel.org; linux-riscv@lists.infradead.org; linux-
> kernel@vger.kernel.org; Sachin Ghadi <sachin.ghadi@sifive.com>
> Subject: Re: [PATCH v2 4/5] gpio: sifive: Add GPIO driver for SiFive SoCs
> 
> śr., 20 lis 2019 o 07:59 Yash Shah <yash.shah@sifive.com> napisał(a):
> >
> > Adds the GPIO driver for SiFive RISC-V SoCs.
> >
> 
> This looks much better just a couple nits.
> 
> > Signed-off-by: Wesley W. Terpstra <wesley@sifive.com>
> > [Atish: Various fixes and code cleanup]
> > Signed-off-by: Atish Patra <atish.patra@wdc.com>
> > Signed-off-by: Yash Shah <yash.shah@sifive.com>
[...]
> > diff --git a/drivers/gpio/gpio-sifive.c b/drivers/gpio/gpio-sifive.c
> > new file mode 100644 index 0000000..02666ae
> > --- /dev/null
> > +++ b/drivers/gpio/gpio-sifive.c
> > @@ -0,0 +1,256 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright (C) 2019 SiFive
> > + */
> 
> I prefer to have a newline between the copyright notice and the headers.

Done

> 
> > +#include <linux/bitops.h>
> > +#include <linux/device.h>
> > +#include <linux/errno.h>
> > +#include <linux/of_irq.h>
> > +#include <linux/gpio/driver.h>
> > +#include <linux/init.h>
> > +#include <linux/of.h>
> 
> Is this really needed? I only see functions defined in of_irq.h.
> 
> > +#include <linux/platform_device.h>
> > +#include <linux/pm.h>
> 
> Same here - I don't see any functions from this header being called.
> 

Yes, you are right. Both the above inclusion of header file is unnecessary. Will remove them.

> > +#include <linux/slab.h>
> > +#include <linux/spinlock.h>
> > +#include <linux/regmap.h>
> > +
> > +#define GPIO_INPUT_VAL 0x00
> > +#define GPIO_INPUT_EN  0x04
> > +#define GPIO_OUTPUT_EN 0x08
> > +#define GPIO_OUTPUT_VAL        0x0C
> > +#define GPIO_RISE_IE   0x18
> > +#define GPIO_RISE_IP   0x1C
> > +#define GPIO_FALL_IE   0x20
> > +#define GPIO_FALL_IP   0x24
> > +#define GPIO_HIGH_IE   0x28
> > +#define GPIO_HIGH_IP   0x2C
> > +#define GPIO_LOW_IE    0x30
> > +#define GPIO_LOW_IP    0x34
> > +#define GPIO_OUTPUT_XOR        0x40
> > +
> > +#define MAX_GPIO               32
> > +#define SIFIVE_GPIO_IRQ_OFFSET 7
> 
> Please use a single prefix for all symbols in this driver. Let's stick to sifive_gpio
> and SIFIVE_GPIO for defines.

Sure.

> 
> > +
> > +struct sifive_gpio {
> > +       void __iomem            *base;
> > +       struct gpio_chip        gc;
> > +       struct regmap           *regs;
> > +       u32                     enabled;
> 
> The name of this field is a bit confusing - do you mind renaming it to
> something like irq_state? Maybe something else, but simply using 'enabled'
> makes me think this has more to do with the chip being enabled.
> 

Sure, will rename it to irq_state.

[...]
> > +       spin_lock_irqsave(&chip->gc.bgpio_lock, flags);
> > +       /* Disable all GPIO interrupts before enabling parent interrupts */
> > +       regmap_write(chip->regs, GPIO_RISE_IE, 0);
> > +       regmap_write(chip->regs, GPIO_FALL_IE, 0);
> > +       regmap_write(chip->regs, GPIO_HIGH_IE, 0);
> > +       regmap_write(chip->regs, GPIO_LOW_IE, 0);
> > +       spin_unlock_irqrestore(&chip->gc.bgpio_lock, flags);
> 
> No need for locking in probe().

Ok.
Thanks for your comments!

- Yash


  reply	other threads:[~2019-11-21  8:32 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-11-20  6:59 [PATCH v2 0/5] GPIO & Hierarchy IRQ support for HiFive Unleashed Yash Shah
2019-11-20  6:59 ` [PATCH v2 1/5] genirq: introduce irq_domain_translate_onecell Yash Shah
2019-11-20  9:34   ` Thomas Gleixner
2019-11-20 10:24     ` Marc Zyngier
2019-11-20 10:48       ` Thomas Gleixner
2019-11-20 10:38   ` Marc Zyngier
2019-11-21  8:35     ` Yash Shah
2019-11-21  8:55       ` Yash Shah
2019-11-21  9:20         ` Marc Zyngier
2019-11-20  6:59 ` [PATCH v2 2/5] irqchip: sifive: Support hierarchy irq domain Yash Shah
2019-11-22 10:17   ` Marc Zyngier
2019-11-20  6:59 ` [PATCH v2 3/5] gpio: sifive: Add DT documentation for SiFive GPIO Yash Shah
2019-11-20  6:59 ` [PATCH v2 4/5] gpio: sifive: Add GPIO driver for SiFive SoCs Yash Shah
2019-11-20 10:01   ` Bartosz Golaszewski
2019-11-21  8:32     ` Yash Shah [this message]
2019-11-20  6:59 ` [PATCH v2 5/5] riscv: dts: Add DT support for SiFive FU540 GPIO driver Yash Shah
2019-11-20  9:14   ` Andreas Schwab
2019-11-21  8:26     ` Yash Shah

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