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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: marvell.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: CO6PR18MB3873.namprd18.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: ce1ed19e-2f42-4fe6-c886-08d8e8903424 X-MS-Exchange-CrossTenant-originalarrivaltime: 16 Mar 2021 15:28:51.8684 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 70e1fb47-1155-421d-87fc-2e58f638b6e0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: h1P/8wN6sb/o0Yx7e7BSXtWc19y2X2QF7y79Y7p6na0/624Bs34wDvvOBMctu+Ek8gNxWtgrxqrhVJ7MOeZEVw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW3PR18MB3642 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.369,18.0.761 definitions=2021-03-16_05:2021-03-16,2021-03-16 signatures=0 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > Hi Stefan >=20 > Thanks for the strings change. Looks a lot better. >=20 > Now i took a look at the bigger picture. >=20 > > According to Armada SoC architecture and design, all the PPv2 ports > > which are populated on the same communication processor silicon die > > (CP11x) share the same Classifier and Parser engines. > > > > Armada is an embedded platform and therefore there is a need to > > reserve some of the PPv2 ports for different use cases. > > > > For example, a port can be reserved for a CM3 CPU running FreeRTOS for > > management purposes Hi Andrew and Jakub, There are multiple reasons why we must let the kernel initialize and manage= the reserved port: 1. According to pp2 hardware design, all classifier and parser configuratio= n access are indirect. In order to prevent race conditions, it needs to be = configured by single entity.=20 2. CM3 code has very small footprint requirement, we cannot implement the c= omplete Serdes and PHY infrastructure that kernel provides as part of CM3 a= pplication. Therefore I would like to continue relying on kernel configurat= ion for that. 3. In some cases we need to dynamically switch the port "user" between CM3 = and kernel. So I would like to preserve this functionality. > So the CM3 CPU has its own driver for this hardware? It seems like we sho= uld > not even instantiate the Linux driver for this port. Does the > CM3 have its own DT blob? I think the better solution is that the Armada = DT > for the board does not list the port, and the DT for the CM3 does. Linux > never sees the port, since Linux should not be using it. >=20 > > or by user-space data plane application. >=20 > You mean XDP/AF_XDP? I don't see any other XDP capable drivers having a > flag like this. If this was required, i would expect it to be a common pr= operly, > not driver private. No XDP doesn't require this. One of the use cases of the port reservation f= eature is the Marvell User Space SDK (MUSDK) which its latest code is publi= cly available here: https://github.com/MarvellEmbeddedProcessors/musdk-marvell You can find example use case for this application here: http://wiki.macchiatobin.net/tiki-index.php?page=3DMUSDK+Introduction Stefan.