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Wed, 2 Dec 2020 16:46:41 +0000 Received: from CY4PR11MB1781.namprd11.prod.outlook.com ([fe80::8135:848d:4e4:8f26]) by CY4PR11MB1781.namprd11.prod.outlook.com ([fe80::8135:848d:4e4:8f26%4]) with mapi id 15.20.3611.031; Wed, 2 Dec 2020 16:46:41 +0000 From: "Thokala, Srikanth" To: Greg KH , "mgross@linux.intel.com" CC: "markgross@kernel.org" , "arnd@arndb.de" , "bp@suse.de" , "damien.lemoal@wdc.com" , "dragan.cvetic@xilinx.com" , "corbet@lwn.net" , "leonard.crestez@nxp.com" , "palmerdabbelt@google.com" , "paul.walmsley@sifive.com" , "peng.fan@nxp.com" , "robh+dt@kernel.org" , "shawnguo@kernel.org" , "linux-kernel@vger.kernel.org" Subject: RE: [PATCH 09/22] misc: xlink-pcie: lh: Add core communication logic Thread-Topic: [PATCH 09/22] misc: xlink-pcie: lh: Add core communication logic Thread-Index: AQHWyDJT4s0PQTkyOUypKya3kV+KRKnjVXAAgACtfKA= Date: Wed, 2 Dec 2020 16:46:41 +0000 Message-ID: References: <20201201223511.65542-1-mgross@linux.intel.com> <20201201223511.65542-10-mgross@linux.intel.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: linuxfoundation.org; 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x-ms-exchange-antispam-messagedata: =?us-ascii?Q?LObIc1qT0m086SFwwiSUFAaAR3elO37XyxHkfdLaO0m5Y9PLwqt1pImaxI9I?= =?us-ascii?Q?w44PRtBrMxESMuFumQZzd9OKKETEbmtGjyp8YHyZ/cm8q8SVYtuq1iNAzRQU?= =?us-ascii?Q?OOISc1iOGB01PJDKgBTpdQWimkD7WUtpRyEAS4m2eY+0GY8ITAmCjHKbsirD?= =?us-ascii?Q?9tf5rbP9bSkNS+3v5Z9yoDLEsN2zXCvSmynLotWeCdS4HlzGMkfIdcnHKRm0?= =?us-ascii?Q?D4SsJG6dmwWlfg6agiAgr/LVwg1t49GBSIFRJ+e7gWC4gmOxv7iDvEedIPnr?= =?us-ascii?Q?I5do5UBaEdf4V9zpXOKN04r4xouPq7kUmmyU342kbDtbYinIif4ND7YxBWi4?= =?us-ascii?Q?+y4gSuF/81knB0zlGHsHSTncFGOXHWTtUUFK6G8UuWSD0I+eJdaA0NpHnScz?= =?us-ascii?Q?pPwZQggVtS6Q6LUQL9H4QyoCQR4QTLrI6Up8FE3y6i5YKTzP+nlMCjcT6dyb?= =?us-ascii?Q?h2d4bYa9RGTWwpNf0QtyRTRwizxaUicv3C96wdCj0A2diGJn3cTNOx0CnS07?= =?us-ascii?Q?ktYBSIOSPM5iiwwRvzDp1steuTHzAUoT57DPZaaQIa1aHcFK+QWHOcXdaKPG?= =?us-ascii?Q?G9BYxoled8dTx/ipc0AglAk9K++1tFZ5/RerwNrhCbqnh4KUnf9ed7CMi5Mt?= =?us-ascii?Q?/oA4cAdkpYWVwAn4e7ynqZwRZtGzSuSxruimMHDtLJhO+UzHIF9IAAilPFeG?= =?us-ascii?Q?uDX+eTKMENjJ+DKSpn7UEGarqekl8ArBZKQLWO4NKaNAvD0UvGeiYndf4oVK?= =?us-ascii?Q?JxxORAC0zVJBVSnS+QUKHbAe67uQAD74CF3JmqYSoCt17fd2gI7tHYZ9DqzU?= =?us-ascii?Q?iRe0U/yAc36u9NpPj9GNBZRTdXuihP+Xeo4RKJbTDcaPdYNVWTxprXEX/cZJ?= =?us-ascii?Q?/Aff0rjJB10bEZ6c1a8HwaDlAwX+Jvw9h6jcqiBiDZFfqF0n6CFpqUh8ou1g?= =?us-ascii?Q?NnhIcf8u4CYntZycDyMmj+GZnf5SIyWBZHeauRK2/ck=3D?= x-ms-exchange-transport-forked: True Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: CY4PR11MB1781.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 538ff2b8-b6f3-4913-15d0-08d896e1d89d X-MS-Exchange-CrossTenant-originalarrivaltime: 02 Dec 2020 16:46:41.7817 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: o5i0GsDHLvVJhvZOy03QWm0cLwnKjK6ivGKKJjuOPo/I/kN5ahhbNcCIVjxQTR1KaHq25d9sYdzXmMGiyW4dvnO41PtVVcL4m5jM4qXFtOY= X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR1101MB2198 X-OriginatorOrg: intel.com Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Greg, > -----Original Message----- > From: Greg KH > Sent: Wednesday, December 2, 2020 11:48 AM > To: mgross@linux.intel.com > Cc: markgross@kernel.org; arnd@arndb.de; bp@suse.de; > damien.lemoal@wdc.com; dragan.cvetic@xilinx.com; corbet@lwn.net; > leonard.crestez@nxp.com; palmerdabbelt@google.com; > paul.walmsley@sifive.com; peng.fan@nxp.com; robh+dt@kernel.org; > shawnguo@kernel.org; linux-kernel@vger.kernel.org; Thokala, Srikanth > > Subject: Re: [PATCH 09/22] misc: xlink-pcie: lh: Add core communication > logic >=20 > On Tue, Dec 01, 2020 at 02:34:58PM -0800, mgross@linux.intel.com wrote: > > From: Srikanth Thokala > > > > Add logic to establish communication with the remote host which is > through > > ring buffer management and MSI/Doorbell interrupts > > > > Reviewed-by: Mark Gross > > Signed-off-by: Srikanth Thokala > > --- > > drivers/misc/xlink-pcie/local_host/Makefile | 2 + > > drivers/misc/xlink-pcie/local_host/core.c | 894 ++++++++++++++++++++ > > drivers/misc/xlink-pcie/local_host/core.h | 247 ++++++ > > drivers/misc/xlink-pcie/local_host/epf.c | 116 ++- > > drivers/misc/xlink-pcie/local_host/epf.h | 26 + > > drivers/misc/xlink-pcie/local_host/util.c | 375 ++++++++ > > drivers/misc/xlink-pcie/local_host/util.h | 70 ++ > > drivers/misc/xlink-pcie/local_host/xpcie.h | 65 ++ > > include/linux/xlink_drv_inf.h | 60 ++ > > 9 files changed, 1847 insertions(+), 8 deletions(-) > > create mode 100644 drivers/misc/xlink-pcie/local_host/core.c > > create mode 100644 drivers/misc/xlink-pcie/local_host/core.h > > create mode 100644 drivers/misc/xlink-pcie/local_host/util.c > > create mode 100644 drivers/misc/xlink-pcie/local_host/util.h > > create mode 100644 include/linux/xlink_drv_inf.h > > > > diff --git a/drivers/misc/xlink-pcie/local_host/Makefile > b/drivers/misc/xlink-pcie/local_host/Makefile > > index 54fc118e2dd1..28761751d43b 100644 > > --- a/drivers/misc/xlink-pcie/local_host/Makefile > > +++ b/drivers/misc/xlink-pcie/local_host/Makefile > > @@ -1,3 +1,5 @@ > > obj-$(CONFIG_XLINK_PCIE_LH_DRIVER) +=3D mxlk_ep.o > > mxlk_ep-objs :=3D epf.o > > mxlk_ep-objs +=3D dma.o > > +mxlk_ep-objs +=3D core.o > > +mxlk_ep-objs +=3D util.o > > diff --git a/drivers/misc/xlink-pcie/local_host/core.c > b/drivers/misc/xlink-pcie/local_host/core.c > > new file mode 100644 > > index 000000000000..aecaaa783153 > > --- /dev/null > > +++ b/drivers/misc/xlink-pcie/local_host/core.c > > @@ -0,0 +1,894 @@ > > +// SPDX-License-Identifier: GPL-2.0-only > > > +/***********************************************************************= * > ***** > > + * > > + * Intel Keem Bay XLink PCIe Driver > > + * > > + * Copyright (C) 2020 Intel Corporation > > + * > > + > *************************************************************************= * > **/ > > + > > +#include > > + > > +#include "epf.h" > > +#include "core.h" > > +#include "util.h" > > + > > +static struct xpcie *global_xpcie; > > + > > +static int rx_pool_size =3D SZ_32M; > > +module_param(rx_pool_size, int, 0664); > > +MODULE_PARM_DESC(rx_pool_size, "receiving pool size (default 32 MiB)")= ; > > + > > +static int tx_pool_size =3D SZ_32M; > > +module_param(tx_pool_size, int, 0664); > > +MODULE_PARM_DESC(tx_pool_size, "transmitting pool size (default 32 > MiB)"); > > + > > +static int fragment_size =3D XPCIE_FRAGMENT_SIZE; > > +module_param(fragment_size, int, 0664); > > +MODULE_PARM_DESC(fragment_size, "transfer descriptor size (default 128 > KiB)"); > > + > > +static bool tx_pool_coherent =3D true; > > +module_param(tx_pool_coherent, bool, 0664); > > +MODULE_PARM_DESC(tx_pool_coherent, > > + "transmitting pool using coherent memory (default true)"); > > + > > +static bool rx_pool_coherent; > > +module_param(rx_pool_coherent, bool, 0664); > > +MODULE_PARM_DESC(rx_pool_coherent, > > + "receiving pool using coherent memory (default false)"); >=20 > This isn't the 1990's anymore. Please make these dynamic such that they > are never needed (the code figures out the best values), or on some > per-device basis using configfs or sysfs. Sure, I will fix it in my v2. thanks! Srikanth =20 > thanks, >=20 > greg k-h