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[144.178.202.138]) by smtp.gmail.com with ESMTPSA id p17-20020a1709060e9100b00a3d11feb32esm1429131ejf.186.2024.02.16.02.46.49 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 16 Feb 2024 02:46:50 -0800 (PST) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Fri, 16 Feb 2024 11:46:49 +0100 Message-Id: Cc: "Andy Gross" , "Bjorn Andersson" , "Konrad Dybcio" , "Thara Gopinath" , "Herbert Xu" , "David S. Miller" , "Rob Herring" , "Krzysztof Kozlowski" , "Conor Dooley" , "Bhupesh Sharma" , <~postmarketos/upstreaming@lists.sr.ht>, , , , , Subject: Re: [PATCH 2/2] arm64: dts: qcom: sm6350: Add Crypto Engine From: "Luca Weiss" To: "Stephan Gerhold" X-Mailer: aerc 0.15.2 References: <20240105-sm6350-qce-v1-0-416e5c7319ac@fairphone.com> <20240105-sm6350-qce-v1-2-416e5c7319ac@fairphone.com> In-Reply-To: On Fri Jan 5, 2024 at 5:30 PM CET, Stephan Gerhold wrote: > On Fri, Jan 05, 2024 at 05:15:44PM +0100, Luca Weiss wrote: > > Add crypto engine (CE) and CE BAM related nodes and definitions for thi= s > > SoC. > >=20 > > For reference: > >=20 > > [ 2.297419] qcrypto 1dfa000.crypto: Crypto device found, version 5= .5.1 > >=20 > > Signed-off-by: Luca Weiss > > --- > > arch/arm64/boot/dts/qcom/sm6350.dtsi | 31 ++++++++++++++++++++++++++++= +++ > > 1 file changed, 31 insertions(+) > >=20 > > diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts= /qcom/sm6350.dtsi > > index 8fd6f4d03490..516aadbb16bb 100644 > > --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi > > +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi > > @@ -1212,6 +1212,37 @@ ufs_mem_phy_lanes: phy@1d87400 { > > }; > > }; > > =20 > > + cryptobam: dma-controller@1dc4000 { > > + compatible =3D "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; > > + reg =3D <0 0x01dc4000 0 0x24000>; > > + interrupts =3D ; > > + #dma-cells =3D <1>; > > + qcom,ee =3D <0>; > > + qcom,controlled-remotely; > > + num-channels =3D <16>; > > + qcom,num-ees =3D <4>; > > + iommus =3D <&apps_smmu 0x432 0x0000>, > > + <&apps_smmu 0x438 0x0001>, > > + <&apps_smmu 0x43f 0x0000>, > > + <&apps_smmu 0x426 0x0011>, > > + <&apps_smmu 0x436 0x0011>; > > The last two lines look equivalent to me: 0x436 & ~0x0011 =3D 0x426. I don't understand the IOMMU SID + mask really, but I think I've seen somewhere before like here that TZ can be a bit picky with the SIDs? https://lore.kernel.org/linux-arm-msm/opqdrmyj3y64nqqqmakjydn5rkspizufyeavm= 7ec7c7ufqz4wk@ey2a7bq3shfj/ https://lore.kernel.org/linux-arm-msm/11b5db69-49f5-4d7b-81c9-687d66a5cb0d@= linaro.org/ I don't quite want to risk having some obscure use case breaking because we cleaned up the dts ;) But if you're more sure than me that it won't break, let me know! > > It's also a bit weird that the mask has one more digit than the stream > ID. And ordered numerically (by stream ID, first number) it would be a > bit easier to read. :-) Sorting them is no problem, can do that for v2. > > Thanks, > Stephan