From: "Voon, Weifeng" <weifeng.voon@intel.com>
To: Jose Abreu <Jose.Abreu@synopsys.com>,
"David S. Miller" <davem@davemloft.net>,
Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: "netdev@vger.kernel.org" <netdev@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"Giuseppe Cavallaro" <peppe.cavallaro@st.com>,
Andrew Lunn <andrew@lunn.ch>,
"Florian Fainelli" <f.fainelli@gmail.com>,
Alexandre Torgue <alexandre.torgue@st.com>,
biao huang <biao.huang@mediatek.com>,
"Ong, Boon Leong" <boon.leong.ong@intel.com>,
"Kweh, Hock Leong" <hock.leong.kweh@intel.com>
Subject: RE: [PATCH net-next v4 5/5] net: stmmac: add EHL SGMII 1Gbps PCI info and PCI ID
Date: Wed, 29 May 2019 18:00:34 +0000 [thread overview]
Message-ID: <D6759987A7968C4889FDA6FA91D5CBC814707D4C@PGSMSX103.gar.corp.intel.com> (raw)
In-Reply-To: <78EB27739596EE489E55E81C33FEC33A0B933497@DE02WEMBXB.internal.synopsys.com>
>
> > + plat->axi->axi_lpi_en = 0;
> > + plat->axi->axi_xit_frm = 0;
> > + plat->axi->axi_wr_osr_lmt = 0;
>
> This is not a valid value.
Can you please explained why is not a valid value? And what should
be the recommended value?
Databook mentioned that "Maximum outstanding requests =
WR_OSR_LMT + 1"
>
> > + plat->axi->axi_rd_osr_lmt = 2;
> > + plat->axi->axi_blen[0] = 4;
> > + plat->axi->axi_blen[1] = 8;
> > + plat->axi->axi_blen[2] = 16;
> > +
> > + /* Set default value for multicast hash bins */
> > + plat->multicast_filter_bins = HASH_TABLE_SIZE;
> > +
> > + /* Set default value for unicast filter entries */
> > + plat->unicast_filter_entries = 1;
> > +
> > + /* Set the maxmtu to a default of JUMBO_LEN */
> > + plat->maxmtu = JUMBO_LEN;
> > +
> > + /* Set 32KB fifo size as the advertised fifo size in
> > + * the HW features is not the same as the HW implementation
> > + */
>
> Hmm ? I'm curious, can you explain ?
The RTL comes with a 64KB selection in HW features. But the HW implementation
only uses a 32KB RAM. This will be documented as errata.
>
> > + plat->tx_fifo_size = 32768;
> > + plat->rx_fifo_size = 32768;
> > +
> > + return 0;
> > +}
> > +
> > +static int ehl_sgmii1g_data(struct pci_dev *pdev,
> > + struct plat_stmmacenet_data *plat) {
> > + int ret;
> > +
> > + /* Set common default data first */
> > + ret = ehl_common_data(pdev, plat);
> > +
>
Regards
Weifeng
prev parent reply other threads:[~2019-05-29 18:00 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-05-29 16:58 [PATCH net-next v4 0/5] net: stmmac: enable EHL SGMI Voon Weifeng
2019-05-29 16:58 ` [PATCH net-next v4 1/5] net: stmmac: enable clause 45 mdio support Voon Weifeng
2019-05-29 10:16 ` Jose Abreu
2019-05-29 17:39 ` Voon, Weifeng
2019-05-29 23:06 ` Andrew Lunn
2019-05-29 16:58 ` [PATCH net-next v4 2/5] net: stmmac: introducing support for DWC xPCS logics Voon Weifeng
2019-05-29 10:19 ` Jose Abreu
2019-05-29 16:58 ` [PATCH net-next v4 3/5] net: stmmac: add xpcs function hooks into main driver and ethtool Voon Weifeng
2019-05-29 10:23 ` Jose Abreu
2019-05-29 16:58 ` [PATCH net-next v4 4/5] net: stmmac: add xPCS functions for device with DWMACv5.1 Voon Weifeng
2019-05-29 10:25 ` Jose Abreu
2019-05-29 16:58 ` [PATCH net-next v4 5/5] net: stmmac: add EHL SGMII 1Gbps PCI info and PCI ID Voon Weifeng
2019-05-29 10:28 ` Jose Abreu
2019-05-29 18:00 ` Voon, Weifeng [this message]
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