From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751731AbcJ0FIU (ORCPT ); Thu, 27 Oct 2016 01:08:20 -0400 Received: from mail-db5eur01on0079.outbound.protection.outlook.com ([104.47.2.79]:35268 "EHLO EUR01-DB5-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1750900AbcJ0FIO (ORCPT ); Thu, 27 Oct 2016 01:08:14 -0400 From: "Y.B. Lu" To: Scott Wood , "linux-mmc@vger.kernel.org" , "ulf.hansson@linaro.org" , Arnd Bergmann CC: "linuxppc-dev@lists.ozlabs.org" , "devicetree@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "linux-clk@vger.kernel.org" , "linux-i2c@vger.kernel.org" , "iommu@lists.linux-foundation.org" , "netdev@vger.kernel.org" , Mark Rutland , Rob Herring , Russell King , Jochen Friedrich , Joerg Roedel , Claudiu Manoil , Bhupesh Sharma , Qiang Zhao , Kumar Gala , Santosh Shilimkar , Leo Li , "X.B. Xie" , "M.H. Lian" Subject: RE: [v12, 5/8] soc: fsl: add GUTS driver for QorIQ platforms Thread-Topic: [v12, 5/8] soc: fsl: add GUTS driver for QorIQ platforms Thread-Index: AQHSE9cxIHr6JcomZ0m5JAkJisranqC7LswAgAC93BA= Date: Thu, 27 Oct 2016 04:34:06 +0000 Message-ID: References: <1474441040-11946-1-git-send-email-yangbo.lu@nxp.com> <1474441040-11946-6-git-send-email-yangbo.lu@nxp.com> <1477501566.6812.9.camel@buserror.net> In-Reply-To: <1477501566.6812.9.camel@buserror.net> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=yangbo.lu@nxp.com; x-originating-ip: [123.151.195.51] x-ms-office365-filtering-correlation-id: ca34b761-9db9-49b4-b0dc-08d3fe227d17 x-microsoft-exchange-diagnostics: 1;HE1PR04MB1195;7:YzSkixY+9HNFKsMC6UTRSNKJdVYba9U5awYfhzwLCYn/ke095pa9nDcBu8z+BwFrzfgnCo2lE88XfZtuhmXOSPe3Ujn7a64ew5oy5zVr7fqb3AOHVTViNBvIP4e+qsduwcBSSS9wYmmXE7UZeFp6RTqqu/7VVRYyATJv0aE51fYs4prU7EMeahO+X9XkKCJyssw6vp4071RBOgMp2olw2F746z6ArlchFC+8WCmxpIJtJ8z/1vEJzcIYThOzabcRtBviEmLuIEik6Stwg3J5cENOzLFBX14b6vnh0XZBUrJITpE6bfUN3F0Y08W+iZb5a3fRahknEQUaed80S1iR5fmNnjdHKd6TWnDrL1EQS68= x-microsoft-antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:HE1PR04MB1195; x-microsoft-antispam-prvs: x-exchange-antispam-report-test: UriScan:(72170088055959)(9452136761055)(65623756079841)(258649278758335); x-exchange-antispam-report-cfa-test: BCL:0;PCL:0;RULEID:(6040176)(6045074)(601004)(2401047)(5005006)(8121501046)(10201501046)(3002001)(6055026)(6046074)(6072074);SRVR:HE1PR04MB1195;BCL:0;PCL:0;RULEID:;SRVR:HE1PR04MB1195; x-forefront-prvs: 0108A997B2 x-forefront-antispam-report: SFV:NSPM;SFS:(10009020)(6009001)(7916002)(377424004)(24454002)(377454003)(199003)(13464003)(189002)(57704003)(4326007)(8936002)(2906002)(9686002)(3660700001)(11100500001)(2900100001)(3846002)(66066001)(102836003)(3280700002)(7416002)(68736007)(586003)(6116002)(19580395003)(7696004)(87936001)(97736004)(5660300001)(86362001)(2501003)(2201001)(189998001)(76576001)(74316002)(92566002)(5001770100001)(54356999)(19580405001)(50986999)(76176999)(2950100002)(106116001)(10400500002)(305945005)(7846002)(101416001)(81156014)(122556002)(5002640100001)(33656002)(8676002)(106356001)(81166006)(7736002)(77096005)(105586002);DIR:OUT;SFP:1101;SCL:1;SRVR:HE1PR04MB1195;H:DB6PR0401MB2536.eurprd04.prod.outlook.com;FPR:;SPF:None;PTR:InfoNoRecords;A:1;MX:1;LANG:en; spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-originalarrivaltime: 27 Oct 2016 04:34:06.9018 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: HE1PR04MB1195 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from base64 to 8bit by mail.home.local id u9R58UZf005573 Hi Scott, > -----Original Message----- > From: Scott Wood [mailto:oss@buserror.net] > Sent: Thursday, October 27, 2016 1:06 AM > To: Y.B. Lu; linux-mmc@vger.kernel.org; ulf.hansson@linaro.org; Arnd > Bergmann > Cc: linuxppc-dev@lists.ozlabs.org; devicetree@vger.kernel.org; linux-arm- > kernel@lists.infradead.org; linux-kernel@vger.kernel.org; linux- > clk@vger.kernel.org; linux-i2c@vger.kernel.org; iommu@lists.linux- > foundation.org; netdev@vger.kernel.org; Mark Rutland; Rob Herring; > Russell King; Jochen Friedrich; Joerg Roedel; Claudiu Manoil; Bhupesh > Sharma; Qiang Zhao; Kumar Gala; Santosh Shilimkar; Leo Li; X.B. Xie; M.H. > Lian > Subject: Re: [v12, 5/8] soc: fsl: add GUTS driver for QorIQ platforms > > On Wed, 2016-09-21 at 14:57 +0800, Yangbo Lu wrote: > > diff --git a/drivers/soc/fsl/Kconfig b/drivers/soc/fsl/Kconfig new > > file mode 100644 index 0000000..b99764c > > --- /dev/null > > +++ b/drivers/soc/fsl/Kconfig > > @@ -0,0 +1,19 @@ > > +# > > +# Freescale SOC drivers > > +# > > + > > +source "drivers/soc/fsl/qe/Kconfig" > > + > > +config FSL_GUTS > > + bool "Freescale QorIQ GUTS driver" > > + select SOC_BUS > > + help > > +   The global utilities block controls power management, I/O device > > +   enabling, power-onreset(POR) configuration monitoring, alternate > > +   function selection for multiplexed signals,and clock control. > > +   This driver is to manage and access global utilities block. > > +   Initially only reading SVR and registering soc device are > > supported. > > +   Other guts accesses, such as reading RCW, should eventually be > > moved > > +   into this driver as well. > > + > > +   If you want GUTS driver support, you should say Y here. > > This is user-enablable without dependencies, which means it will break > some randconfigs.  If this is to be enabled via select then remove the > text after "bool". [Lu Yangbo-B47093] Will enable it via select and remove text after 'bool'. > > > +/* SoC die attribute definition for QorIQ platform */ static const > > +struct fsl_soc_die_attr fsl_soc_die[] = { #ifdef CONFIG_PPC > > + /* > > +  * Power Architecture-based SoCs T Series > > +  */ > > + > > + /* Die: T4240, SoC: T4240/T4160/T4080 */ > > + { .die = "T4240", > > +   .svr = 0x82400000, > > +   .mask = 0xfff00000, > > + }, > > + /* Die: T1040, SoC: T1040/T1020/T1042/T1022 */ > > + { .die = "T1040", > > +   .svr = 0x85200000, > > +   .mask = 0xfff00000, > > + }, > > + /* Die: T2080, SoC: T2080/T2081 */ > > + { .die = "T2080", > > +   .svr = 0x85300000, > > +   .mask = 0xfff00000, > > + }, > > + /* Die: T1024, SoC: T1024/T1014/T1023/T1013 */ > > + { .die = "T1024", > > +   .svr = 0x85400000, > > +   .mask = 0xfff00000, > > + }, > > +#endif /* CONFIG_PPC */ > > +#if defined(CONFIG_ARCH_MXC) || defined(CONFIG_ARCH_LAYERSCAPE) > > Will this driver ever be probed on MXC?  Why do we need these ifdefs at > all? [Lu Yangbo-B47093] Will remove them. In the previous version, we use too many members for soc definition, so I add #ifdef for ARCH. CONFIG_ARCH_MXC was for ls1021a. > > > > + /* > > +  * ARM-based SoCs LS Series > > +  */ > > + > > + /* Die: LS1043A, SoC: LS1043A/LS1023A */ > > + { .die = "LS1043A", > > +   .svr = 0x87920000, > > +   .mask = 0xffff0000, > > + }, > > + /* Die: LS2080A, SoC: LS2080A/LS2040A/LS2085A */ > > + { .die = "LS2080A", > > +   .svr = 0x87010000, > > +   .mask = 0xff3f0000, > > + }, > > + /* Die: LS1088A, SoC: LS1088A/LS1048A/LS1084A/LS1044A */ > > + { .die = "LS1088A", > > +   .svr = 0x87030000, > > +   .mask = 0xff3f0000, > > + }, > > + /* Die: LS1012A, SoC: LS1012A */ > > + { .die = "LS1012A", > > +   .svr = 0x87040000, > > +   .mask = 0xffff0000, > > + }, > > + /* Die: LS1046A, SoC: LS1046A/LS1026A */ > > + { .die = "LS1046A", > > +   .svr = 0x87070000, > > +   .mask = 0xffff0000, > > + }, > > + /* Die: LS2088A, SoC: LS2088A/LS2048A/LS2084A/LS2044A */ > > + { .die = "LS2088A", > > +   .svr = 0x87090000, > > +   .mask = 0xff3f0000, > > + }, > > + /* Die: LS1021A, SoC: LS1021A/LS1020A/LS1022A > > +  * Note: Put this die at the end in cause of incorrect > > identification > > +  */ > > + { .die = "LS1021A", > > +   .svr = 0x87000000, > > +   .mask = 0xfff00000, > > + }, > > +#endif /* CONFIG_ARCH_MXC || CONFIG_ARCH_LAYERSCAPE */ > > Instead of relying on ordering, add more bits to the mask so that there's > no overlap.  I think 0xfff70000 would work. [Lu Yangbo-B47093] Ok, Will do that. Then we add 3 bits of 'Various Personalities' field for ls1021a die identification. > > > +out: > > + kfree(soc_dev_attr.machine); > > + kfree(soc_dev_attr.family); > > + kfree(soc_dev_attr.soc_id); > > + kfree(soc_dev_attr.revision); > > + iounmap(guts->regs); > > +out_free: > > + kfree(guts); > > + return ret; > > +} > > Please use devm. [Lu Yangbo-B47093] Sorry for forgetting this. Will do that and send out the new version soon. Thanks for your comments. > > -Scott