From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933993AbcIEVVy (ORCPT ); Mon, 5 Sep 2016 17:21:54 -0400 Received: from mail-db5eur01on0049.outbound.protection.outlook.com ([104.47.2.49]:32544 "EHLO EUR01-DB5-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S932454AbcIEVVw (ORCPT ); Mon, 5 Sep 2016 17:21:52 -0400 X-Greylist: delayed 44346 seconds by postgrey-1.27 at vger.kernel.org; Mon, 05 Sep 2016 17:21:51 EDT From: Meng Yi To: Stefan Agner , "dri-devel@lists.freedesktop.org" CC: "alison.wang@freescale.com" , "jianwei.wang.chn@gmail.com" , "linux-kernel@vger.kernel.org" , "stable@vger.kernel.org" Subject: RE: [PATCH] drm/fsl-dcu: fix endian issue when using clk_register_divider Thread-Topic: [PATCH] drm/fsl-dcu: fix endian issue when using clk_register_divider Thread-Index: AQHSBU1bKUSXgxk6JUihA1w3GJdGcqBqmQAg Date: Mon, 5 Sep 2016 08:46:56 +0000 Message-ID: References: <20160902190753.27736-1-stefan@agner.ch> In-Reply-To: <20160902190753.27736-1-stefan@agner.ch> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=meng.yi@nxp.com; x-originating-ip: [199.59.231.64] x-ms-office365-filtering-correlation-id: 33ca4b2c-730d-4014-9296-08d3d5693132 x-microsoft-exchange-diagnostics: 1;DB6PR0401MB2632;6:8A/Qqj94u7yaWGMwyOiRStkezo/px3JRGoI9wgnCRbcoubB9flUKIsjVS2S2ncubNcnWWnshla2eqB4hZRoJble3VhQ3T6eZ1uyd+4yJWpF0WmSnpYPGPfMKSPO3wun7lxVycA04rhLaHbDzYtRACOiDUdVjWKROSlYiin1ORwgq/7KNp0llQ8lBj+grCytYUrZ0pJjvqz7E+UuLWYzMQucpqkGEzMzjTCY0WC3zkFQgQp9hnLKeMxQojtS/q54NLCi0stOWqnyNqgt69CiH4EPYiOuQDixTWrALabCv+bLkqBNjwp/uBTUnjwGzHCkZrzORqk2RGgWwaSSKJ4pTfA==;5:9cBoxTBkoUeNASkRvYKQUw53B8M2fIrni+SHAiZ2hETUZDY1alL5sm/VSM+678i1Gg7c+bLM9RxCgS5ALMkcFHwMbYTcuqMR3GKxOFmceIj+jU58UwobhjYPn0wXMH76JlOoJwVdCLW+dAY/rRf2YQ==;24:ycx0bNWUc/p82Cs/ny63XpfQ4zfjo3W5dt/5M0TwKco+RNCw0yr1lRoPi+QgyBurJmbSVSY1oyux1fUbiPonU0tbarbe8n0IDBZSJfAuf/w=;7:VU5cMIPySu/gss/veTJ6em+AKM4C6KPXRy0oHN6YshbXeLTbPjLiiF/SqSZgaquJHTIEMeD0T36pMk7ACKbOVpVUqXHgRaEfawGcqqEiYS7bXV5/UKYV6yjvw8XNVgbE/U2+Y14RjZzBiqHcn0DWLFDJN/P8e3iLrpFANXLpPHapLg9H1N0SKUSZ0p1r6jIRLj4gYHE2zxQExtgrdb8W9AjD5SI20GTLcs5K0beLM2H2nKUCEKuxr5AqgT0wA7bV x-microsoft-antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:DB6PR0401MB2632; x-microsoft-antispam-prvs: x-exchange-antispam-report-test: UriScan:(9452136761055)(185117386973197); x-exchange-antispam-report-cfa-test: BCL:0;PCL:0;RULEID:(6040176)(601004)(2401047)(5005006)(8121501046)(3002001)(10201501046)(6055026);SRVR:DB6PR0401MB2632;BCL:0;PCL:0;RULEID:;SRVR:DB6PR0401MB2632; x-forefront-prvs: 005671E15D x-forefront-antispam-report: SFV:NSPM;SFS:(10009020)(6009001)(7916002)(189002)(43544003)(199003)(50986999)(10400500002)(81156014)(586003)(102836003)(81166006)(86362001)(19580395003)(8676002)(2900100001)(8936002)(3846002)(2950100001)(3280700002)(5002640100001)(4326007)(189998001)(105586002)(87936001)(76576001)(33656002)(7846002)(2501003)(9686002)(92566002)(68736007)(11100500001)(305945005)(74316002)(7736002)(19580405001)(77096005)(66066001)(7696003)(2906002)(76176999)(97736004)(54356999)(5660300001)(106356001)(5001770100001)(3660700001)(101416001)(122556002)(6116002)(106116001);DIR:OUT;SFP:1101;SCL:1;SRVR:DB6PR0401MB2632;H:DB6PR0401MB2631.eurprd04.prod.outlook.com;FPR:;SPF:None;PTR:InfoNoRecords;MX:1;A:1;LANG:en; spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-originalarrivaltime: 05 Sep 2016 08:46:56.1070 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB6PR0401MB2632 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from quoted-printable to 8bit by mail.home.local id u85LM0nw004132 > Subject: [PATCH] drm/fsl-dcu: fix endian issue when using clk_register_divider > > Since using clk_register_divider to setup the pixel clock, regmap is no longer > used. Regmap did take care of DCU using different endianness. Check > endianness using the device-tree property "big-endian" to determine the > location of DIV_RATIO. > > Cc: stable@vger.kernel.org > Fixes: 2d701449bce1 ("drm/fsl-dcu: use common clock framework for pixel > clock divider") > Reported-by: Meng Yi > Signed-off-by: Stefan Agner > --- > drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c | 7 ++++++- > 1 file changed, 6 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c b/drivers/gpu/drm/fsl- > dcu/fsl_dcu_drm_drv.c > index 7882387..8dd042e 100644 > --- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c > +++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c > @@ -330,6 +330,7 @@ static int fsl_dcu_drm_probe(struct platform_device > *pdev) > const char *pix_clk_in_name; > const struct of_device_id *id; > int ret; > + u8 div_ratio_shift = 0; > > fsl_dev = devm_kzalloc(dev, sizeof(*fsl_dev), GFP_KERNEL); > if (!fsl_dev) > @@ -382,11 +383,15 @@ static int fsl_dcu_drm_probe(struct platform_device > *pdev) > pix_clk_in = fsl_dev->clk; > } > > + if (of_property_read_bool(dev->of_node, "big-endian")) > + div_ratio_shift = 24; > + > + > pix_clk_in_name = __clk_get_name(pix_clk_in); > snprintf(pix_clk_name, sizeof(pix_clk_name), "%s_pix", > pix_clk_in_name); > fsl_dev->pix_clk = clk_register_divider(dev, pix_clk_name, > pix_clk_in_name, 0, base + DCU_DIV_RATIO, > - 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL); > + div_ratio_shift, 8, CLK_DIVIDER_ROUND_CLOSEST, > NULL); > if (IS_ERR(fsl_dev->pix_clk)) { > dev_err(dev, "failed to register pix clk\n"); > ret = PTR_ERR(fsl_dev->pix_clk); > -- > 2.9.0 Tested-by: Meng Yi On LS1021A-TWR board. Meng