From: "Z.q. Hou" <zhiqiang.hou@nxp.com>
To: Andrew Murray <amurray@thegoodpenguin.co.uk>
Cc: "linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"bhelgaas@google.com" <bhelgaas@google.com>,
"robh+dt@kernel.org" <robh+dt@kernel.org>,
"andrew.murray@arm.com" <andrew.murray@arm.com>,
"arnd@arndb.de" <arnd@arndb.de>,
"mark.rutland@arm.com" <mark.rutland@arm.com>,
"l.subrahmanya@mobiveil.co.in" <l.subrahmanya@mobiveil.co.in>,
"shawnguo@kernel.org" <shawnguo@kernel.org>,
"m.karthikeyan@mobiveil.co.in" <m.karthikeyan@mobiveil.co.in>,
Leo Li <leoyang.li@nxp.com>,
"lorenzo.pieralisi@arm.com" <lorenzo.pieralisi@arm.com>,
"catalin.marinas@arm.com" <catalin.marinas@arm.com>,
"will.deacon@arm.com" <will.deacon@arm.com>,
Mingkai Hu <mingkai.hu@nxp.com>,
"M.h. Lian" <minghuan.lian@nxp.com>,
Xiaowei Bao <xiaowei.bao@nxp.com>
Subject: RE: [PATCHv10 08/13] PCI: mobiveil: Add 8-bit and 16-bit CSR register accessors
Date: Mon, 24 Feb 2020 05:50:18 +0000 [thread overview]
Message-ID: <DB8PR04MB6747E9173765F4113350ABF584EC0@DB8PR04MB6747.eurprd04.prod.outlook.com> (raw)
In-Reply-To: <20200220172924.GI19388@big-machine>
Hi Andrew,
Thanks a lot for your review!
Thanks,
Zhiqiang
> -----Original Message-----
> From: Andrew Murray <amurray@thegoodpenguin.co.uk>
> Sent: 2020年2月21日 1:29
> To: Z.q. Hou <zhiqiang.hou@nxp.com>
> Cc: linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org;
> bhelgaas@google.com; robh+dt@kernel.org; andrew.murray@arm.com;
> arnd@arndb.de; mark.rutland@arm.com; l.subrahmanya@mobiveil.co.in;
> shawnguo@kernel.org; m.karthikeyan@mobiveil.co.in; Leo Li
> <leoyang.li@nxp.com>; lorenzo.pieralisi@arm.com;
> catalin.marinas@arm.com; will.deacon@arm.com; Mingkai Hu
> <mingkai.hu@nxp.com>; M.h. Lian <minghuan.lian@nxp.com>; Xiaowei Bao
> <xiaowei.bao@nxp.com>
> Subject: Re: [PATCHv10 08/13] PCI: mobiveil: Add 8-bit and 16-bit CSR
> register accessors
>
> On Thu, Feb 13, 2020 at 12:06:39PM +0800, Zhiqiang Hou wrote:
> > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> >
> > There are some 8-bit and 16-bit registers in PCIe configuration space,
> > so add these accessors accordingly.
> >
> > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
> > Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
>
> Reviewed-by: Andrew Murray <amurray@thegoodpenguin.co.uk>
>
> > ---
> > V10:
> > - Changed the return types to reflect the size of the access.
> >
> > .../pci/controller/mobiveil/pcie-mobiveil.h | 23
> +++++++++++++++++++
> > 1 file changed, 23 insertions(+)
> >
> > diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil.h
> > b/drivers/pci/controller/mobiveil/pcie-mobiveil.h
> > index 623c5f0c4441..72c62b4d8f7b 100644
> > --- a/drivers/pci/controller/mobiveil/pcie-mobiveil.h
> > +++ b/drivers/pci/controller/mobiveil/pcie-mobiveil.h
> > @@ -182,10 +182,33 @@ static inline u32 mobiveil_csr_readl(struct
> mobiveil_pcie *pcie, u32 off)
> > return mobiveil_csr_read(pcie, off, 0x4); }
> >
> > +static inline u16 mobiveil_csr_readw(struct mobiveil_pcie *pcie, u32
> > +off) {
> > + return mobiveil_csr_read(pcie, off, 0x2); }
> > +
> > +static inline u8 mobiveil_csr_readb(struct mobiveil_pcie *pcie, u32
> > +off) {
> > + return mobiveil_csr_read(pcie, off, 0x1); }
> > +
> > +
> > static inline void mobiveil_csr_writel(struct mobiveil_pcie *pcie, u32 val,
> > u32 off)
> > {
> > mobiveil_csr_write(pcie, val, off, 0x4); }
> >
> > +static inline void mobiveil_csr_writew(struct mobiveil_pcie *pcie, u16 val,
> > + u32 off)
> > +{
> > + mobiveil_csr_write(pcie, val, off, 0x2); }
> > +
> > +static inline void mobiveil_csr_writeb(struct mobiveil_pcie *pcie, u8 val,
> > + u32 off)
> > +{
> > + mobiveil_csr_write(pcie, val, off, 0x1); }
> > +
> > #endif /* _PCIE_MOBIVEIL_H */
> > --
> > 2.17.1
> >
next prev parent reply other threads:[~2020-02-24 5:50 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-13 4:06 [PATCHv10 00/13] PCI: Recode Mobiveil driver and add PCIe Gen4 driver for NXP Layerscape SoCs Zhiqiang Hou
2020-02-13 4:06 ` [PATCHv10 01/13] PCI: mobiveil: Introduce a new structure mobiveil_root_port Zhiqiang Hou
2020-02-20 17:12 ` Andrew Murray
2020-02-24 5:45 ` Z.q. Hou
2020-02-13 4:06 ` [PATCHv10 02/13] PCI: mobiveil: Move the host initialization into a function Zhiqiang Hou
2020-02-20 17:19 ` Andrew Murray
2020-02-24 5:48 ` Z.q. Hou
2020-02-21 12:15 ` Lorenzo Pieralisi
2020-02-13 4:06 ` [PATCHv10 03/13] PCI: mobiveil: Collect the interrupt related operations " Zhiqiang Hou
2020-02-20 17:23 ` Andrew Murray
2020-02-24 5:49 ` Z.q. Hou
2020-02-13 4:06 ` [PATCHv10 04/13] PCI: mobiveil: Modularize the Mobiveil PCIe Host Bridge IP driver Zhiqiang Hou
2020-02-13 4:06 ` [PATCHv10 05/13] PCI: mobiveil: Add callback function for interrupt initialization Zhiqiang Hou
2020-02-20 17:25 ` Andrew Murray
2020-02-24 5:49 ` Z.q. Hou
2020-02-13 4:06 ` [PATCHv10 06/13] PCI: mobiveil: Add callback function for link up check Zhiqiang Hou
2020-02-13 4:06 ` [PATCHv10 07/13] PCI: mobiveil: Allow mobiveil_host_init() to be used to re-init host Zhiqiang Hou
2020-02-20 17:28 ` Andrew Murray
2020-02-24 5:49 ` Z.q. Hou
2020-02-13 4:06 ` [PATCHv10 08/13] PCI: mobiveil: Add 8-bit and 16-bit CSR register accessors Zhiqiang Hou
2020-02-20 17:29 ` Andrew Murray
2020-02-24 5:50 ` Z.q. Hou [this message]
2020-02-13 4:06 ` [PATCHv10 09/13] PCI: mobiveil: Add Header Type field check Zhiqiang Hou
2020-02-20 17:31 ` Andrew Murray
2020-02-24 5:50 ` Z.q. Hou
2020-02-13 4:06 ` [PATCHv10 10/13] dt-bindings: PCI: Add NXP Layerscape SoCs PCIe Gen4 controller Zhiqiang Hou
2020-02-13 4:06 ` [PATCHv10 11/13] PCI: mobiveil: Add PCIe Gen4 RC driver for NXP Layerscape SoCs Zhiqiang Hou
2020-02-20 17:43 ` Andrew Murray
2020-02-24 5:50 ` Z.q. Hou
2020-02-21 12:17 ` Lorenzo Pieralisi
2020-02-24 5:58 ` Z.q. Hou
2020-02-13 4:06 ` [PATCHv10 12/13] arm64: dts: lx2160a: Add PCIe controller DT nodes Zhiqiang Hou
2020-02-24 1:28 ` Shawn Guo
2020-02-24 6:11 ` Z.q. Hou
2020-02-13 4:06 ` [PATCHv10 13/13] arm64: defconfig: Enable CONFIG_PCIE_LAYERSCAPE_GEN4 Zhiqiang Hou
2020-02-24 1:29 ` Shawn Guo
2020-02-21 12:19 ` [PATCHv10 00/13] PCI: Recode Mobiveil driver and add PCIe Gen4 driver for NXP Layerscape SoCs Lorenzo Pieralisi
2020-02-24 6:07 ` Z.q. Hou
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